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ASoC: tegra-alt: remove overrides for device names

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Currently we maintain auxdata structure for Tegra210 and Tegra186. This
is nothing but a lookup table used for device names and platform data.
It is used to override device names when creating devices from DT. Since
we have moved all DAI links to DT and no more we rely on device names,
automatically generated device names should be good enough. Hence this
patch removes auxdata table and dev_set_name() calls from XBAR, AMX
drivers.

Some of the embedded platforms are using older machine utility code,
which are using these names. Hence the utility code is also updated to
use automatically generated device names.

Bug 200503387

Change-Id: I80c4fb3a5927001f58a54ca90437ec67ed14bf54
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258385
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sameer Pujar
2019-12-08 15:23:21 +05:30
parent 001188d41c
commit 7a56385cb5
4 changed files with 588 additions and 814 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
sound/soc/tegra-alt/include/tegra210_xbar_alt.h
View File

@@ -91,80 +91,6 @@
#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG) #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
/* T210 Modules Base address */
#define T210_ADMAIF_BASE_ADDR 0x702d0000
#define T210_I2S1_BASE_ADDR 0x702d1000
#define T210_I2S2_BASE_ADDR 0x702d1100
#define T210_I2S3_BASE_ADDR 0x702d1200
#define T210_I2S4_BASE_ADDR 0x702d1300
#define T210_I2S5_BASE_ADDR 0x702d1400
#define T210_AMX1_BASE_ADDR 0x702d3000
#define T210_AMX2_BASE_ADDR 0x702d3100
#define T210_ADX1_BASE_ADDR 0x702d3800
#define T210_ADX2_BASE_ADDR 0x702d3900
#define T210_AFC1_BASE_ADDR 0x702d7000
#define T210_AFC2_BASE_ADDR 0x702d7100
#define T210_AFC3_BASE_ADDR 0x702d7200
#define T210_AFC4_BASE_ADDR 0x702d7300
#define T210_AFC5_BASE_ADDR 0x702d7400
#define T210_AFC6_BASE_ADDR 0x702d7500
#define T210_SFC1_BASE_ADDR 0x702d2000
#define T210_SFC2_BASE_ADDR 0x702d2200
#define T210_SFC3_BASE_ADDR 0x702d2400
#define T210_SFC4_BASE_ADDR 0x702d2600
#define T210_MVC1_BASE_ADDR 0x702da000
#define T210_MVC2_BASE_ADDR 0x702da200
#define T210_IQC1_BASE_ADDR 0x702de000
#define T210_IQC2_BASE_ADDR 0x702de200
#define T210_DMIC1_BASE_ADDR 0x702d4000
#define T210_DMIC2_BASE_ADDR 0x702d4100
#define T210_DMIC3_BASE_ADDR 0x702d4200
#define T210_OPE1_BASE_ADDR 0x702d8000
#define T210_OPE2_BASE_ADDR 0x702d8400
#define T210_AMIXER1_BASE_ADDR 0x702dbb00
/* T186 Modules Base address */
#define T186_ADMAIF_BASE_ADDR 0x0290F000
#define T186_I2S1_BASE_ADDR 0x02901000
#define T186_I2S2_BASE_ADDR 0x02901100
#define T186_I2S3_BASE_ADDR 0x02901200
#define T186_I2S4_BASE_ADDR 0x02901300
#define T186_I2S5_BASE_ADDR 0x02901400
#define T186_I2S6_BASE_ADDR 0x02901500
#define T186_AMX1_BASE_ADDR 0x02903000
#define T186_AMX2_BASE_ADDR 0x02903100
#define T186_AMX3_BASE_ADDR 0x02903200
#define T186_AMX4_BASE_ADDR 0x02903300
#define T186_ADX1_BASE_ADDR 0x02903800
#define T186_ADX2_BASE_ADDR 0x02903900
#define T186_ADX3_BASE_ADDR 0x02903a00
#define T186_ADX4_BASE_ADDR 0x02903b00
#define T186_AFC1_BASE_ADDR 0x02907000
#define T186_AFC2_BASE_ADDR 0x02907100
#define T186_AFC3_BASE_ADDR 0x02907200
#define T186_AFC4_BASE_ADDR 0x02907300
#define T186_AFC5_BASE_ADDR 0x02907400
#define T186_AFC6_BASE_ADDR 0x02907500
#define T186_SFC1_BASE_ADDR 0x02902000
#define T186_SFC2_BASE_ADDR 0x02902200
#define T186_SFC3_BASE_ADDR 0x02902400
#define T186_SFC4_BASE_ADDR 0x02902600
#define T186_MVC1_BASE_ADDR 0x0290A000
#define T186_MVC2_BASE_ADDR 0x0290A200
#define T186_IQC1_BASE_ADDR 0x0290E000
#define T186_IQC2_BASE_ADDR 0x0290E200
#define T186_DMIC1_BASE_ADDR 0x02904000
#define T186_DMIC2_BASE_ADDR 0x02904100
#define T186_DMIC3_BASE_ADDR 0x02904200
#define T186_DMIC4_BASE_ADDR 0x02904300
#define T186_OPE1_BASE_ADDR 0x02908000
#define T186_AMIXER1_BASE_ADDR 0x0290BB00
#define T186_ASRC1_BASE_ADDR 0x02910000
#define T186_ARAD1_BASE_ADDR 0x0290E400
#define T186_DSPK1_BASE_ADDR 0x02905000
#define T186_DSPK2_BASE_ADDR 0x02905100
struct tegra210_xbar_cif_conf { struct tegra210_xbar_cif_conf {
unsigned int threshold; unsigned int threshold;
unsigned int audio_channels; unsigned int audio_channels;

6
sound/soc/tegra-alt/tegra210_amx_alt.c
View File

@@ -912,12 +912,6 @@ static int tegra210_amx_platform_probe(struct platform_device *pdev)
return ret; return ret;
} }
/* following is necessary to have the required codec-dai-name */
if (dev_set_name(&pdev->dev, "%s.%d", DRV_NAME, pdev->dev.id)) {
dev_err(&pdev->dev, "error in setting AMX dev name\n");
return -ENODEV;
}
pm_runtime_enable(&pdev->dev); pm_runtime_enable(&pdev->dev);
ret = snd_soc_register_codec(&pdev->dev, &tegra210_amx_codec, ret = snd_soc_register_codec(&pdev->dev, &tegra210_amx_codec,
tegra210_amx_dais, tegra210_amx_dais,

150
sound/soc/tegra-alt/tegra210_xbar_alt.c
View File

@@ -1110,140 +1110,6 @@ static const struct snd_soc_dapm_route tegra186_xbar_routes[] = {
IN_OUT_ROUTES("ARAD1") IN_OUT_ROUTES("ARAD1")
}; };
static struct of_dev_auxdata tegra210_xbar_auxdata[] = {
OF_DEV_AUXDATA("nvidia,tegra210-admaif", T210_ADMAIF_BASE_ADDR,
"tegra210-admaif", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T210_I2S1_BASE_ADDR,
"tegra210-i2s.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T210_I2S2_BASE_ADDR,
"tegra210-i2s.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T210_I2S3_BASE_ADDR,
"tegra210-i2s.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T210_I2S4_BASE_ADDR,
"tegra210-i2s.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T210_I2S5_BASE_ADDR,
"tegra210-i2s.4", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T210_ADX1_BASE_ADDR,
"tegra210-adx.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T210_ADX2_BASE_ADDR,
"tegra210-adx.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC1_BASE_ADDR,
"tegra210-afc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC2_BASE_ADDR,
"tegra210-afc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC3_BASE_ADDR,
"tegra210-afc.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC4_BASE_ADDR,
"tegra210-afc.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC5_BASE_ADDR,
"tegra210-afc.4", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-afc", T210_AFC6_BASE_ADDR,
"tegra210-afc.5", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T210_SFC1_BASE_ADDR,
"tegra210-sfc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T210_SFC2_BASE_ADDR,
"tegra210-sfc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T210_SFC3_BASE_ADDR,
"tegra210-sfc.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T210_SFC4_BASE_ADDR,
"tegra210-sfc.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-mvc", T210_MVC1_BASE_ADDR,
"tegra210-mvc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-mvc", T210_MVC2_BASE_ADDR,
"tegra210-mvc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-iqc", T210_IQC1_BASE_ADDR,
"tegra210-iqc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-iqc", T210_IQC2_BASE_ADDR,
"tegra210-iqc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T210_DMIC1_BASE_ADDR,
"tegra210-dmic.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T210_DMIC2_BASE_ADDR,
"tegra210-dmic.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T210_DMIC3_BASE_ADDR,
"tegra210-dmic.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-ope", T210_OPE1_BASE_ADDR,
"tegra210-ope.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-ope", T210_OPE2_BASE_ADDR,
"tegra210-ope.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-amixer", T210_AMIXER1_BASE_ADDR,
"tegra210-mixer", NULL),
{}
};
static struct of_dev_auxdata tegra186_xbar_auxdata[] = {
OF_DEV_AUXDATA("nvidia,tegra186-admaif", T186_ADMAIF_BASE_ADDR,
"tegra186-admaif", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S1_BASE_ADDR,
"tegra210-i2s.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S2_BASE_ADDR,
"tegra210-i2s.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S3_BASE_ADDR,
"tegra210-i2s.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S4_BASE_ADDR,
"tegra210-i2s.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S5_BASE_ADDR,
"tegra210-i2s.4", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-i2s", T186_I2S6_BASE_ADDR,
"tegra210-i2s.5", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T186_ADX1_BASE_ADDR,
"tegra210-adx.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T186_ADX2_BASE_ADDR,
"tegra210-adx.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T186_ADX3_BASE_ADDR,
"tegra210-adx.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-adx", T186_ADX4_BASE_ADDR,
"tegra210-adx.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC1_BASE_ADDR,
"tegra186-afc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC2_BASE_ADDR,
"tegra186-afc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC3_BASE_ADDR,
"tegra186-afc.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC4_BASE_ADDR,
"tegra186-afc.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC5_BASE_ADDR,
"tegra186-afc.4", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-afc", T186_AFC6_BASE_ADDR,
"tegra186-afc.5", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T186_SFC1_BASE_ADDR,
"tegra210-sfc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T186_SFC2_BASE_ADDR,
"tegra210-sfc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T186_SFC3_BASE_ADDR,
"tegra210-sfc.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-sfc", T186_SFC4_BASE_ADDR,
"tegra210-sfc.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-mvc", T186_MVC1_BASE_ADDR,
"tegra210-mvc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-mvc", T186_MVC2_BASE_ADDR,
"tegra210-mvc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-iqc", T186_IQC1_BASE_ADDR,
"tegra210-iqc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-iqc", T186_IQC2_BASE_ADDR,
"tegra210-iqc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T186_DMIC1_BASE_ADDR,
"tegra210-dmic.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T186_DMIC2_BASE_ADDR,
"tegra210-dmic.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T186_DMIC3_BASE_ADDR,
"tegra210-dmic.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-dmic", T186_DMIC4_BASE_ADDR,
"tegra210-dmic.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-ope", T186_OPE1_BASE_ADDR,
"tegra210-ope.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra210-amixer", T186_AMIXER1_BASE_ADDR,
"tegra210-mixer", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-asrc", T186_ASRC1_BASE_ADDR,
"tegra186-asrc", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-arad", T186_ARAD1_BASE_ADDR,
"tegra186-arad", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-dspk", T186_DSPK1_BASE_ADDR,
"tegra186-dspk.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra186-dspk", T186_DSPK2_BASE_ADDR,
"tegra186-dspk.1", NULL),
{}
};
static struct snd_soc_codec_driver tegra210_xbar_codec = { static struct snd_soc_codec_driver tegra210_xbar_codec = {
.idle_bias_off = 1, .idle_bias_off = 1,
.component_driver = { .component_driver = {
@@ -1306,10 +1172,7 @@ static int tegra210_xbar_registration(struct platform_device *pdev)
return -EBUSY; return -EBUSY;
} }
of_platform_populate(pdev->dev.of_node, NULL, tegra210_xbar_auxdata, return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
&pdev->dev);
return 0;
} }
static int tegra186_xbar_registration(struct platform_device *pdev) static int tegra186_xbar_registration(struct platform_device *pdev)
@@ -1336,10 +1199,7 @@ static int tegra186_xbar_registration(struct platform_device *pdev)
return -EBUSY; return -EBUSY;
} }
of_platform_populate(pdev->dev.of_node, NULL, tegra186_xbar_auxdata, return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
&pdev->dev);
return 0;
} }
static const struct tegra_xbar_soc_data soc_data_tegra210 = { static const struct tegra_xbar_soc_data soc_data_tegra210 = {
@@ -1375,12 +1235,6 @@ static int tegra_dev_xbar_probe(struct platform_device *pdev)
const struct of_device_id *match; const struct of_device_id *match;
struct tegra_xbar_soc_data *soc_data; struct tegra_xbar_soc_data *soc_data;
/* required to register the xbar codec with generic name */
if (dev_set_name(&pdev->dev, "%s", DRV_NAME) < 0) {
dev_err(&pdev->dev, "error in setting xbar device name\n");
return -ENODEV;
}
match = of_match_device(tegra_xbar_of_match, &pdev->dev); match = of_match_device(tegra_xbar_of_match, &pdev->dev);
if (!match) { if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n"); dev_err(&pdev->dev, "Error: No device match found\n");

1172
sound/soc/tegra-alt/utils/tegra_asoc_machine_alt.c
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