From 7df2aa44f2fa35453577ec0f28696c921fd5438d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 12 Mar 2021 17:39:49 +0000 Subject: [PATCH] drm/tegra: Add support for NVENC and NVJPG Add support for the Host1x NVENC and NVJPG engines. JIRA LS-411 Change-Id: Ied1c64c17d337e571512c053ef9552642faa430c Signed-off-by: Jon Hunter Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2490297 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/host1x/dev.c | 30 +++++++++++++++++++ .../gpu/host1x/include/linux/host1x-next.h | 3 ++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 6364f01b..429efe17 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -132,12 +132,24 @@ static const struct host1x_sid_entry tegra186_sid_table[] = { .offset = 0x30, .limit = 0x34 }, + { + /* NVENC */ + .base = 0x1af8, + .offset = 0x30, + .limit = 0x34 + }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, + { + /* NVJPG */ + .base = 0x1b08, + .offset = 0x30, + .limit = 0x34 + }, }; static const struct host1x_info host1x06_info = { @@ -162,12 +174,30 @@ static const struct host1x_sid_entry tegra194_sid_table[] = { .offset = 0x30, .limit = 0x34 }, + { + /* NVENC */ + .base = 0x1af8, + .offset = 0x30, + .limit = 0x34 + }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, + { + /* NVJPG */ + .base = 0x1b08, + .offset = 0x30, + .limit = 0x34 + }, + { + /* NVENC1 */ + .base = 0x1bb8, + .offset = 0x30, + .limit = 0x34 + }, { /* NVDEC1 */ .base = 0x1bc0, diff --git a/drivers/gpu/host1x/include/linux/host1x-next.h b/drivers/gpu/host1x/include/linux/host1x-next.h index 1ab8088b..45e0a712 100644 --- a/drivers/gpu/host1x/include/linux/host1x-next.h +++ b/drivers/gpu/host1x/include/linux/host1x-next.h @@ -13,10 +13,13 @@ enum host1x_class { HOST1X_CLASS_HOST1X = 0x1, + HOST1X_CLASS_NVENC = 0x21, + HOST1X_CLASS_NVENC1 = 0x22, HOST1X_CLASS_GR2D = 0x51, HOST1X_CLASS_GR2D_SB = 0x52, HOST1X_CLASS_VIC = 0x5D, HOST1X_CLASS_GR3D = 0x60, + HOST1X_CLASS_NVJPG = 0xC0, HOST1X_CLASS_NVDEC = 0xF0, HOST1X_CLASS_NVDEC1 = 0xF5, };