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tegra-virt-alt: Unify Mixer controls with L4T

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- Rename the mixer controls to match with L4T mixer controls.
- As most of the controls are matching between t234 and t264,
  the difference controls are added as part of component driver
  probe.
- Comment ARAD and regdump controls as ARAD and regdump are
  non-functional currently.
- Remove unused controls. MIXER, ASRC and AMX Enable controls are
  not required to be set explicitly as AudioServer handles this.

Bug 4796520

Change-Id: Ia6fdd507819b1b354544b2b1217d9aa399e106b9
Signed-off-by: Sheetal <sheetal@nvidia.com>
This commit is contained in:
Sheetal
2024-08-30 11:14:51 +00:00
committed by Jon Hunter
parent e71627a4e5
commit 7e6dc18387
4 changed files with 479 additions and 1192 deletions
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646
sound/soc/tegra-virt-alt/tegra210_virt_alt_admaif.c
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@@ -381,207 +381,60 @@ static const struct soc_enum tegra_virt_t186_arad_source =
static const struct soc_enum tegra_virt_t210_mvc_curvetype =
SOC_ENUM_SINGLE_EXT(NUM_MVC_CURVETYPE, tegra210_mvc_curve_type_text);
static const struct snd_kcontrol_new tegra_virt_t210ref_controls[] = {
MIXER_GAIN_CTRL_DECL("RX1 Gain", 0x00),
MIXER_GAIN_CTRL_DECL("RX2 Gain", 0x01),
MIXER_GAIN_CTRL_DECL("RX3 Gain", 0x02),
MIXER_GAIN_CTRL_DECL("RX4 Gain", 0x03),
MIXER_GAIN_CTRL_DECL("RX5 Gain", 0x04),
MIXER_GAIN_CTRL_DECL("RX6 Gain", 0x05),
MIXER_GAIN_CTRL_DECL("RX7 Gain", 0x06),
MIXER_GAIN_CTRL_DECL("RX8 Gain", 0x07),
MIXER_GAIN_CTRL_DECL("RX9 Gain", 0x08),
MIXER_GAIN_CTRL_DECL("RX10 Gain", 0x09),
MIXER_GAIN_INSTANT_CTRL_DECL("RX1 Gain Instant", 0x00),
MIXER_GAIN_INSTANT_CTRL_DECL("RX2 Gain Instant", 0x01),
MIXER_GAIN_INSTANT_CTRL_DECL("RX3 Gain Instant", 0x02),
MIXER_GAIN_INSTANT_CTRL_DECL("RX4 Gain Instant", 0x03),
MIXER_GAIN_INSTANT_CTRL_DECL("RX5 Gain Instant", 0x04),
MIXER_GAIN_INSTANT_CTRL_DECL("RX6 Gain Instant", 0x05),
MIXER_GAIN_INSTANT_CTRL_DECL("RX7 Gain Instant", 0x06),
MIXER_GAIN_INSTANT_CTRL_DECL("RX8 Gain Instant", 0x07),
MIXER_GAIN_INSTANT_CTRL_DECL("RX9 Gain Instant", 0x08),
MIXER_GAIN_INSTANT_CTRL_DECL("RX10 Gain Instant", 0x09),
MIXER_DURATION_CTRL_DECL("RX1 Duration", 0x00),
MIXER_DURATION_CTRL_DECL("RX2 Duration", 0x01),
MIXER_DURATION_CTRL_DECL("RX3 Duration", 0x02),
MIXER_DURATION_CTRL_DECL("RX4 Duration", 0x03),
MIXER_DURATION_CTRL_DECL("RX5 Duration", 0x04),
MIXER_DURATION_CTRL_DECL("RX6 Duration", 0x05),
MIXER_DURATION_CTRL_DECL("RX7 Duration", 0x06),
MIXER_DURATION_CTRL_DECL("RX8 Duration", 0x07),
MIXER_DURATION_CTRL_DECL("RX9 Duration", 0x08),
MIXER_DURATION_CTRL_DECL("RX10 Duration", 0x09),
MIXER_ENABLE_CTRL_DECL("Mixer Enable", 0x00),
MIXER_SET_FADE("Mixer fade", 0x00),
MIXER_GET_FADE_STATUS("Mixer fade status", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC1 input rate", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC2 input rate", 0x01),
SFC_IN_FREQ_CTRL_DECL("SFC3 input rate", 0x02),
SFC_IN_FREQ_CTRL_DECL("SFC4 input rate", 0x03),
SFC_OUT_FREQ_CTRL_DECL("SFC1 output rate", 0x00),
SFC_OUT_FREQ_CTRL_DECL("SFC2 output rate", 0x01),
SFC_OUT_FREQ_CTRL_DECL("SFC3 output rate", 0x02),
SFC_OUT_FREQ_CTRL_DECL("SFC4 output rate", 0x03),
MVC_CURVE_TYPE_CTRL_DECL("MVC1 Curve Type", 0x00,
&tegra_virt_t210_mvc_curvetype),
MVC_CURVE_TYPE_CTRL_DECL("MVC2 Curve Type", 0x01,
&tegra_virt_t210_mvc_curvetype),
MVC_TAR_VOL_CTRL_DECL("MVC1 Vol", 0x00),
MVC_TAR_VOL_CTRL_DECL("MVC2 Vol", 0x01),
MVC_MUTE_CTRL_DECL("MVC1 Mute", 0x00),
MVC_MUTE_CTRL_DECL("MVC2 Mute", 0x01),
AMX_ENABLE_CTRL_DECL("AMX1-1 Enable", 0x01, 0x01),
AMX_ENABLE_CTRL_DECL("AMX1-2 Enable", 0x01, 0x02),
AMX_ENABLE_CTRL_DECL("AMX1-3 Enable", 0x01, 0x03),
AMX_ENABLE_CTRL_DECL("AMX1-4 Enable", 0x01, 0x04),
AMX_ENABLE_CTRL_DECL("AMX2-1 Enable", 0x02, 0x01),
AMX_ENABLE_CTRL_DECL("AMX2-2 Enable", 0x02, 0x02),
AMX_ENABLE_CTRL_DECL("AMX2-3 Enable", 0x02, 0x03),
AMX_ENABLE_CTRL_DECL("AMX2-4 Enable", 0x02, 0x04),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S1 Loopback", 0x01),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S2 Loopback", 0x02),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S3 Loopback", 0x03),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S4 Loopback", 0x04),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S5 Loopback", 0x05),
REGDUMP_CTRL_DECL("ADMAIF1 regdump", ADMAIF1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF2 regdump", ADMAIF2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF3 regdump", ADMAIF3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF4 regdump", ADMAIF4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF5 regdump", ADMAIF5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF6 regdump", ADMAIF6, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF7 regdump", ADMAIF7, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF8 regdump", ADMAIF8, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF9 regdump", ADMAIF9, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF10 regdump", ADMAIF10, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX1 regdump", AMX1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX2 regdump", AMX2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX1 regdump", ADX1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX2 regdump", ADX2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MIXER1-1 RX regdump", MIXER1, 0, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-2 RX regdump", MIXER1, 1, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-3 RX regdump", MIXER1, 2, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-4 RX regdump", MIXER1, 3, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-5 RX regdump", MIXER1, 4, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-6 RX regdump", MIXER1, 5, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-7 RX regdump", MIXER1, 6, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-8 RX regdump", MIXER1, 7, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-9 RX regdump", MIXER1, 8, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-10 RX regdump", MIXER1, 9, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-1 TX regdump", MIXER1, 0, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-2 TX regdump", MIXER1, 1, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-3 TX regdump", MIXER1, 2, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-4 TX regdump", MIXER1, 3, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-5 TX regdump", MIXER1, 4, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("I2S1 regdump", I2S1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S2 regdump", I2S2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S3 regdump", I2S3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S4 regdump", I2S4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S5 regdump", I2S5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC1 regdump", SFC1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC2 regdump", SFC2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC3 regdump", SFC3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC4 regdump", SFC4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MVC1 regdump", MVC1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MVC2 regdump", MVC2, 0, NVAUDIO_REGDUMP_RX_TX),
ADMA_REGDUMP_CTRL_DECL("ADMA1 regdump", 1),
ADMA_REGDUMP_CTRL_DECL("ADMA2 regdump", 2),
ADMA_REGDUMP_CTRL_DECL("ADMA3 regdump", 3),
ADMA_REGDUMP_CTRL_DECL("ADMA4 regdump", 4),
ADMA_REGDUMP_CTRL_DECL("ADMA5 regdump", 5),
ADMA_REGDUMP_CTRL_DECL("ADMA6 regdump", 6),
ADMA_REGDUMP_CTRL_DECL("ADMA7 regdump", 7),
ADMA_REGDUMP_CTRL_DECL("ADMA8 regdump", 8),
ADMA_REGDUMP_CTRL_DECL("ADMA9 regdump", 9),
ADMA_REGDUMP_CTRL_DECL("ADMA10 regdump", 10),
ADMA_REGDUMP_CTRL_DECL("ADMA11 regdump", 11),
ADMA_REGDUMP_CTRL_DECL("ADMA12 regdump", 12),
ADMA_REGDUMP_CTRL_DECL("ADMA13 regdump", 13),
ADMA_REGDUMP_CTRL_DECL("ADMA14 regdump", 14),
ADMA_REGDUMP_CTRL_DECL("ADMA15 regdump", 15),
ADMA_REGDUMP_CTRL_DECL("ADMA16 regdump", 16),
ADMA_REGDUMP_CTRL_DECL("ADMA17 regdump", 17),
ADMA_REGDUMP_CTRL_DECL("ADMA18 regdump", 18),
ADMA_REGDUMP_CTRL_DECL("ADMA19 regdump", 19),
ADMA_REGDUMP_CTRL_DECL("ADMA20 regdump", 20),
};
static const struct snd_kcontrol_new tegra_virt_t186ref_controls[] = {
MIXER_GAIN_CTRL_DECL("RX1 Gain", 0x00),
MIXER_GAIN_CTRL_DECL("RX2 Gain", 0x01),
MIXER_GAIN_CTRL_DECL("RX3 Gain", 0x02),
MIXER_GAIN_CTRL_DECL("RX4 Gain", 0x03),
MIXER_GAIN_CTRL_DECL("RX5 Gain", 0x04),
MIXER_GAIN_CTRL_DECL("RX6 Gain", 0x05),
MIXER_GAIN_CTRL_DECL("RX7 Gain", 0x06),
MIXER_GAIN_CTRL_DECL("RX8 Gain", 0x07),
MIXER_GAIN_CTRL_DECL("RX9 Gain", 0x08),
MIXER_GAIN_CTRL_DECL("RX10 Gain", 0x09),
MIXER_GAIN_CTRL_DECL("MIXER1 RX1 Gain Volume", 0x00),
MIXER_GAIN_CTRL_DECL("MIXER1 RX2 Gain Volume", 0x01),
MIXER_GAIN_CTRL_DECL("MIXER1 RX3 Gain Volume", 0x02),
MIXER_GAIN_CTRL_DECL("MIXER1 RX4 Gain Volume", 0x03),
MIXER_GAIN_CTRL_DECL("MIXER1 RX5 Gain Volume", 0x04),
MIXER_GAIN_CTRL_DECL("MIXER1 RX6 Gain Volume", 0x05),
MIXER_GAIN_CTRL_DECL("MIXER1 RX7 Gain Volume", 0x06),
MIXER_GAIN_CTRL_DECL("MIXER1 RX8 Gain Volume", 0x07),
MIXER_GAIN_CTRL_DECL("MIXER1 RX9 Gain Volume", 0x08),
MIXER_GAIN_CTRL_DECL("MIXER1 RX10 Gain Volume", 0x09),
MIXER_GAIN_INSTANT_CTRL_DECL("RX1 Gain Instant", 0x00),
MIXER_GAIN_INSTANT_CTRL_DECL("RX2 Gain Instant", 0x01),
MIXER_GAIN_INSTANT_CTRL_DECL("RX3 Gain Instant", 0x02),
MIXER_GAIN_INSTANT_CTRL_DECL("RX4 Gain Instant", 0x03),
MIXER_GAIN_INSTANT_CTRL_DECL("RX5 Gain Instant", 0x04),
MIXER_GAIN_INSTANT_CTRL_DECL("RX6 Gain Instant", 0x05),
MIXER_GAIN_INSTANT_CTRL_DECL("RX7 Gain Instant", 0x06),
MIXER_GAIN_INSTANT_CTRL_DECL("RX8 Gain Instant", 0x07),
MIXER_GAIN_INSTANT_CTRL_DECL("RX9 Gain Instant", 0x08),
MIXER_GAIN_INSTANT_CTRL_DECL("RX10 Gain Instant", 0x09),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX1 Instant Gain Volume", 0x00),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX2 Instant Gain Volume", 0x01),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX3 Instant Gain Volume", 0x02),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX4 Instant Gain Volume", 0x03),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX5 Instant Gain Volume", 0x04),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX6 Instant Gain Volume", 0x05),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX7 Instant Gain Volume", 0x06),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX8 Instant Gain Volume", 0x07),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX9 Instant Gain Volume", 0x08),
MIXER_GAIN_INSTANT_CTRL_DECL("MIXER1 RX10 Instant Gain Volume", 0x09),
MIXER_DURATION_CTRL_DECL("RX1 Duration", 0x00),
MIXER_DURATION_CTRL_DECL("RX2 Duration", 0x01),
MIXER_DURATION_CTRL_DECL("RX3 Duration", 0x02),
MIXER_DURATION_CTRL_DECL("RX4 Duration", 0x03),
MIXER_DURATION_CTRL_DECL("RX5 Duration", 0x04),
MIXER_DURATION_CTRL_DECL("RX6 Duration", 0x05),
MIXER_DURATION_CTRL_DECL("RX7 Duration", 0x06),
MIXER_DURATION_CTRL_DECL("RX8 Duration", 0x07),
MIXER_DURATION_CTRL_DECL("RX9 Duration", 0x08),
MIXER_DURATION_CTRL_DECL("RX10 Duration", 0x09),
MIXER_DURATION_CTRL_DECL("MIXER1 RX1 Duration", 0x00),
MIXER_DURATION_CTRL_DECL("MIXER1 RX2 Duration", 0x01),
MIXER_DURATION_CTRL_DECL("MIXER1 RX3 Duration", 0x02),
MIXER_DURATION_CTRL_DECL("MIXER1 RX4 Duration", 0x03),
MIXER_DURATION_CTRL_DECL("MIXER1 RX5 Duration", 0x04),
MIXER_DURATION_CTRL_DECL("MIXER1 RX6 Duration", 0x05),
MIXER_DURATION_CTRL_DECL("MIXER1 RX7 Duration", 0x06),
MIXER_DURATION_CTRL_DECL("MIXER1 RX8 Duration", 0x07),
MIXER_DURATION_CTRL_DECL("MIXER1 RX9 Duration", 0x08),
MIXER_DURATION_CTRL_DECL("MIXER1 RX10 Duration", 0x09),
MIXER_ENABLE_CTRL_DECL("Mixer Enable", 0x00),
MIXER_SET_FADE("Mixer fade", 0x00),
MIXER_GET_FADE_STATUS("Mixer fade status", 0x00),
MIXER_SET_FADE("MIXER1 Fade", 0x00),
MIXER_GET_FADE_STATUS("MIXER1 Fade Status", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC1 input rate", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC2 input rate", 0x01),
SFC_IN_FREQ_CTRL_DECL("SFC3 input rate", 0x02),
SFC_IN_FREQ_CTRL_DECL("SFC4 input rate", 0x03),
SFC_IN_FREQ_CTRL_DECL("SFC1 Input Sample Rate", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC2 Input Sample Rate", 0x01),
SFC_IN_FREQ_CTRL_DECL("SFC3 Input Sample Rate", 0x02),
SFC_IN_FREQ_CTRL_DECL("SFC4 Input Sample Rate", 0x03),
SFC_OUT_FREQ_CTRL_DECL("SFC1 output rate", 0x00),
SFC_OUT_FREQ_CTRL_DECL("SFC2 output rate", 0x01),
SFC_OUT_FREQ_CTRL_DECL("SFC3 output rate", 0x02),
SFC_OUT_FREQ_CTRL_DECL("SFC4 output rate", 0x03),
SFC_OUT_FREQ_CTRL_DECL("SFC1 Output Sample Rate", 0x00),
SFC_OUT_FREQ_CTRL_DECL("SFC2 Output Sample Rate", 0x01),
SFC_OUT_FREQ_CTRL_DECL("SFC3 Output Sample Rate", 0x02),
SFC_OUT_FREQ_CTRL_DECL("SFC4 Output Sample Rate", 0x03),
MVC_CURVE_TYPE_CTRL_DECL("MVC1 Curve Type", 0x00,
&tegra_virt_t210_mvc_curvetype),
MVC_CURVE_TYPE_CTRL_DECL("MVC2 Curve Type", 0x01,
&tegra_virt_t210_mvc_curvetype),
MVC_TAR_VOL_CTRL_DECL("MVC1 Vol", 0x00),
MVC_TAR_VOL_CTRL_DECL("MVC2 Vol", 0x01),
MVC_TAR_VOL_CTRL_DECL("MVC1 Volume", 0x00),
MVC_TAR_VOL_CTRL_DECL("MVC2 Volume", 0x01),
MVC_MUTE_CTRL_DECL("MVC1 Mute", 0x00),
MVC_MUTE_CTRL_DECL("MVC2 Mute", 0x01),
@@ -593,47 +446,41 @@ ASRC_RATIO_CTRL_DECL("ASRC1 Ratio4", 0x04),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio5", 0x05),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio6", 0x06),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio1 SRC", 0x01,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio1 Source", 0x01,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio2 SRC", 0x02,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio2 Source", 0x02,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio3 SRC", 0x03,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio3 Source", 0x03,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio4 SRC", 0x04,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio4 Source", 0x04,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio5 SRC", 0x05,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio5 Source", 0x05,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio6 SRC", 0x06,
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio6 Source", 0x06,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream1 Enable", 0x01),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream2 Enable", 0x02),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream3 Enable", 0x03),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream4 Enable", 0x04),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream5 Enable", 0x05),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream6 Enable", 0x06),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream1 HW Component Disable", 0x01),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream2 HW Component Disable", 0x02),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream3 HW Component Disable", 0x03),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream4 HW Component Disable", 0x04),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream5 HW Component Disable", 0x05),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream6 HW Component Disable", 0x06),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream1 Hwcomp Disable", 0x01),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream2 Hwcomp Disable", 0x02),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream3 Hwcomp Disable", 0x03),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream4 Hwcomp Disable", 0x04),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream5 Hwcomp Disable", 0x05),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream6 Hwcomp Disable", 0x06),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Input Threshold", 0x01),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Input Threshold", 0x02),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Input Threshold", 0x03),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Input Threshold", 0x04),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Input Threshold", 0x05),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Input Threshold", 0x06),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Input Thresh", 0x01),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Input Thresh", 0x02),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Input Thresh", 0x03),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Input Thresh", 0x04),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Input Thresh", 0x05),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Input Thresh", 0x06),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Output Thresh", 0x01),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Output Thresh", 0x02),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Output Thresh", 0x03),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Output Thresh", 0x04),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Output Thresh", 0x05),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Output Thresh", 0x06),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Output Threshold", 0x01),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Output Threshold", 0x02),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Output Threshold", 0x03),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Output Threshold", 0x04),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Output Threshold", 0x05),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Output Threshold", 0x06),
#if TEGRA_ARAD
ARAD_LANE_SOURCE_CTRL_DECL("Numerator1 Mux", numerator1_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator2 Mux", numerator2_enum,
@@ -687,33 +534,7 @@ ARAD_LANE_RATIO_CTRL_DECL("Lane3 Ratio", 0x02),
ARAD_LANE_RATIO_CTRL_DECL("Lane4 Ratio", 0x03),
ARAD_LANE_RATIO_CTRL_DECL("Lane5 Ratio", 0x04),
ARAD_LANE_RATIO_CTRL_DECL("Lane6 Ratio", 0x05),
AMX_ENABLE_CTRL_DECL("AMX1-1 Enable", 0x01, 0x01),
AMX_ENABLE_CTRL_DECL("AMX1-2 Enable", 0x01, 0x02),
AMX_ENABLE_CTRL_DECL("AMX1-3 Enable", 0x01, 0x03),
AMX_ENABLE_CTRL_DECL("AMX1-4 Enable", 0x01, 0x04),
AMX_ENABLE_CTRL_DECL("AMX2-1 Enable", 0x02, 0x01),
AMX_ENABLE_CTRL_DECL("AMX2-2 Enable", 0x02, 0x02),
AMX_ENABLE_CTRL_DECL("AMX2-3 Enable", 0x02, 0x03),
AMX_ENABLE_CTRL_DECL("AMX2-4 Enable", 0x02, 0x04),
AMX_ENABLE_CTRL_DECL("AMX3-1 Enable", 0x03, 0x01),
AMX_ENABLE_CTRL_DECL("AMX3-2 Enable", 0x03, 0x02),
AMX_ENABLE_CTRL_DECL("AMX3-3 Enable", 0x03, 0x03),
AMX_ENABLE_CTRL_DECL("AMX3-4 Enable", 0x03, 0x04),
AMX_ENABLE_CTRL_DECL("AMX4-1 Enable", 0x04, 0x01),
AMX_ENABLE_CTRL_DECL("AMX4-2 Enable", 0x04, 0x02),
AMX_ENABLE_CTRL_DECL("AMX4-3 Enable", 0x04, 0x03),
AMX_ENABLE_CTRL_DECL("AMX4-4 Enable", 0x04, 0x04),
I2S_SET_RATE("I2S1 rate", 0x01),
I2S_SET_RATE("I2S2 rate", 0x02),
I2S_SET_RATE("I2S3 rate", 0x03),
I2S_SET_RATE("I2S4 rate", 0x04),
I2S_SET_RATE("I2S5 rate", 0x05),
I2S_SET_RATE("I2S6 rate", 0x06),
#endif
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S1 Loopback", 0x01),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S2 Loopback", 0x02),
@@ -722,6 +543,7 @@ I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S4 Loopback", 0x04),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S5 Loopback", 0x05),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S6 Loopback", 0x06),
#if TEGRA_REGDUMP
REGDUMP_CTRL_DECL("ADMAIF1 regdump", ADMAIF1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF2 regdump", ADMAIF2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF3 regdump", ADMAIF3, 0, NVAUDIO_REGDUMP_RX_TX),
@@ -831,237 +653,14 @@ ADMA_REGDUMP_CTRL_DECL("ADMA29 regdump", 29),
ADMA_REGDUMP_CTRL_DECL("ADMA30 regdump", 30),
ADMA_REGDUMP_CTRL_DECL("ADMA31 regdump", 31),
ADMA_REGDUMP_CTRL_DECL("ADMA32 regdump", 32),
#endif
};
static const struct snd_kcontrol_new tegra_virt_t264ref_controls[] = {
MIXER_GAIN_CTRL_DECL("RX1 Gain", 0x00),
MIXER_GAIN_CTRL_DECL("RX2 Gain", 0x01),
MIXER_GAIN_CTRL_DECL("RX3 Gain", 0x02),
MIXER_GAIN_CTRL_DECL("RX4 Gain", 0x03),
MIXER_GAIN_CTRL_DECL("RX5 Gain", 0x04),
MIXER_GAIN_CTRL_DECL("RX6 Gain", 0x05),
MIXER_GAIN_CTRL_DECL("RX7 Gain", 0x06),
MIXER_GAIN_CTRL_DECL("RX8 Gain", 0x07),
MIXER_GAIN_CTRL_DECL("RX9 Gain", 0x08),
MIXER_GAIN_CTRL_DECL("RX10 Gain", 0x09),
MIXER_GAIN_INSTANT_CTRL_DECL("RX1 Gain Instant", 0x00),
MIXER_GAIN_INSTANT_CTRL_DECL("RX2 Gain Instant", 0x01),
MIXER_GAIN_INSTANT_CTRL_DECL("RX3 Gain Instant", 0x02),
MIXER_GAIN_INSTANT_CTRL_DECL("RX4 Gain Instant", 0x03),
MIXER_GAIN_INSTANT_CTRL_DECL("RX5 Gain Instant", 0x04),
MIXER_GAIN_INSTANT_CTRL_DECL("RX6 Gain Instant", 0x05),
MIXER_GAIN_INSTANT_CTRL_DECL("RX7 Gain Instant", 0x06),
MIXER_GAIN_INSTANT_CTRL_DECL("RX8 Gain Instant", 0x07),
MIXER_GAIN_INSTANT_CTRL_DECL("RX9 Gain Instant", 0x08),
MIXER_GAIN_INSTANT_CTRL_DECL("RX10 Gain Instant", 0x09),
MIXER_DURATION_CTRL_DECL("RX1 Duration", 0x00),
MIXER_DURATION_CTRL_DECL("RX2 Duration", 0x01),
MIXER_DURATION_CTRL_DECL("RX3 Duration", 0x02),
MIXER_DURATION_CTRL_DECL("RX4 Duration", 0x03),
MIXER_DURATION_CTRL_DECL("RX5 Duration", 0x04),
MIXER_DURATION_CTRL_DECL("RX6 Duration", 0x05),
MIXER_DURATION_CTRL_DECL("RX7 Duration", 0x06),
MIXER_DURATION_CTRL_DECL("RX8 Duration", 0x07),
MIXER_DURATION_CTRL_DECL("RX9 Duration", 0x08),
MIXER_DURATION_CTRL_DECL("RX10 Duration", 0x09),
MIXER_ENABLE_CTRL_DECL("Mixer Enable", 0x00),
MIXER_SET_FADE("Mixer fade", 0x00),
MIXER_GET_FADE_STATUS("Mixer fade status", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC1 input rate", 0x00),
SFC_IN_FREQ_CTRL_DECL("SFC2 input rate", 0x01),
SFC_IN_FREQ_CTRL_DECL("SFC3 input rate", 0x02),
SFC_IN_FREQ_CTRL_DECL("SFC4 input rate", 0x03),
SFC_OUT_FREQ_CTRL_DECL("SFC1 output rate", 0x00),
SFC_OUT_FREQ_CTRL_DECL("SFC2 output rate", 0x01),
SFC_OUT_FREQ_CTRL_DECL("SFC3 output rate", 0x02),
SFC_OUT_FREQ_CTRL_DECL("SFC4 output rate", 0x03),
MVC_CURVE_TYPE_CTRL_DECL("MVC1 Curve Type", 0x00,
&tegra_virt_t210_mvc_curvetype),
MVC_CURVE_TYPE_CTRL_DECL("MVC2 Curve Type", 0x01,
&tegra_virt_t210_mvc_curvetype),
MVC_TAR_VOL_CTRL_DECL("MVC1 Vol", 0x00),
MVC_TAR_VOL_CTRL_DECL("MVC2 Vol", 0x01),
MVC_MUTE_CTRL_DECL("MVC1 Mute", 0x00),
MVC_MUTE_CTRL_DECL("MVC2 Mute", 0x01),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio1", 0x01),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio2", 0x02),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio3", 0x03),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio4", 0x04),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio5", 0x05),
ASRC_RATIO_CTRL_DECL("ASRC1 Ratio6", 0x06),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio1 SRC", 0x01,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio2 SRC", 0x02,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio3 SRC", 0x03,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio4 SRC", 0x04,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio5 SRC", 0x05,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_RATIO_CTRL_DECL("ASRC1 Ratio6 SRC", 0x06,
&tegra_virt_t186_asrc_source),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream1 Enable", 0x01),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream2 Enable", 0x02),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream3 Enable", 0x03),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream4 Enable", 0x04),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream5 Enable", 0x05),
ASRC_STREAM_ENABLE_CTRL_DECL("ASRC1 Stream6 Enable", 0x06),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream1 Hwcomp Disable", 0x01),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream2 Hwcomp Disable", 0x02),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream3 Hwcomp Disable", 0x03),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream4 Hwcomp Disable", 0x04),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream5 Hwcomp Disable", 0x05),
ASRC_STREAM_HWCOMP_CTRL_DECL("ASRC1 Stream6 Hwcomp Disable", 0x06),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Input Thresh", 0x01),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Input Thresh", 0x02),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Input Thresh", 0x03),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Input Thresh", 0x04),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Input Thresh", 0x05),
ASRC_STREAM_INPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Input Thresh", 0x06),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream1 Output Thresh", 0x01),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream2 Output Thresh", 0x02),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream3 Output Thresh", 0x03),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream4 Output Thresh", 0x04),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream5 Output Thresh", 0x05),
ASRC_STREAM_OUTPUT_THRESHOLD_CTRL_DECL("ASRC1 Stream6 Output Thresh", 0x06),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator1 Mux", numerator1_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator2 Mux", numerator2_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator3 Mux", numerator3_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator4 Mux", numerator4_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator5 Mux", numerator5_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Numerator6 Mux", numerator6_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator1 Mux", denominator1_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator2 Mux", denominator2_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator3 Mux", denominator3_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator4 Mux", denominator4_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator5 Mux", denominator5_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_SOURCE_CTRL_DECL("Denominator6 Mux", denominator6_enum,
&tegra_virt_t186_arad_source),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator1 Prescalar", numerator1_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator2 Prescalar", numerator2_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator3 Prescalar", numerator3_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator4 Prescalar", numerator4_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator5 Prescalar", numerator5_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Numerator6 Prescalar", numerator6_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator1 Prescalar", denominator1_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator2 Prescalar", denominator2_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator3 Prescalar", denominator3_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator4 Prescalar", denominator4_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator5 Prescalar", denominator5_enum),
ARAD_LANE_PRESCALAR_CTRL_DECL("Denominator6 Prescalar", denominator6_enum),
ARAD_LANE_ENABLE_CTRL_DECL("Lane1 enable", 0x00),
ARAD_LANE_ENABLE_CTRL_DECL("Lane2 enable", 0x01),
ARAD_LANE_ENABLE_CTRL_DECL("Lane3 enable", 0x02),
ARAD_LANE_ENABLE_CTRL_DECL("Lane4 enable", 0x03),
ARAD_LANE_ENABLE_CTRL_DECL("Lane5 enable", 0x04),
ARAD_LANE_ENABLE_CTRL_DECL("Lane6 enable", 0x05),
ARAD_LANE_RATIO_CTRL_DECL("Lane1 Ratio", 0x00),
ARAD_LANE_RATIO_CTRL_DECL("Lane2 Ratio", 0x01),
ARAD_LANE_RATIO_CTRL_DECL("Lane3 Ratio", 0x02),
ARAD_LANE_RATIO_CTRL_DECL("Lane4 Ratio", 0x03),
ARAD_LANE_RATIO_CTRL_DECL("Lane5 Ratio", 0x04),
ARAD_LANE_RATIO_CTRL_DECL("Lane6 Ratio", 0x05),
AMX_ENABLE_CTRL_DECL("AMX1-1 Enable", 0x01, 0x01),
AMX_ENABLE_CTRL_DECL("AMX1-2 Enable", 0x01, 0x02),
AMX_ENABLE_CTRL_DECL("AMX1-3 Enable", 0x01, 0x03),
AMX_ENABLE_CTRL_DECL("AMX1-4 Enable", 0x01, 0x04),
AMX_ENABLE_CTRL_DECL("AMX2-1 Enable", 0x02, 0x01),
AMX_ENABLE_CTRL_DECL("AMX2-2 Enable", 0x02, 0x02),
AMX_ENABLE_CTRL_DECL("AMX2-3 Enable", 0x02, 0x03),
AMX_ENABLE_CTRL_DECL("AMX2-4 Enable", 0x02, 0x04),
AMX_ENABLE_CTRL_DECL("AMX3-1 Enable", 0x03, 0x01),
AMX_ENABLE_CTRL_DECL("AMX3-2 Enable", 0x03, 0x02),
AMX_ENABLE_CTRL_DECL("AMX3-3 Enable", 0x03, 0x03),
AMX_ENABLE_CTRL_DECL("AMX3-4 Enable", 0x03, 0x04),
AMX_ENABLE_CTRL_DECL("AMX4-1 Enable", 0x04, 0x01),
AMX_ENABLE_CTRL_DECL("AMX4-2 Enable", 0x04, 0x02),
AMX_ENABLE_CTRL_DECL("AMX4-3 Enable", 0x04, 0x03),
AMX_ENABLE_CTRL_DECL("AMX4-4 Enable", 0x04, 0x04),
AMX_ENABLE_CTRL_DECL("AMX5-1 Enable", 0x05, 0x01),
AMX_ENABLE_CTRL_DECL("AMX5-2 Enable", 0x05, 0x02),
AMX_ENABLE_CTRL_DECL("AMX5-3 Enable", 0x05, 0x03),
AMX_ENABLE_CTRL_DECL("AMX5-4 Enable", 0x05, 0x04),
AMX_ENABLE_CTRL_DECL("AMX6-1 Enable", 0x06, 0x01),
AMX_ENABLE_CTRL_DECL("AMX6-2 Enable", 0x06, 0x02),
AMX_ENABLE_CTRL_DECL("AMX6-3 Enable", 0x06, 0x03),
AMX_ENABLE_CTRL_DECL("AMX6-4 Enable", 0x06, 0x04),
I2S_SET_RATE("I2S1 rate", 0x01),
I2S_SET_RATE("I2S2 rate", 0x02),
I2S_SET_RATE("I2S3 rate", 0x03),
I2S_SET_RATE("I2S4 rate", 0x04),
I2S_SET_RATE("I2S5 rate", 0x05),
I2S_SET_RATE("I2S6 rate", 0x06),
I2S_SET_RATE("I2S7 rate", 0x07),
I2S_SET_RATE("I2S8 rate", 0x08),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S1 Loopback", 0x01),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S2 Loopback", 0x02),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S3 Loopback", 0x03),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S4 Loopback", 0x04),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S5 Loopback", 0x05),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S6 Loopback", 0x06),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S7 Loopback", 0x07),
I2S_LOOPBACK_ENABLE_CTRL_DECL("I2S8 Loopback", 0x08),
REGDUMP_CTRL_DECL("ADMAIF1 regdump", ADMAIF1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF2 regdump", ADMAIF2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF3 regdump", ADMAIF3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF4 regdump", ADMAIF4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF5 regdump", ADMAIF5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF6 regdump", ADMAIF6, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF7 regdump", ADMAIF7, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF8 regdump", ADMAIF8, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF9 regdump", ADMAIF9, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF10 regdump", ADMAIF10, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF11 regdump", ADMAIF11, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF12 regdump", ADMAIF12, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF13 regdump", ADMAIF13, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF14 regdump", ADMAIF14, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF15 regdump", ADMAIF15, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF16 regdump", ADMAIF16, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF17 regdump", ADMAIF17, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF18 regdump", ADMAIF18, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF19 regdump", ADMAIF19, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF20 regdump", ADMAIF20, 0, NVAUDIO_REGDUMP_RX_TX),
#if TEGRA_REGDUMP
REGDUMP_CTRL_DECL("ADMAIF21 regdump", ADMAIF21, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF22 regdump", ADMAIF22, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF23 regdump", ADMAIF23, 0, NVAUDIO_REGDUMP_RX_TX),
@@ -1075,100 +674,15 @@ REGDUMP_CTRL_DECL("ADMAIF30 regdump", ADMAIF30, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF31 regdump", ADMAIF31, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADMAIF32 regdump", ADMAIF32, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX1 regdump", AMX1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX2 regdump", AMX2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX3 regdump", AMX3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX4 regdump", AMX4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX5 regdump", AMX5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("AMX6 regdump", AMX6, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX1 regdump", ADX1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX2 regdump", ADX2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX3 regdump", ADX3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX4 regdump", ADX4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX5 regdump", ADX5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ADX6 regdump", ADX6, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MIXER1-1 RX regdump", MIXER1, 0, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-2 RX regdump", MIXER1, 1, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-3 RX regdump", MIXER1, 2, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-4 RX regdump", MIXER1, 3, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-5 RX regdump", MIXER1, 4, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-6 RX regdump", MIXER1, 5, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-7 RX regdump", MIXER1, 6, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-8 RX regdump", MIXER1, 7, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-9 RX regdump", MIXER1, 8, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-10 RX regdump", MIXER1, 9, NVAUDIO_REGDUMP_RX),
REGDUMP_CTRL_DECL("MIXER1-1 TX regdump", MIXER1, 0, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-2 TX regdump", MIXER1, 1, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-3 TX regdump", MIXER1, 2, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-4 TX regdump", MIXER1, 3, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("MIXER1-5 TX regdump", MIXER1, 4, NVAUDIO_REGDUMP_TX),
REGDUMP_CTRL_DECL("I2S1 regdump", I2S1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S2 regdump", I2S2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S3 regdump", I2S3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S4 regdump", I2S4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S5 regdump", I2S5, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S6 regdump", I2S6, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S7 regdump", I2S7, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("I2S8 regdump", I2S8, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-1 regdump", ASRC1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-2 regdump", ASRC1, 1, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-3 regdump", ASRC1, 2, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-4 regdump", ASRC1, 3, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-5 regdump", ASRC1, 4, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ASRC1-6 regdump", ASRC1, 5, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC1 regdump", SFC1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC2 regdump", SFC2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC3 regdump", SFC3, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("SFC4 regdump", SFC4, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MVC1 regdump", MVC1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("MVC2 regdump", MVC2, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane1 regdump", ARAD1, 0, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane2 regdump", ARAD1, 1, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane3 regdump", ARAD1, 2, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane4 regdump", ARAD1, 3, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane5 regdump", ARAD1, 4, NVAUDIO_REGDUMP_RX_TX),
REGDUMP_CTRL_DECL("ARAD1 Lane6 regdump", ARAD1, 5, NVAUDIO_REGDUMP_RX_TX),
ADMA_REGDUMP_CTRL_DECL("ADMA1 regdump", 1),
ADMA_REGDUMP_CTRL_DECL("ADMA2 regdump", 2),
ADMA_REGDUMP_CTRL_DECL("ADMA3 regdump", 3),
ADMA_REGDUMP_CTRL_DECL("ADMA4 regdump", 4),
ADMA_REGDUMP_CTRL_DECL("ADMA5 regdump", 5),
ADMA_REGDUMP_CTRL_DECL("ADMA6 regdump", 6),
ADMA_REGDUMP_CTRL_DECL("ADMA7 regdump", 7),
ADMA_REGDUMP_CTRL_DECL("ADMA8 regdump", 8),
ADMA_REGDUMP_CTRL_DECL("ADMA9 regdump", 9),
ADMA_REGDUMP_CTRL_DECL("ADMA10 regdump", 10),
ADMA_REGDUMP_CTRL_DECL("ADMA11 regdump", 11),
ADMA_REGDUMP_CTRL_DECL("ADMA12 regdump", 12),
ADMA_REGDUMP_CTRL_DECL("ADMA13 regdump", 13),
ADMA_REGDUMP_CTRL_DECL("ADMA14 regdump", 14),
ADMA_REGDUMP_CTRL_DECL("ADMA15 regdump", 15),
ADMA_REGDUMP_CTRL_DECL("ADMA16 regdump", 16),
ADMA_REGDUMP_CTRL_DECL("ADMA17 regdump", 17),
ADMA_REGDUMP_CTRL_DECL("ADMA18 regdump", 18),
ADMA_REGDUMP_CTRL_DECL("ADMA19 regdump", 19),
ADMA_REGDUMP_CTRL_DECL("ADMA20 regdump", 20),
ADMA_REGDUMP_CTRL_DECL("ADMA21 regdump", 21),
ADMA_REGDUMP_CTRL_DECL("ADMA22 regdump", 22),
ADMA_REGDUMP_CTRL_DECL("ADMA23 regdump", 23),
ADMA_REGDUMP_CTRL_DECL("ADMA24 regdump", 24),
ADMA_REGDUMP_CTRL_DECL("ADMA25 regdump", 25),
ADMA_REGDUMP_CTRL_DECL("ADMA26 regdump", 26),
ADMA_REGDUMP_CTRL_DECL("ADMA27 regdump", 27),
ADMA_REGDUMP_CTRL_DECL("ADMA28 regdump", 28),
ADMA_REGDUMP_CTRL_DECL("ADMA29 regdump", 29),
ADMA_REGDUMP_CTRL_DECL("ADMA30 regdump", 30),
ADMA_REGDUMP_CTRL_DECL("ADMA31 regdump", 31),
ADMA_REGDUMP_CTRL_DECL("ADMA32 regdump", 32),
ADMA_REGDUMP_CTRL_DECL("ADMA33 regdump", 33),
ADMA_REGDUMP_CTRL_DECL("ADMA34 regdump", 34),
ADMA_REGDUMP_CTRL_DECL("ADMA35 regdump", 35),
@@ -1201,8 +715,21 @@ ADMA_REGDUMP_CTRL_DECL("ADMA61 regdump", 61),
ADMA_REGDUMP_CTRL_DECL("ADMA62 regdump", 62),
ADMA_REGDUMP_CTRL_DECL("ADMA63 regdump", 63),
ADMA_REGDUMP_CTRL_DECL("ADMA64 regdump", 64),
#endif
};
static int tegra210_virt_admaif_component_probe(struct snd_soc_component *component)
{
int err;
err = snd_soc_add_component_controls(component, tegra_virt_t264ref_controls,
ARRAY_SIZE(tegra_virt_t264ref_controls));
if (err)
dev_err(component->dev, "can't add T264 specific controls, err: %d\n", err);
return err;
}
static struct snd_soc_component_driver tegra210_admaif_dai_driver = {
.name = "tegra210-virt-pcm",
.controls = tegra_virt_t186ref_controls,
@@ -1210,9 +737,10 @@ static struct snd_soc_component_driver tegra210_admaif_dai_driver = {
};
static struct snd_soc_component_driver tegra264_admaif_dai_driver = {
.probe = tegra210_virt_admaif_component_probe,
.name = "tegra264-virt-pcm",
.controls = tegra_virt_t264ref_controls,
.num_controls = ARRAY_SIZE(tegra_virt_t264ref_controls),
.controls = tegra_virt_t186ref_controls,
.num_controls = ARRAY_SIZE(tegra_virt_t186ref_controls),
};
int tegra210_virt_admaif_register_component(struct platform_device *pdev,

229
sound/soc/tegra-virt-alt/tegra_asoc_util_virt_alt.c
View File

@@ -8,6 +8,7 @@
#include "tegra_virt_alt_ivc.h"
#include "tegra_asoc_util_virt_alt.h"
#if TEGRA_ARAD
const int tegra186_arad_mux_value[] = {
-1, /* None */
0, 1, 2, 3, 4, 5, /* I2S1~6 */
@@ -30,6 +31,7 @@ const char * const tegra186_arad_mux_text[] = {
"DSPK1",
"DSPK2",
};
#endif
const char * const tegra186_asrc_ratio_source_text[] = {
"ARAD",
@@ -267,60 +269,6 @@ int tegra_virt_t210mixer_set_adder_config(struct snd_kcontrol *kcontrol,
}
EXPORT_SYMBOL(tegra_virt_t210mixer_set_adder_config);
int tegra_virt_t210mixer_get_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_AMIXER_GET_ENABLE;
msg.params.amixer_info.id = 0;
msg.ack_required = true;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0)
pr_err("%s: error on ivc_send_receive\n", __func__);
ucontrol->value.integer.value[0] = msg.params.amixer_info.enable;
if (err < 0)
return err;
return 0;
}
EXPORT_SYMBOL(tegra_virt_t210mixer_get_enable);
int tegra_virt_t210mixer_set_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_AMIXER_SET_ENABLE;
msg.params.amixer_info.id = 0;
msg.params.amixer_info.enable =
ucontrol->value.integer.value[0];
msg.ack_required = true;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
return 0;
}
EXPORT_SYMBOL(tegra_virt_t210mixer_set_enable);
int tegra_virt_t210sfc_get_in_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -775,68 +723,6 @@ int tegra186_virt_asrc_set_ratio_source(struct snd_kcontrol *kcontrol,
}
EXPORT_SYMBOL(tegra186_virt_asrc_set_ratio_source);
int tegra186_virt_asrc_get_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int32_t reg = mc->reg;
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_ASRC_GET_STREAM_ENABLE;
msg.params.asrc_info.id = 0;
msg.params.asrc_info.stream_num = reg;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
ucontrol->value.integer.value[0] = msg.params.asrc_info.stream_enable;
return 0;
}
EXPORT_SYMBOL(tegra186_virt_asrc_get_stream_enable);
int tegra186_virt_asrc_set_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int32_t reg = mc->reg;
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_ASRC_SET_STREAM_ENABLE;
msg.params.asrc_info.id = 0;
msg.params.asrc_info.stream_num = reg;
msg.params.asrc_info.stream_enable =
ucontrol->value.integer.value[0];
msg.ack_required = true;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
return 0;
}
EXPORT_SYMBOL(tegra186_virt_asrc_set_stream_enable);
int tegra186_virt_asrc_get_hwcomp_disable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -1035,49 +921,7 @@ int tegra186_virt_asrc_set_output_threshold(
}
EXPORT_SYMBOL(tegra186_virt_asrc_set_output_threshold);
int tegra_virt_t210_amx_get_input_stream_enable(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return 0;
}
EXPORT_SYMBOL(tegra_virt_t210_amx_get_input_stream_enable);
int tegra_virt_t210_amx_set_input_stream_enable(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int32_t reg = mc->reg;
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_AMX_SET_INPUT_STREAM_ENABLE;
msg.params.amx_info.amx_id = ((reg) >>
MIXER_CONFIG_SHIFT_VALUE) & 0xFFFF;
msg.params.amx_info.amx_stream_id = (reg) & 0xFFFF;
msg.params.amx_info.amx_stream_enable =
ucontrol->value.integer.value[0];
msg.ack_required = true;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
return 0;
}
EXPORT_SYMBOL(tegra_virt_t210_amx_set_input_stream_enable);
#if TEGRA_ARAD
int tegra186_virt_arad_get_lane_source(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
@@ -1344,6 +1188,7 @@ int tegra186_virt_arad_get_lane_ratio(
return 0;
}
EXPORT_SYMBOL(tegra186_virt_arad_get_lane_ratio);
#endif
int tegra_virt_i2s_get_loopback_enable(
struct snd_kcontrol *kcontrol,
@@ -1409,70 +1254,7 @@ int tegra_virt_i2s_set_loopback_enable(
}
EXPORT_SYMBOL(tegra_virt_i2s_set_loopback_enable);
int tegra_virt_i2s_get_rate(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_I2S_GET_RATE;
msg.params.i2s_info.i2s_id = reg;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
ucontrol->value.integer.value[0] =
msg.params.i2s_info.i2s_rate;
return 0;
}
EXPORT_SYMBOL(tegra_virt_i2s_get_rate);
int tegra_virt_i2s_set_rate(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int32_t reg = mc->reg;
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct nvaudio_ivc_ctxt *hivc_client =
nvaudio_ivc_alloc_ctxt(card->dev);
int err;
struct nvaudio_ivc_msg msg;
memset(&msg, 0, sizeof(struct nvaudio_ivc_msg));
msg.cmd = NVAUDIO_I2S_SET_RATE;
msg.params.i2s_info.i2s_id = reg;
msg.params.i2s_info.i2s_rate =
ucontrol->value.integer.value[0];
msg.ack_required = true;
err = nvaudio_ivc_send_receive(hivc_client,
&msg,
sizeof(struct nvaudio_ivc_msg));
if (err < 0) {
pr_err("%s: error on ivc_send_receive\n", __func__);
return err;
}
return 0;
}
EXPORT_SYMBOL(tegra_virt_i2s_set_rate);
#if TEGRA_REGDUMP
int tegra_virt_t210ahub_get_regdump(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -1551,6 +1333,7 @@ int tegra_virt_t210adma_set_regdump(struct snd_kcontrol *kcontrol,
return 0;
}
EXPORT_SYMBOL(tegra_virt_t210adma_set_regdump);
#endif
//Set mixer fade
int tegra_virt_t210mixer_set_fade(struct snd_kcontrol *kcontrol,

60
sound/soc/tegra-virt-alt/tegra_asoc_util_virt_alt.h
View File

@@ -8,6 +8,10 @@
#include <sound/soc.h>
/* ARAD and Regdump controls are non-functional, hence comment them */
#define TEGRA_REGDUMP 0
#define TEGRA_ARAD 0
#define MIXER_CONFIG_SHIFT_VALUE 16
#define STREAM_ID_SHIFT_VALUE 16
#define REGDUMP_CMD_SHIFT_VALUE 24
@@ -46,12 +50,6 @@
tegra_virt_t210mixer_get_adder_config, \
tegra_virt_t210mixer_set_adder_config)
#define MIXER_ENABLE_CTRL_DECL(ename, reg) \
SOC_SINGLE_EXT(ename, reg, \
0, 1, 0, \
tegra_virt_t210mixer_get_enable, \
tegra_virt_t210mixer_set_enable)
#define SFC_IN_FREQ_CTRL_DECL(ename, id) \
SOC_SINGLE_EXT(ename, id, \
0, 192000, 0, \
@@ -103,12 +101,6 @@
tegra186_virt_asrc_get_ratio_source, \
tegra186_virt_asrc_set_ratio_source)
#define ASRC_STREAM_ENABLE_CTRL_DECL(ename, reg) \
SOC_SINGLE_EXT(ename, reg, \
0, 1, 0, \
tegra186_virt_asrc_get_stream_enable, \
tegra186_virt_asrc_set_stream_enable)
#define ASRC_STREAM_HWCOMP_CTRL_DECL(ename, reg) \
SOC_SINGLE_EXT(ename, reg, \
0, 1, 0, \
@@ -127,12 +119,7 @@
tegra186_virt_asrc_get_output_threshold, \
tegra186_virt_asrc_set_output_threshold)
#define AMX_ENABLE_CTRL_DECL(ename, reg1, reg2) \
SOC_SINGLE_EXT(ename, REG_PACK(reg1, reg2), \
0, 1, 0, \
tegra_virt_t210_amx_get_input_stream_enable, \
tegra_virt_t210_amx_set_input_stream_enable)
#if TEGRA_ARAD
#define ARAD_LANE_SOURCE_CTRL_DECL(ename, reg, src) \
SOC_ENUM_EXT_REG(ename, reg, \
src, \
@@ -155,6 +142,7 @@
SOC_SINGLE_EXT(ename, reg, \
0, 0xFFFFFFFF, 0, \
tegra186_virt_arad_get_lane_ratio, NULL)
#endif
#define I2S_LOOPBACK_ENABLE_CTRL_DECL(ename, reg) \
SOC_SINGLE_EXT(ename, reg, \
@@ -162,12 +150,6 @@
tegra_virt_i2s_get_loopback_enable, \
tegra_virt_i2s_set_loopback_enable)
#define I2S_SET_RATE(ename, reg) \
SOC_SINGLE_EXT(ename, reg, \
0, 96000, 0, \
tegra_virt_i2s_get_rate, \
tegra_virt_i2s_set_rate)
#define MIXER_SET_FADE(xname, xbase) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.info = tegra_virt_t210mixer_param_info, \
@@ -190,6 +172,7 @@
{.base = xbase, .num_regs = 128, \
.mask = SNDRV_CTL_ELEM_TYPE_INTEGER}) }
#if TEGRA_REGDUMP
#define REGDUMP_PACK(id1, id2, id3) \
(id1 | (id2 << STREAM_ID_SHIFT_VALUE) | (id3 << REGDUMP_CMD_SHIFT_VALUE))
#define REGDUMP_CTRL_DECL(ename, id, stream_id, cmd) \
@@ -203,6 +186,7 @@
0, 1, 0, \
tegra_virt_t210adma_get_regdump, \
tegra_virt_t210adma_set_regdump)
#endif
#define ADDER_CTRL_DECL(name, id) \
static const struct snd_kcontrol_new name[] = { \
@@ -279,12 +263,6 @@ int tegra_virt_t210mixer_get_adder_config(struct snd_kcontrol *kcontrol,
int tegra_virt_t210mixer_set_adder_config(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210mixer_get_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210mixer_set_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210sfc_get_in_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
@@ -324,11 +302,6 @@ int tegra186_virt_asrc_get_ratio_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra186_virt_asrc_set_ratio_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra186_virt_asrc_get_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra186_virt_asrc_set_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra186_virt_asrc_get_hwcomp_disable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
@@ -347,12 +320,7 @@ int tegra186_virt_asrc_get_output_threshold(
int tegra186_virt_asrc_set_output_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210_amx_get_input_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210_amx_set_input_stream_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
#if TEGRA_ARAD
int tegra186_virt_arad_get_lane_source(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
@@ -379,7 +347,7 @@ int tegra186_virt_arad_set_lane_enable(
int tegra186_virt_arad_get_lane_ratio(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
#endif
int tegra_virt_i2s_set_loopback_enable(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
@@ -387,12 +355,6 @@ int tegra_virt_i2s_get_loopback_enable(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_i2s_set_rate(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_i2s_get_rate(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
//Mixer fade
int tegra_virt_t210mixer_get_fade_status(
struct snd_kcontrol *kcontrol,
@@ -405,6 +367,7 @@ int tegra_virt_t210mixer_get_fade(
struct snd_ctl_elem_value *ucontrol);
int tegra_virt_t210mixer_param_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo);
#if TEGRA_REGDUMP
int tegra_virt_t210ahub_get_regdump(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
@@ -418,5 +381,6 @@ int tegra_virt_t210adma_set_regdump(
int tegra_virt_t210adma_get_regdump(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
#endif
#endif

734
sound/soc/tegra-virt-alt/tegra_asoc_xbar_virt_alt.c
View File

@@ -208,11 +208,11 @@ const char * const tegra_virt_t234ref_source_text[] = {
"SFC2",
"SFC3",
"SFC4",
"MIXER1-1",
"MIXER1-2",
"MIXER1-3",
"MIXER1-4",
"MIXER1-5",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
"AMX1",
"AMX2",
"AMX3",
@@ -238,32 +238,32 @@ const char * const tegra_virt_t234ref_source_text[] = {
"DMIC2",
"DMIC3",
"DMIC4",
"ADX1-1",
"ADX1-2",
"ADX1-3",
"ADX1-4",
"ADX2-1",
"ADX2-2",
"ADX2-3",
"ADX2-4",
"ADX3-1",
"ADX3-2",
"ADX3-3",
"ADX3-4",
"ADX4-1",
"ADX4-2",
"ADX4-3",
"ADX4-4",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"ADX3 TX1",
"ADX3 TX2",
"ADX3 TX3",
"ADX3 TX4",
"ADX4 TX1",
"ADX4 TX2",
"ADX4 TX3",
"ADX4 TX4",
"ADMAIF17",
"ADMAIF18",
"ADMAIF19",
"ADMAIF20",
"ASRC1-1",
"ASRC1-2",
"ASRC1-3",
"ASRC1-4",
"ASRC1-5",
"ASRC1-6",
"ASRC1 TX1",
"ASRC1 TX2",
"ASRC1 TX3",
"ASRC1 TX4",
"ASRC1 TX5",
"ASRC1 TX6",
};
const int tegra_virt_t264ref_source_value[] = {
@@ -399,11 +399,11 @@ const char * const tegra_virt_t264ref_source_text[] = {
"SFC2",
"SFC3",
"SFC4",
"MIXER1-1",
"MIXER1-2",
"MIXER1-3",
"MIXER1-4",
"MIXER1-5",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
"AMX1",
"AMX2",
"AMX3",
@@ -424,36 +424,36 @@ const char * const tegra_virt_t264ref_source_text[] = {
"DMIC2",
"DMIC3",
"DMIC4",
"ADX1-1",
"ADX1-2",
"ADX1-3",
"ADX1-4",
"ADX2-1",
"ADX2-2",
"ADX2-3",
"ADX2-4",
"ADX3-1",
"ADX3-2",
"ADX3-3",
"ADX3-4",
"ADX4-1",
"ADX4-2",
"ADX4-3",
"ADX4-4",
"ADX5-1",
"ADX5-2",
"ADX5-3",
"ADX5-4",
"ADX6-1",
"ADX6-2",
"ADX6-3",
"ADX6-4",
"ASRC1-1",
"ASRC1-2",
"ASRC1-3",
"ASRC1-4",
"ASRC1-5",
"ASRC1-6",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"ADX3 TX1",
"ADX3 TX2",
"ADX3 TX3",
"ADX3 TX4",
"ADX4 TX1",
"ADX4 TX2",
"ADX4 TX3",
"ADX4 TX4",
"ADX5 TX1",
"ADX5 TX2",
"ADX5 TX3",
"ADX5 TX4",
"ADX6 TX1",
"ADX6 TX2",
"ADX6 TX3",
"ADX6 TX4",
"ASRC1 TX1",
"ASRC1 TX2",
"ASRC1 TX3",
"ASRC1 TX4",
"ASRC1 TX5",
"ASRC1 TX6",
"ADMAIF17",
"ADMAIF18",
"ADMAIF19",
@@ -685,31 +685,31 @@ static struct snd_soc_dapm_widget tegra264_virt_xbar_widgets[] = {
WIDGETS("SFC2", t264_sfc2_tx),
WIDGETS("SFC3", t264_sfc3_tx),
WIDGETS("SFC4", t264_sfc4_tx),
MIXER_IN_WIDGETS("MIXER1-1", t264_mixer11_tx),
MIXER_IN_WIDGETS("MIXER1-2", t264_mixer12_tx),
MIXER_IN_WIDGETS("MIXER1-3", t264_mixer13_tx),
MIXER_IN_WIDGETS("MIXER1-4", t264_mixer14_tx),
MIXER_IN_WIDGETS("MIXER1-5", t264_mixer15_tx),
MIXER_IN_WIDGETS("MIXER1-6", t264_mixer16_tx),
MIXER_IN_WIDGETS("MIXER1-7", t264_mixer17_tx),
MIXER_IN_WIDGETS("MIXER1-8", t264_mixer18_tx),
MIXER_IN_WIDGETS("MIXER1-9", t264_mixer19_tx),
MIXER_IN_WIDGETS("MIXER1-10", t264_mixer110_tx),
MIXER_IN_WIDGETS("MIXER1 RX1", t264_mixer11_tx),
MIXER_IN_WIDGETS("MIXER1 RX2", t264_mixer12_tx),
MIXER_IN_WIDGETS("MIXER1 RX3", t264_mixer13_tx),
MIXER_IN_WIDGETS("MIXER1 RX4", t264_mixer14_tx),
MIXER_IN_WIDGETS("MIXER1 RX5", t264_mixer15_tx),
MIXER_IN_WIDGETS("MIXER1 RX6", t264_mixer16_tx),
MIXER_IN_WIDGETS("MIXER1 RX7", t264_mixer17_tx),
MIXER_IN_WIDGETS("MIXER1 RX8", t264_mixer18_tx),
MIXER_IN_WIDGETS("MIXER1 RX9", t264_mixer19_tx),
MIXER_IN_WIDGETS("MIXER1 RX10", t264_mixer110_tx),
MIXER_OUT_WIDGETS("MIXER1-1"),
MIXER_OUT_WIDGETS("MIXER1-2"),
MIXER_OUT_WIDGETS("MIXER1-3"),
MIXER_OUT_WIDGETS("MIXER1-4"),
MIXER_OUT_WIDGETS("MIXER1-5"),
SND_SOC_DAPM_MIXER("Adder1", SND_SOC_NOPM, 1, 0,
MIXER_OUT_WIDGETS("MIXER1 TX1"),
MIXER_OUT_WIDGETS("MIXER1 TX2"),
MIXER_OUT_WIDGETS("MIXER1 TX3"),
MIXER_OUT_WIDGETS("MIXER1 TX4"),
MIXER_OUT_WIDGETS("MIXER1 TX5"),
SND_SOC_DAPM_MIXER("MIXER1 Adder1", SND_SOC_NOPM, 1, 0,
Adder1, ARRAY_SIZE(Adder1)),
SND_SOC_DAPM_MIXER("Adder2", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder2", SND_SOC_NOPM, 1, 0,
Adder2, ARRAY_SIZE(Adder2)),
SND_SOC_DAPM_MIXER("Adder3", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder3", SND_SOC_NOPM, 1, 0,
Adder3, ARRAY_SIZE(Adder3)),
SND_SOC_DAPM_MIXER("Adder4", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder4", SND_SOC_NOPM, 1, 0,
Adder4, ARRAY_SIZE(Adder4)),
SND_SOC_DAPM_MIXER("Adder5", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder5", SND_SOC_NOPM, 1, 0,
Adder5, ARRAY_SIZE(Adder5)),
WIDGETS("AFC1", t264_afc1_tx),
WIDGETS("AFC2", t264_afc2_tx),
@@ -720,14 +720,14 @@ static struct snd_soc_dapm_widget tegra264_virt_xbar_widgets[] = {
WIDGETS("OPE1", t264_ope1_tx),
WIDGETS("MVC1", t264_mvc1_tx),
WIDGETS("MVC2", t264_mvc2_tx),
WIDGETS("AMX1-1", t264_amx11_tx),
WIDGETS("AMX1-2", t264_amx12_tx),
WIDGETS("AMX1-3", t264_amx13_tx),
WIDGETS("AMX1-4", t264_amx14_tx),
WIDGETS("AMX2-1", t264_amx21_tx),
WIDGETS("AMX2-2", t264_amx22_tx),
WIDGETS("AMX2-3", t264_amx23_tx),
WIDGETS("AMX2-4", t264_amx24_tx),
WIDGETS("AMX1 RX1", t264_amx11_tx),
WIDGETS("AMX1 RX2", t264_amx12_tx),
WIDGETS("AMX1 RX3", t264_amx13_tx),
WIDGETS("AMX1 RX4", t264_amx14_tx),
WIDGETS("AMX2 RX1", t264_amx21_tx),
WIDGETS("AMX2 RX2", t264_amx22_tx),
WIDGETS("AMX2 RX3", t264_amx23_tx),
WIDGETS("AMX2 RX4", t264_amx24_tx),
WIDGETS("ADX1", t264_adx1_tx),
WIDGETS("ADX2", t264_adx2_tx),
@@ -736,66 +736,66 @@ static struct snd_soc_dapm_widget tegra264_virt_xbar_widgets[] = {
TX_WIDGETS("DMIC3"),
TX_WIDGETS("DMIC4"),
TX_WIDGETS("ADX1-1"),
TX_WIDGETS("ADX1-2"),
TX_WIDGETS("ADX1-3"),
TX_WIDGETS("ADX1-4"),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2-1"),
TX_WIDGETS("ADX2-2"),
TX_WIDGETS("ADX2-3"),
TX_WIDGETS("ADX2-4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
WIDGETS("ADMAIF17", t264_admaif17_tx),
WIDGETS("ADMAIF18", t264_admaif18_tx),
WIDGETS("ADMAIF19", t264_admaif19_tx),
WIDGETS("ADMAIF20", t264_admaif20_tx),
WIDGETS("AMX3-1", t264_amx31_tx),
WIDGETS("AMX3-2", t264_amx32_tx),
WIDGETS("AMX3-3", t264_amx33_tx),
WIDGETS("AMX3-4", t264_amx34_tx),
WIDGETS("AMX4-1", t264_amx41_tx),
WIDGETS("AMX4-2", t264_amx42_tx),
WIDGETS("AMX4-3", t264_amx43_tx),
WIDGETS("AMX4-4", t264_amx44_tx),
WIDGETS("AMX5-1", t264_amx51_tx),
WIDGETS("AMX5-2", t264_amx52_tx),
WIDGETS("AMX5-3", t264_amx53_tx),
WIDGETS("AMX5-4", t264_amx54_tx),
WIDGETS("AMX6-1", t264_amx61_tx),
WIDGETS("AMX6-2", t264_amx62_tx),
WIDGETS("AMX6-3", t264_amx63_tx),
WIDGETS("AMX6-4", t264_amx64_tx),
WIDGETS("AMX3 RX1", t264_amx31_tx),
WIDGETS("AMX3 RX2", t264_amx32_tx),
WIDGETS("AMX3 RX3", t264_amx33_tx),
WIDGETS("AMX3 RX4", t264_amx34_tx),
WIDGETS("AMX4 RX1", t264_amx41_tx),
WIDGETS("AMX4 RX2", t264_amx42_tx),
WIDGETS("AMX4 RX3", t264_amx43_tx),
WIDGETS("AMX4 RX4", t264_amx44_tx),
WIDGETS("AMX5 RX1", t264_amx51_tx),
WIDGETS("AMX5 RX2", t264_amx52_tx),
WIDGETS("AMX5 RX3", t264_amx53_tx),
WIDGETS("AMX5 RX4", t264_amx54_tx),
WIDGETS("AMX6 RX1", t264_amx61_tx),
WIDGETS("AMX6 RX2", t264_amx62_tx),
WIDGETS("AMX6 RX3", t264_amx63_tx),
WIDGETS("AMX6 RX4", t264_amx64_tx),
WIDGETS("ADX3", t264_adx3_tx),
WIDGETS("ADX4", t264_adx4_tx),
WIDGETS("ADX5", t264_adx5_tx),
WIDGETS("ADX6", t264_adx6_tx),
WIDGETS("ASRC1-1", t264_asrc11_tx),
WIDGETS("ASRC1-2", t264_asrc12_tx),
WIDGETS("ASRC1-3", t264_asrc13_tx),
WIDGETS("ASRC1-4", t264_asrc14_tx),
WIDGETS("ASRC1-5", t264_asrc15_tx),
WIDGETS("ASRC1-6", t264_asrc16_tx),
WIDGETS("ASRC1 RX1", t264_asrc11_tx),
WIDGETS("ASRC1 RX2", t264_asrc12_tx),
WIDGETS("ASRC1 RX3", t264_asrc13_tx),
WIDGETS("ASRC1 RX4", t264_asrc14_tx),
WIDGETS("ASRC1 RX5", t264_asrc15_tx),
WIDGETS("ASRC1 RX6", t264_asrc16_tx),
TX_WIDGETS("ADX3-1"),
TX_WIDGETS("ADX3-2"),
TX_WIDGETS("ADX3-3"),
TX_WIDGETS("ADX3-4"),
TX_WIDGETS("ADX3 TX1"),
TX_WIDGETS("ADX3 TX2"),
TX_WIDGETS("ADX3 TX3"),
TX_WIDGETS("ADX3 TX4"),
TX_WIDGETS("ADX4-1"),
TX_WIDGETS("ADX4-2"),
TX_WIDGETS("ADX4-3"),
TX_WIDGETS("ADX4-4"),
TX_WIDGETS("ADX5-1"),
TX_WIDGETS("ADX5-2"),
TX_WIDGETS("ADX5-3"),
TX_WIDGETS("ADX5-4"),
TX_WIDGETS("ADX4 TX1"),
TX_WIDGETS("ADX4 TX2"),
TX_WIDGETS("ADX4 TX3"),
TX_WIDGETS("ADX4 TX4"),
TX_WIDGETS("ADX5 TX1"),
TX_WIDGETS("ADX5 TX2"),
TX_WIDGETS("ADX5 TX3"),
TX_WIDGETS("ADX5 TX4"),
TX_WIDGETS("ADX6-1"),
TX_WIDGETS("ADX6-2"),
TX_WIDGETS("ADX6-3"),
TX_WIDGETS("ADX6-4"),
TX_WIDGETS("ADX6 TX1"),
TX_WIDGETS("ADX6 TX2"),
TX_WIDGETS("ADX6 TX3"),
TX_WIDGETS("ADX6 TX4"),
TX_WIDGETS("AMX3"),
TX_WIDGETS("AMX4"),
TX_WIDGETS("AMX5"),
@@ -821,6 +821,12 @@ static struct snd_soc_dapm_widget tegra264_virt_xbar_widgets[] = {
WIDGETS("ADMAIF30", t264_admaif30_tx),
WIDGETS("ADMAIF31", t264_admaif31_tx),
WIDGETS("ADMAIF32", t264_admaif32_tx),
TX_WIDGETS("ASRC1 TX1"),
TX_WIDGETS("ASRC1 TX2"),
TX_WIDGETS("ASRC1 TX3"),
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
};
static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
@@ -843,31 +849,31 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
WIDGETS("SFC2", t234_sfc2_tx),
WIDGETS("SFC3", t234_sfc3_tx),
WIDGETS("SFC4", t234_sfc4_tx),
MIXER_IN_WIDGETS("MIXER1-1", t234_mixer11_tx),
MIXER_IN_WIDGETS("MIXER1-2", t234_mixer12_tx),
MIXER_IN_WIDGETS("MIXER1-3", t234_mixer13_tx),
MIXER_IN_WIDGETS("MIXER1-4", t234_mixer14_tx),
MIXER_IN_WIDGETS("MIXER1-5", t234_mixer15_tx),
MIXER_IN_WIDGETS("MIXER1-6", t234_mixer16_tx),
MIXER_IN_WIDGETS("MIXER1-7", t234_mixer17_tx),
MIXER_IN_WIDGETS("MIXER1-8", t234_mixer18_tx),
MIXER_IN_WIDGETS("MIXER1-9", t234_mixer19_tx),
MIXER_IN_WIDGETS("MIXER1-10", t234_mixer110_tx),
MIXER_IN_WIDGETS("MIXER1 RX1", t234_mixer11_tx),
MIXER_IN_WIDGETS("MIXER1 RX2", t234_mixer12_tx),
MIXER_IN_WIDGETS("MIXER1 RX3", t234_mixer13_tx),
MIXER_IN_WIDGETS("MIXER1 RX4", t234_mixer14_tx),
MIXER_IN_WIDGETS("MIXER1 RX5", t234_mixer15_tx),
MIXER_IN_WIDGETS("MIXER1 RX6", t234_mixer16_tx),
MIXER_IN_WIDGETS("MIXER1 RX7", t234_mixer17_tx),
MIXER_IN_WIDGETS("MIXER1 RX8", t234_mixer18_tx),
MIXER_IN_WIDGETS("MIXER1 RX9", t234_mixer19_tx),
MIXER_IN_WIDGETS("MIXER1 RX10", t234_mixer110_tx),
MIXER_OUT_WIDGETS("MIXER1-1"),
MIXER_OUT_WIDGETS("MIXER1-2"),
MIXER_OUT_WIDGETS("MIXER1-3"),
MIXER_OUT_WIDGETS("MIXER1-4"),
MIXER_OUT_WIDGETS("MIXER1-5"),
SND_SOC_DAPM_MIXER("Adder1", SND_SOC_NOPM, 1, 0,
MIXER_OUT_WIDGETS("MIXER1 TX1"),
MIXER_OUT_WIDGETS("MIXER1 TX2"),
MIXER_OUT_WIDGETS("MIXER1 TX3"),
MIXER_OUT_WIDGETS("MIXER1 TX4"),
MIXER_OUT_WIDGETS("MIXER1 TX5"),
SND_SOC_DAPM_MIXER("MIXER1 Adder1", SND_SOC_NOPM, 1, 0,
Adder1, ARRAY_SIZE(Adder1)),
SND_SOC_DAPM_MIXER("Adder2", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder2", SND_SOC_NOPM, 1, 0,
Adder2, ARRAY_SIZE(Adder2)),
SND_SOC_DAPM_MIXER("Adder3", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder3", SND_SOC_NOPM, 1, 0,
Adder3, ARRAY_SIZE(Adder3)),
SND_SOC_DAPM_MIXER("Adder4", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder4", SND_SOC_NOPM, 1, 0,
Adder4, ARRAY_SIZE(Adder4)),
SND_SOC_DAPM_MIXER("Adder5", SND_SOC_NOPM, 1, 0,
SND_SOC_DAPM_MIXER("MIXER1 Adder5", SND_SOC_NOPM, 1, 0,
Adder5, ARRAY_SIZE(Adder5)),
WIDGETS("AFC1", t234_afc1_tx),
WIDGETS("AFC2", t234_afc2_tx),
@@ -879,29 +885,29 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
WIDGETS("SPKPROT1", t234_spkprot_tx),
WIDGETS("MVC1", t234_mvc1_tx),
WIDGETS("MVC2", t234_mvc2_tx),
WIDGETS("AMX1-1", t234_amx11_tx),
WIDGETS("AMX1-2", t234_amx12_tx),
WIDGETS("AMX1-3", t234_amx13_tx),
WIDGETS("AMX1-4", t234_amx14_tx),
WIDGETS("AMX2-1", t234_amx21_tx),
WIDGETS("AMX2-2", t234_amx22_tx),
WIDGETS("AMX2-3", t234_amx23_tx),
WIDGETS("AMX2-4", t234_amx24_tx),
WIDGETS("AMX1 RX1", t234_amx11_tx),
WIDGETS("AMX1 RX2", t234_amx12_tx),
WIDGETS("AMX1 RX3", t234_amx13_tx),
WIDGETS("AMX1 RX4", t234_amx14_tx),
WIDGETS("AMX2 RX1", t234_amx21_tx),
WIDGETS("AMX2 RX2", t234_amx22_tx),
WIDGETS("AMX2 RX3", t234_amx23_tx),
WIDGETS("AMX2 RX4", t234_amx24_tx),
WIDGETS("ADX1", t234_adx1_tx),
WIDGETS("ADX2", t234_adx2_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
TX_WIDGETS("AMX1"),
TX_WIDGETS("ADX1-1"),
TX_WIDGETS("ADX1-2"),
TX_WIDGETS("ADX1-3"),
TX_WIDGETS("ADX1-4"),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("AMX2"),
TX_WIDGETS("ADX2-1"),
TX_WIDGETS("ADX2-2"),
TX_WIDGETS("ADX2-3"),
TX_WIDGETS("ADX2-4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
WIDGETS("ADMAIF11", t234_admaif11_tx),
WIDGETS("ADMAIF12", t234_admaif12_tx),
WIDGETS("ADMAIF13", t234_admaif13_tx),
@@ -913,32 +919,32 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
WIDGETS("ADMAIF19", t234_admaif19_tx),
WIDGETS("ADMAIF20", t234_admaif20_tx),
WIDGETS("I2S6", t234_i2s6_tx),
WIDGETS("AMX3-1", t234_amx31_tx),
WIDGETS("AMX3-2", t234_amx32_tx),
WIDGETS("AMX3-3", t234_amx33_tx),
WIDGETS("AMX3-4", t234_amx34_tx),
WIDGETS("AMX4-1", t234_amx41_tx),
WIDGETS("AMX4-2", t234_amx42_tx),
WIDGETS("AMX4-3", t234_amx43_tx),
WIDGETS("AMX4-4", t234_amx44_tx),
WIDGETS("AMX3 RX1", t234_amx31_tx),
WIDGETS("AMX3 RX2", t234_amx32_tx),
WIDGETS("AMX3 RX3", t234_amx33_tx),
WIDGETS("AMX3 RX4", t234_amx34_tx),
WIDGETS("AMX4 RX1", t234_amx41_tx),
WIDGETS("AMX4 RX2", t234_amx42_tx),
WIDGETS("AMX4 RX3", t234_amx43_tx),
WIDGETS("AMX4 RX4", t234_amx44_tx),
WIDGETS("ADX3", t234_adx3_tx),
WIDGETS("ADX4", t234_adx4_tx),
WIDGETS("ASRC1-1", t234_asrc11_tx),
WIDGETS("ASRC1-2", t234_asrc12_tx),
WIDGETS("ASRC1-3", t234_asrc13_tx),
WIDGETS("ASRC1-4", t234_asrc14_tx),
WIDGETS("ASRC1-5", t234_asrc15_tx),
WIDGETS("ASRC1-6", t234_asrc16_tx),
WIDGETS("ASRC1 RX1", t234_asrc11_tx),
WIDGETS("ASRC1 RX2", t234_asrc12_tx),
WIDGETS("ASRC1 RX3", t234_asrc13_tx),
WIDGETS("ASRC1 RX4", t234_asrc14_tx),
WIDGETS("ASRC1 RX5", t234_asrc15_tx),
WIDGETS("ASRC1 RX6", t234_asrc16_tx),
TX_WIDGETS("AMX3"),
TX_WIDGETS("ADX3-1"),
TX_WIDGETS("ADX3-2"),
TX_WIDGETS("ADX3-3"),
TX_WIDGETS("ADX3-4"),
TX_WIDGETS("ADX3 TX1"),
TX_WIDGETS("ADX3 TX2"),
TX_WIDGETS("ADX3 TX3"),
TX_WIDGETS("ADX3 TX4"),
TX_WIDGETS("AMX4"),
TX_WIDGETS("ADX4-1"),
TX_WIDGETS("ADX4-2"),
TX_WIDGETS("ADX4-3"),
TX_WIDGETS("ADX4-4"),
TX_WIDGETS("ADX4 TX1"),
TX_WIDGETS("ADX4 TX2"),
TX_WIDGETS("ADX4 TX3"),
TX_WIDGETS("ADX4 TX4"),
TX_WIDGETS("DMIC4"),
TX_WIDGETS("ARAD1"),
CODEC_WIDGET("I2S1"),
@@ -947,6 +953,12 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
CODEC_WIDGET("I2S4"),
CODEC_WIDGET("I2S5"),
CODEC_WIDGET("I2S6"),
TX_WIDGETS("ASRC1 TX1"),
TX_WIDGETS("ASRC1 TX2"),
TX_WIDGETS("ASRC1 TX3"),
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
};
#define MUX_ROUTES_234(name) \
@@ -969,11 +981,11 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "SFC2", "SFC2 RX" }, \
{ name " Mux", "SFC3", "SFC3 RX" }, \
{ name " Mux", "SFC4", "SFC4 RX" }, \
{ name " Mux", "MIXER1-1", "MIXER1-1 RX" }, \
{ name " Mux", "MIXER1-2", "MIXER1-2 RX" }, \
{ name " Mux", "MIXER1-3", "MIXER1-3 RX" }, \
{ name " Mux", "MIXER1-4", "MIXER1-4 RX" }, \
{ name " Mux", "MIXER1-5", "MIXER1-5 RX" }, \
{ name " Mux", "MIXER1 TX1", "MIXER1 TX1 RX" }, \
{ name " Mux", "MIXER1 TX2", "MIXER1 TX2 RX" }, \
{ name " Mux", "MIXER1 TX3", "MIXER1 TX3 RX" }, \
{ name " Mux", "MIXER1 TX4", "MIXER1 TX4 RX" }, \
{ name " Mux", "MIXER1 TX5", "MIXER1 TX5 RX" }, \
{ name " Mux", "AFC1", "AFC1 RX" }, \
{ name " Mux", "AFC2", "AFC2 RX" }, \
{ name " Mux", "AFC3", "AFC3 RX" }, \
@@ -987,15 +999,15 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "DMIC2", "DMIC2 RX" }, \
{ name " Mux", "DMIC3", "DMIC3 RX" }, \
{ name " Mux", "AMX1", "AMX1 RX" }, \
{ name " Mux", "ADX1-1", "ADX1-1 RX" }, \
{ name " Mux", "ADX1-2", "ADX1-2 RX" }, \
{ name " Mux", "ADX1-3", "ADX1-3 RX" }, \
{ name " Mux", "ADX1-4", "ADX1-4 RX" }, \
{ name " Mux", "ADX1 TX1", "ADX1 TX1 RX" }, \
{ name " Mux", "ADX1 TX2", "ADX1 TX2 RX" }, \
{ name " Mux", "ADX1 TX3", "ADX1 TX3 RX" }, \
{ name " Mux", "ADX1 TX4", "ADX1 TX4 RX" }, \
{ name " Mux", "AMX2", "AMX2 RX" }, \
{ name " Mux", "ADX2-1", "ADX2-1 RX" }, \
{ name " Mux", "ADX2-2", "ADX2-2 RX" }, \
{ name " Mux", "ADX2-3", "ADX2-3 RX" }, \
{ name " Mux", "ADX2-4", "ADX2-4 RX" }, \
{ name " Mux", "ADX2 TX1", "ADX2 TX1 RX" }, \
{ name " Mux", "ADX2 TX2", "ADX2 TX2 RX" }, \
{ name " Mux", "ADX2 TX3", "ADX2 TX3 RX" }, \
{ name " Mux", "ADX2 TX4", "ADX2 TX4 RX" }, \
{ name " Mux", "ADMAIF11", "ADMAIF11 RX" }, \
{ name " Mux", "ADMAIF12", "ADMAIF12 RX" }, \
{ name " Mux", "ADMAIF13", "ADMAIF13 RX" }, \
@@ -1008,35 +1020,35 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "ADMAIF20", "ADMAIF20 RX" }, \
{ name " Mux", "DMIC4", "DMIC4 RX" }, \
{ name " Mux", "I2S6", "I2S6 RX" }, \
{ name " Mux", "ASRC1-1", "ASRC1-1 RX" }, \
{ name " Mux", "ASRC1-2", "ASRC1-2 RX" }, \
{ name " Mux", "ASRC1-3", "ASRC1-3 RX" }, \
{ name " Mux", "ASRC1-4", "ASRC1-4 RX" }, \
{ name " Mux", "ASRC1-5", "ASRC1-5 RX" }, \
{ name " Mux", "ASRC1-6", "ASRC1-6 RX" }, \
{ name " Mux", "ASRC1 TX1", "ASRC1 TX1 RX" }, \
{ name " Mux", "ASRC1 TX2", "ASRC1 TX2 RX" }, \
{ name " Mux", "ASRC1 TX3", "ASRC1 TX3 RX" }, \
{ name " Mux", "ASRC1 TX4", "ASRC1 TX4 RX" }, \
{ name " Mux", "ASRC1 TX5", "ASRC1 TX5 RX" }, \
{ name " Mux", "ASRC1 TX6", "ASRC1 TX6 RX" }, \
{ name " Mux", "AMX3", "AMX3 RX" }, \
{ name " Mux", "ADX3-1", "ADX3-1 RX" }, \
{ name " Mux", "ADX3-2", "ADX3-2 RX" }, \
{ name " Mux", "ADX3-3", "ADX3-3 RX" }, \
{ name " Mux", "ADX3-4", "ADX3-4 RX" }, \
{ name " Mux", "ADX3 TX1", "ADX3 TX1 RX" }, \
{ name " Mux", "ADX3 TX2", "ADX3 TX2 RX" }, \
{ name " Mux", "ADX3 TX3", "ADX3 TX3 RX" }, \
{ name " Mux", "ADX3 TX4", "ADX3 TX4 RX" }, \
{ name " Mux", "AMX4", "AMX4 RX" }, \
{ name " Mux", "ADX4-1", "ADX4-1 RX" }, \
{ name " Mux", "ADX4-2", "ADX4-2 RX" }, \
{ name " Mux", "ADX4-3", "ADX4-3 RX" }, \
{ name " Mux", "ADX4-4", "ADX4-4 RX" }, \
{ name " Mux", "ADX4 TX1", "ADX4 TX1 RX" }, \
{ name " Mux", "ADX4 TX2", "ADX4 TX2 RX" }, \
{ name " Mux", "ADX4 TX3", "ADX4 TX3 RX" }, \
{ name " Mux", "ADX4 TX4", "ADX4 TX4 RX" }, \
{ name " Mux", "ARAD1", "ARAD1 RX" },
#define AMX_OUT_ROUTES(name) \
{ name " RX", NULL, name "-1 Mux" }, \
{ name " RX", NULL, name "-2 Mux" }, \
{ name " RX", NULL, name "-3 Mux" }, \
{ name " RX", NULL, name "-4 Mux" },
{ name " RX", NULL, name " RX1 Mux" }, \
{ name " RX", NULL, name " RX2 Mux" }, \
{ name " RX", NULL, name " RX3 Mux" }, \
{ name " RX", NULL, name " RX4 Mux" },
#define ADX_IN_ROUTES_234(name) \
{ name "-1 RX", NULL, name " Mux" }, \
{ name "-2 RX", NULL, name " Mux" }, \
{ name "-3 RX", NULL, name " Mux" }, \
{ name "-4 RX", NULL, name " Mux" }, \
{ name " TX1 RX", NULL, name " Mux" }, \
{ name " TX2 RX", NULL, name " Mux" }, \
{ name " TX3 RX", NULL, name " Mux" }, \
{ name " TX4 RX", NULL, name " Mux" }, \
TEGRA234_ROUTES(name)
#define IN_OUT_ROUTES_234(name) \
@@ -1057,17 +1069,17 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
MUX_ROUTES_234(name)
#define MIXER_ROUTES(name, id) \
{name, "RX1", "MIXER1-1 Mux",}, \
{name, "RX2", "MIXER1-2 Mux",}, \
{name, "RX3", "MIXER1-3 Mux",}, \
{name, "RX4", "MIXER1-4 Mux",}, \
{name, "RX5", "MIXER1-5 Mux",}, \
{name, "RX6", "MIXER1-6 Mux",}, \
{name, "RX7", "MIXER1-7 Mux",}, \
{name, "RX8", "MIXER1-8 Mux",}, \
{name, "RX9", "MIXER1-9 Mux",}, \
{name, "RX10", "MIXER1-10 Mux"}, \
{"MIXER1-"#id " RX", NULL, name}
{name, "RX1", "MIXER1 RX1 Mux",}, \
{name, "RX2", "MIXER1 RX2 Mux",}, \
{name, "RX3", "MIXER1 RX3 Mux",}, \
{name, "RX4", "MIXER1 RX4 Mux",}, \
{name, "RX5", "MIXER1 RX5 Mux",}, \
{name, "RX6", "MIXER1 RX6 Mux",}, \
{name, "RX7", "MIXER1 RX7 Mux",}, \
{name, "RX8", "MIXER1 RX8 Mux",}, \
{name, "RX9", "MIXER1 RX9 Mux",}, \
{name, "RX10", "MIXER1 RX10 Mux"}, \
{"MIXER1 TX"#id " RX", NULL, name}
#define MUX_ROUTES_264(name) \
{ name " Mux", "ADMAIF1", "ADMAIF1 RX" }, \
@@ -1089,11 +1101,11 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "SFC2", "SFC2 RX" }, \
{ name " Mux", "SFC3", "SFC3 RX" }, \
{ name " Mux", "SFC4", "SFC4 RX" }, \
{ name " Mux", "MIXER1-1", "MIXER1-1 RX" }, \
{ name " Mux", "MIXER1-2", "MIXER1-2 RX" }, \
{ name " Mux", "MIXER1-3", "MIXER1-3 RX" }, \
{ name " Mux", "MIXER1-4", "MIXER1-4 RX" }, \
{ name " Mux", "MIXER1-5", "MIXER1-5 RX" }, \
{ name " Mux", "MIXER1 TX1", "MIXER1 TX1 RX" }, \
{ name " Mux", "MIXER1 TX2", "MIXER1 TX2 RX" }, \
{ name " Mux", "MIXER1 TX3", "MIXER1 TX3 RX" }, \
{ name " Mux", "MIXER1 TX4", "MIXER1 TX4 RX" }, \
{ name " Mux", "MIXER1 TX5", "MIXER1 TX5 RX" }, \
{ name " Mux", "AFC1", "AFC1 RX" }, \
{ name " Mux", "AFC2", "AFC2 RX" }, \
{ name " Mux", "AFC3", "AFC3 RX" }, \
@@ -1108,15 +1120,15 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "DMIC3", "DMIC3 RX" }, \
{ name " Mux", "DMIC4", "DMIC4 RX" }, \
{ name " Mux", "AMX1", "AMX1 RX" }, \
{ name " Mux", "ADX1-1", "ADX1-1 RX" }, \
{ name " Mux", "ADX1-2", "ADX1-2 RX" }, \
{ name " Mux", "ADX1-3", "ADX1-3 RX" }, \
{ name " Mux", "ADX1-4", "ADX1-4 RX" }, \
{ name " Mux", "ADX1 TX1", "ADX1 TX1 RX" }, \
{ name " Mux", "ADX1 TX2", "ADX1 TX2 RX" }, \
{ name " Mux", "ADX1 TX3", "ADX1 TX3 RX" }, \
{ name " Mux", "ADX1 TX4", "ADX1 TX4 RX" }, \
{ name " Mux", "AMX2", "AMX2 RX" }, \
{ name " Mux", "ADX2-1", "ADX2-1 RX" }, \
{ name " Mux", "ADX2-2", "ADX2-2 RX" }, \
{ name " Mux", "ADX2-3", "ADX2-3 RX" }, \
{ name " Mux", "ADX2-4", "ADX2-4 RX" }, \
{ name " Mux", "ADX2 TX1", "ADX2 TX1 RX" }, \
{ name " Mux", "ADX2 TX2", "ADX2 TX2 RX" }, \
{ name " Mux", "ADX2 TX3", "ADX2 TX3 RX" }, \
{ name " Mux", "ADX2 TX4", "ADX2 TX4 RX" }, \
{ name " Mux", "ADMAIF11", "ADMAIF11 RX" }, \
{ name " Mux", "ADMAIF12", "ADMAIF12 RX" }, \
{ name " Mux", "ADMAIF13", "ADMAIF13 RX" }, \
@@ -1142,39 +1154,39 @@ static struct snd_soc_dapm_widget tegra234_virt_xbar_widgets[] = {
{ name " Mux", "I2S6", "I2S6 RX" }, \
{ name " Mux", "I2S7", "I2S7 RX" }, \
{ name " Mux", "I2S8", "I2S8 RX" }, \
{ name " Mux", "ASRC1-1", "ASRC1-1 RX" }, \
{ name " Mux", "ASRC1-2", "ASRC1-2 RX" }, \
{ name " Mux", "ASRC1-3", "ASRC1-3 RX" }, \
{ name " Mux", "ASRC1-4", "ASRC1-4 RX" }, \
{ name " Mux", "ASRC1-5", "ASRC1-5 RX" }, \
{ name " Mux", "ASRC1-6", "ASRC1-6 RX" }, \
{ name " Mux", "ASRC1 TX1", "ASRC1 TX1 RX" }, \
{ name " Mux", "ASRC1 TX2", "ASRC1 TX2 RX" }, \
{ name " Mux", "ASRC1 TX3", "ASRC1 TX3 RX" }, \
{ name " Mux", "ASRC1 TX4", "ASRC1 TX4 RX" }, \
{ name " Mux", "ASRC1 TX5", "ASRC1 TX5 RX" }, \
{ name " Mux", "ASRC1 TX6", "ASRC1 TX6 RX" }, \
{ name " Mux", "AMX3", "AMX3 RX" }, \
{ name " Mux", "ADX3-1", "ADX3-1 RX" }, \
{ name " Mux", "ADX3-2", "ADX3-2 RX" }, \
{ name " Mux", "ADX3-3", "ADX3-3 RX" }, \
{ name " Mux", "ADX3-4", "ADX3-4 RX" }, \
{ name " Mux", "ADX3 TX1", "ADX3 TX1 RX" }, \
{ name " Mux", "ADX3 TX2", "ADX3 TX2 RX" }, \
{ name " Mux", "ADX3 TX3", "ADX3 TX3 RX" }, \
{ name " Mux", "ADX3 TX4", "ADX3 TX4 RX" }, \
{ name " Mux", "AMX4", "AMX4 RX" }, \
{ name " Mux", "ADX4-1", "ADX4-1 RX" }, \
{ name " Mux", "ADX4-2", "ADX4-2 RX" }, \
{ name " Mux", "ADX4-3", "ADX4-3 RX" }, \
{ name " Mux", "ADX4-4", "ADX4-4 RX" }, \
{ name " Mux", "ADX4 TX1", "ADX4 TX1 RX" }, \
{ name " Mux", "ADX4 TX2", "ADX4 TX2 RX" }, \
{ name " Mux", "ADX4 TX3", "ADX4 TX3 RX" }, \
{ name " Mux", "ADX4 TX4", "ADX4 TX4 RX" }, \
{ name " Mux", "AMX5", "AMX5 RX" }, \
{ name " Mux", "ADX5-1", "ADX5-1 RX" }, \
{ name " Mux", "ADX5-2", "ADX5-2 RX" }, \
{ name " Mux", "ADX5-3", "ADX5-3 RX" }, \
{ name " Mux", "ADX5-4", "ADX5-4 RX" }, \
{ name " Mux", "ADX5 TX1", "ADX5 TX1 RX" }, \
{ name " Mux", "ADX5 TX2", "ADX5 TX2 RX" }, \
{ name " Mux", "ADX5 TX3", "ADX5 TX3 RX" }, \
{ name " Mux", "ADX5 TX4", "ADX5 TX4 RX" }, \
{ name " Mux", "AMX6", "AMX6 RX" }, \
{ name " Mux", "ADX6-1", "ADX6-1 RX" }, \
{ name " Mux", "ADX6-2", "ADX6-2 RX" }, \
{ name " Mux", "ADX6-3", "ADX6-3 RX" }, \
{ name " Mux", "ADX6-4", "ADX6-4 RX" }, \
{ name " Mux", "ADX6 TX1", "ADX6 TX1 RX" }, \
{ name " Mux", "ADX6 TX2", "ADX6 TX2 RX" }, \
{ name " Mux", "ADX6 TX3", "ADX6 TX3 RX" }, \
{ name " Mux", "ADX6 TX4", "ADX6 TX4 RX" }, \
{ name " Mux", "ARAD1", "ARAD1 RX" },
#define ADX_IN_ROUTES_264(name) \
{ name "-1 RX", NULL, name " Mux" }, \
{ name "-2 RX", NULL, name " Mux" }, \
{ name "-3 RX", NULL, name " Mux" }, \
{ name "-4 RX", NULL, name " Mux" }, \
{ name " TX1 RX", NULL, name " Mux" }, \
{ name " TX2 RX", NULL, name " Mux" }, \
{ name " TX3 RX", NULL, name " Mux" }, \
{ name " TX4 RX", NULL, name " Mux" }, \
TEGRA264_ROUTES(name)
#define IN_OUT_ROUTES_264(name) \
@@ -1214,22 +1226,22 @@ static struct snd_soc_dapm_route tegra234_virt_xbar_routes[] = {
TEGRA234_ROUTES("SFC2")
TEGRA234_ROUTES("SFC3")
TEGRA234_ROUTES("SFC4")
MIXER_IN_ROUTES_234("MIXER1-1")
MIXER_IN_ROUTES_234("MIXER1-2")
MIXER_IN_ROUTES_234("MIXER1-3")
MIXER_IN_ROUTES_234("MIXER1-4")
MIXER_IN_ROUTES_234("MIXER1-5")
MIXER_IN_ROUTES_234("MIXER1-6")
MIXER_IN_ROUTES_234("MIXER1-7")
MIXER_IN_ROUTES_234("MIXER1-8")
MIXER_IN_ROUTES_234("MIXER1-9")
MIXER_IN_ROUTES_234("MIXER1-10")
MIXER_IN_ROUTES_234("MIXER1 RX1")
MIXER_IN_ROUTES_234("MIXER1 RX2")
MIXER_IN_ROUTES_234("MIXER1 RX3")
MIXER_IN_ROUTES_234("MIXER1 RX4")
MIXER_IN_ROUTES_234("MIXER1 RX5")
MIXER_IN_ROUTES_234("MIXER1 RX6")
MIXER_IN_ROUTES_234("MIXER1 RX7")
MIXER_IN_ROUTES_234("MIXER1 RX8")
MIXER_IN_ROUTES_234("MIXER1 RX9")
MIXER_IN_ROUTES_234("MIXER1 RX10")
MIXER_ROUTES("Adder1", 1),
MIXER_ROUTES("Adder2", 2),
MIXER_ROUTES("Adder3", 3),
MIXER_ROUTES("Adder4", 4),
MIXER_ROUTES("Adder5", 5),
MIXER_ROUTES("MIXER1 Adder1", 1),
MIXER_ROUTES("MIXER1 Adder2", 2),
MIXER_ROUTES("MIXER1 Adder3", 3),
MIXER_ROUTES("MIXER1 Adder4", 4),
MIXER_ROUTES("MIXER1 Adder5", 5),
TEGRA234_ROUTES("AFC1")
TEGRA234_ROUTES("AFC2")
@@ -1241,14 +1253,14 @@ static struct snd_soc_dapm_route tegra234_virt_xbar_routes[] = {
TEGRA234_ROUTES("SPKPROT1")
TEGRA234_ROUTES("MVC1")
TEGRA234_ROUTES("MVC2")
TEGRA234_ROUTES("AMX1-1")
TEGRA234_ROUTES("AMX1-2")
TEGRA234_ROUTES("AMX1-3")
TEGRA234_ROUTES("AMX1-4")
TEGRA234_ROUTES("AMX2-1")
TEGRA234_ROUTES("AMX2-2")
TEGRA234_ROUTES("AMX2-3")
TEGRA234_ROUTES("AMX2-4")
TEGRA234_ROUTES("AMX1 RX1")
TEGRA234_ROUTES("AMX1 RX2")
TEGRA234_ROUTES("AMX1 RX3")
TEGRA234_ROUTES("AMX1 RX4")
TEGRA234_ROUTES("AMX2 RX1")
TEGRA234_ROUTES("AMX2 RX2")
TEGRA234_ROUTES("AMX2 RX3")
TEGRA234_ROUTES("AMX2 RX4")
ADX_IN_ROUTES_234("ADX1")
ADX_IN_ROUTES_234("ADX2")
AMX_OUT_ROUTES("AMX1")
@@ -1263,23 +1275,23 @@ static struct snd_soc_dapm_route tegra234_virt_xbar_routes[] = {
IN_OUT_ROUTES_234("ADMAIF18")
IN_OUT_ROUTES_234("ADMAIF19")
IN_OUT_ROUTES_234("ADMAIF20")
TEGRA234_ROUTES("AMX3-1")
TEGRA234_ROUTES("AMX3-2")
TEGRA234_ROUTES("AMX3-3")
TEGRA234_ROUTES("AMX3-4")
TEGRA234_ROUTES("AMX4-1")
TEGRA234_ROUTES("AMX4-2")
TEGRA234_ROUTES("AMX4-3")
TEGRA234_ROUTES("AMX4-4")
TEGRA234_ROUTES("AMX3 RX1")
TEGRA234_ROUTES("AMX3 RX2")
TEGRA234_ROUTES("AMX3 RX3")
TEGRA234_ROUTES("AMX3 RX4")
TEGRA234_ROUTES("AMX4 RX1")
TEGRA234_ROUTES("AMX4 RX2")
TEGRA234_ROUTES("AMX4 RX3")
TEGRA234_ROUTES("AMX4 RX4")
ADX_IN_ROUTES_234("ADX3")
ADX_IN_ROUTES_234("ADX4")
MIC_SPK_ROUTES_234("I2S6")
TEGRA234_ROUTES("ASRC1-1")
TEGRA234_ROUTES("ASRC1-2")
TEGRA234_ROUTES("ASRC1-3")
TEGRA234_ROUTES("ASRC1-4")
TEGRA234_ROUTES("ASRC1-5")
TEGRA234_ROUTES("ASRC1-6")
TEGRA234_ROUTES("ASRC1 RX1")
TEGRA234_ROUTES("ASRC1 RX2")
TEGRA234_ROUTES("ASRC1 RX3")
TEGRA234_ROUTES("ASRC1 RX4")
TEGRA234_ROUTES("ASRC1 RX5")
TEGRA234_ROUTES("ASRC1 RX6")
AMX_OUT_ROUTES("AMX3")
AMX_OUT_ROUTES("AMX4")
};
@@ -1313,51 +1325,51 @@ static struct snd_soc_dapm_route tegra264_virt_xbar_routes[] = {
TEGRA264_ROUTES("SFC2")
TEGRA264_ROUTES("SFC3")
TEGRA264_ROUTES("SFC4")
MIXER_IN_ROUTES_264("MIXER1-1")
MIXER_IN_ROUTES_264("MIXER1-2")
MIXER_IN_ROUTES_264("MIXER1-3")
MIXER_IN_ROUTES_264("MIXER1-4")
MIXER_IN_ROUTES_264("MIXER1-5")
MIXER_IN_ROUTES_264("MIXER1-6")
MIXER_IN_ROUTES_264("MIXER1-7")
MIXER_IN_ROUTES_264("MIXER1-8")
MIXER_IN_ROUTES_264("MIXER1-9")
MIXER_IN_ROUTES_264("MIXER1-10")
MIXER_ROUTES("Adder1", 1),
MIXER_ROUTES("Adder2", 2),
MIXER_ROUTES("Adder3", 3),
MIXER_ROUTES("Adder4", 4),
MIXER_ROUTES("Adder5", 5),
MIXER_IN_ROUTES_264("MIXER1 RX1")
MIXER_IN_ROUTES_264("MIXER1 RX2")
MIXER_IN_ROUTES_264("MIXER1 RX3")
MIXER_IN_ROUTES_264("MIXER1 RX4")
MIXER_IN_ROUTES_264("MIXER1 RX5")
MIXER_IN_ROUTES_264("MIXER1 RX6")
MIXER_IN_ROUTES_264("MIXER1 RX7")
MIXER_IN_ROUTES_264("MIXER1 RX8")
MIXER_IN_ROUTES_264("MIXER1 RX9")
MIXER_IN_ROUTES_264("MIXER1 RX10")
MIXER_ROUTES("MIXER1 Adder1", 1),
MIXER_ROUTES("MIXER1 Adder2", 2),
MIXER_ROUTES("MIXER1 Adder3", 3),
MIXER_ROUTES("MIXER1 Adder4", 4),
MIXER_ROUTES("MIXER1 Adder5", 5),
AMX_OUT_ROUTES("AMX1")
AMX_OUT_ROUTES("AMX2")
AMX_OUT_ROUTES("AMX3")
AMX_OUT_ROUTES("AMX4")
AMX_OUT_ROUTES("AMX5")
AMX_OUT_ROUTES("AMX6")
TEGRA264_ROUTES("AMX1-1")
TEGRA264_ROUTES("AMX1-2")
TEGRA264_ROUTES("AMX1-3")
TEGRA264_ROUTES("AMX1-4")
TEGRA264_ROUTES("AMX2-1")
TEGRA264_ROUTES("AMX2-2")
TEGRA264_ROUTES("AMX2-3")
TEGRA264_ROUTES("AMX2-4")
TEGRA264_ROUTES("AMX3-1")
TEGRA264_ROUTES("AMX3-2")
TEGRA264_ROUTES("AMX3-3")
TEGRA264_ROUTES("AMX3-4")
TEGRA264_ROUTES("AMX4-1")
TEGRA264_ROUTES("AMX4-2")
TEGRA264_ROUTES("AMX4-3")
TEGRA264_ROUTES("AMX4-4")
TEGRA264_ROUTES("AMX5-1")
TEGRA264_ROUTES("AMX5-2")
TEGRA264_ROUTES("AMX5-3")
TEGRA264_ROUTES("AMX5-4")
TEGRA264_ROUTES("AMX6-1")
TEGRA264_ROUTES("AMX6-2")
TEGRA264_ROUTES("AMX6-3")
TEGRA264_ROUTES("AMX6-4")
TEGRA264_ROUTES("AMX1 RX1")
TEGRA264_ROUTES("AMX1 RX2")
TEGRA264_ROUTES("AMX1 RX3")
TEGRA264_ROUTES("AMX1 RX4")
TEGRA264_ROUTES("AMX2 RX1")
TEGRA264_ROUTES("AMX2 RX2")
TEGRA264_ROUTES("AMX2 RX3")
TEGRA264_ROUTES("AMX2 RX4")
TEGRA264_ROUTES("AMX3 RX1")
TEGRA264_ROUTES("AMX3 RX2")
TEGRA264_ROUTES("AMX3 RX3")
TEGRA264_ROUTES("AMX3 RX4")
TEGRA264_ROUTES("AMX4 RX1")
TEGRA264_ROUTES("AMX4 RX2")
TEGRA264_ROUTES("AMX4 RX3")
TEGRA264_ROUTES("AMX4 RX4")
TEGRA264_ROUTES("AMX5 RX1")
TEGRA264_ROUTES("AMX5 RX2")
TEGRA264_ROUTES("AMX5 RX3")
TEGRA264_ROUTES("AMX5 RX4")
TEGRA264_ROUTES("AMX6 RX1")
TEGRA264_ROUTES("AMX6 RX2")
TEGRA264_ROUTES("AMX6 RX3")
TEGRA264_ROUTES("AMX6 RX4")
TEGRA264_ROUTES("AFC1")
TEGRA264_ROUTES("AFC2")
TEGRA264_ROUTES("AFC3")
@@ -1373,12 +1385,12 @@ static struct snd_soc_dapm_route tegra264_virt_xbar_routes[] = {
ADX_IN_ROUTES_264("ADX4")
ADX_IN_ROUTES_264("ADX5")
ADX_IN_ROUTES_264("ADX6")
TEGRA264_ROUTES("ASRC1-1")
TEGRA264_ROUTES("ASRC1-2")
TEGRA264_ROUTES("ASRC1-3")
TEGRA264_ROUTES("ASRC1-4")
TEGRA264_ROUTES("ASRC1-5")
TEGRA264_ROUTES("ASRC1-6")
TEGRA264_ROUTES("ASRC1 RX1")
TEGRA264_ROUTES("ASRC1 RX2")
TEGRA264_ROUTES("ASRC1 RX3")
TEGRA264_ROUTES("ASRC1 RX4")
TEGRA264_ROUTES("ASRC1 RX5")
TEGRA264_ROUTES("ASRC1 RX6")
IN_OUT_ROUTES_264("ADMAIF17")
IN_OUT_ROUTES_264("ADMAIF18")
IN_OUT_ROUTES_264("ADMAIF19")