From 7fec719a7ce8c6c4c88edbda42cee3ec774e1db0 Mon Sep 17 00:00:00 2001 From: Sanath Kumar Gampa Date: Tue, 15 Apr 2025 05:15:30 -0700 Subject: [PATCH] nvethernet:Move blocking MACSec in PHY to server Removed the below functionality from Linux OSD as we moved the same to ethernet server to avoid implementation in QNX OSD - Restrict enabling MACSec in PHY Bug 5221921 Change-Id: I0cbdeccfe91a67060a4609b9b8bc2bf842547b99 Signed-off-by: Sanath Kumar Gampa Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3341020 Reviewed-by: Narayana Reddy P Reviewed-by: Srinivas Ramachandran Reviewed-by: svcacv Reviewed-by: Bhadram Varka GVS: buildbot_gerritrpt --- .../ethernet/nvidia/nvethernet/ether_linux.c | 46 ------------------- .../ethernet/nvidia/nvethernet/ether_linux.h | 8 ---- 2 files changed, 54 deletions(-) diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c index 66adfa7c..637fbc6f 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c @@ -2900,26 +2900,6 @@ static int ether_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, "%s:No clks available, skipping PHY write\n", __func__); return -ENODEV; } - if (pdata->phy_str != NULL) { - // For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl - if (strcmp(pdata->phy_str, "MVQ3244") == 0) { - if ((phyreg == MACSEC_REG_MVQ3244) && ((phydata & OSI_BIT(1)) == 0U)) { - dev_err(pdata->dev, - "restricting access to enable macsec in MVQ3244 PHY \n"); - return -ENODEV; - } - // For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008 - } else if (strcmp(pdata->phy_str, "88Q2221M") == 0) { - if ((phyaddr == MACSEC_REG_88Q2221M) && - (((phydata & OSI_BIT(5)) == 0U) || ((phydata & OSI_BIT(6)) == 0U))) { - dev_err(pdata->dev, - "restricting access to enable macsec in 88Q221M PHY \n"); - return -ENODEV; - } - } else { - /** Do Nothing for other PHY types */ - } - } return osi_write_phy_reg(pdata->osi_core, (unsigned int)phyaddr, (unsigned int)phyreg, phydata); @@ -4371,29 +4351,6 @@ static int ether_handle_priv_wmdio_ioctl(struct ether_priv_data *pdata, prtad = mdio_phy_id_prtad(mii_data->phy_id); devad = mdio_phy_id_devad(mii_data->phy_id); devad = ether_mdio_c45_addr(devad, mii_data->reg_num); - - if (pdata->phy_str != NULL) { - // For MV-Q3244 0x401e002a is pointing to 0x407C2780 value pointed by Sau Loh from Mrvl - if (strcmp(pdata->phy_str, "MVQ3244") == 0) { - if ((devad == MACSEC_REG_MVQ3244) && - ((mii_data->val_in & OSI_BIT(1)) == 0U)) { - dev_err(pdata->dev, - "restricting access to enable macsec in MVQ3244 PHY \n"); - return -ENODEV; - } - // For 88Q2221M dev 0x1F and Register 0xa008 is pointed to 0x401fa008 - } else if (strcmp(pdata->phy_str, "88Q2221M") == 0) { - if ((devad == MACSEC_REG_88Q2221M) && - (((mii_data->val_in & OSI_BIT(5)) == 0U) || - ((mii_data->val_in & OSI_BIT(6)) == 0U))) { - dev_err(pdata->dev, - "restricting access to enable macsec in 88Q2221M PHY \n"); - return -ENODEV; - } - } else { - /** Do Nothing for other PHY types */ - } - } } else { prtad = mii_data->phy_id; devad = mii_data->reg_num; @@ -7482,9 +7439,6 @@ int ether_probe(struct platform_device *pdev) } } - /* Read PHY type from DT */ - (void)of_property_read_string(pdata->dev->of_node, - "nvidia,phy_type", &pdata->phy_str); /* Set netdev features based on hw features */ ether_set_ndev_features(ndev, pdata); diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h index 668b1f5a..8c1634cc 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h @@ -264,12 +264,6 @@ */ #define FIXED_PHY_INVALID_MDIO_ADDR 0xFFU -/** - * @brief PHY register address to enable MACSEc feature in PHY - */ -#define MACSEC_REG_MVQ3244 0x401e002aU -#define MACSEC_REG_88Q2221M 0x401fa008U - #define ETHER_ADDRESS_32BIT 0 #define ETHER_ADDRESS_40BIT 1 #define ETHER_ADDRESS_48BIT 2 @@ -691,8 +685,6 @@ struct ether_priv_data { int phy_reset_post_delay; /** PHY reset duration delay */ int phy_reset_duration; - /** Pointer to the phy type being used */ - const char *phy_str; #ifdef ETHER_NVGRO /** Master queue */ struct sk_buff_head mq;