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ASoC: tegra: add clk_prepare/clk_unprepare

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Use clk_prepare/clk_unprepare as required by the generic clk framework.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Prashant Gaikwad
2012-06-05 09:59:42 +05:30
committed by Sameer Pujar
parent bb86c1ecb3
commit 840703a965
1 changed files with 6 additions and 6 deletions
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12
sound/soc/tegra/tegra_asoc_utils.c
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@@ -69,9 +69,9 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
data->set_baseclock = 0; data->set_baseclock = 0;
data->set_mclk = 0; data->set_mclk = 0;
clk_disable(data->clk_cdev1); clk_disable_unprepare(data->clk_cdev1);
clk_disable(data->clk_pll_a_out0); clk_disable_unprepare(data->clk_pll_a_out0);
clk_disable(data->clk_pll_a); clk_disable_unprepare(data->clk_pll_a);
err = clk_set_rate(data->clk_pll_a, new_baseclock); err = clk_set_rate(data->clk_pll_a, new_baseclock);
if (err) { if (err) {
@@ -87,19 +87,19 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
err = clk_enable(data->clk_pll_a); err = clk_prepare_enable(data->clk_pll_a);
if (err) { if (err) {
dev_err(data->dev, "Can't enable pll_a: %d\n", err); dev_err(data->dev, "Can't enable pll_a: %d\n", err);
return err; return err;
} }
err = clk_enable(data->clk_pll_a_out0); err = clk_prepare_enable(data->clk_pll_a_out0);
if (err) { if (err) {
dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
return err; return err;
} }
err = clk_enable(data->clk_cdev1); err = clk_prepare_enable(data->clk_cdev1);
if (err) { if (err) {
dev_err(data->dev, "Can't enable cdev1: %d\n", err); dev_err(data->dev, "Can't enable cdev1: %d\n", err);
return err; return err;