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documentation: Add DT binding document for central activity monitor
Add Device Tree binding document for the NVIDIA Tegra central activity monitor device. Bug 3625675 Change-Id: I85dc848b561802dd749f59c0a57654264f83f082 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2705397 GVS: Gerrit_Virtual_Submit
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Documentation/devicetree/bindings/soc/nvidia/tegra/cactmon.yaml
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Documentation/devicetree/bindings/soc/nvidia/tegra/cactmon.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/nvidia/tegra/cactmon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Device tree binding for NVIDIA Tegra central actmon
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maintainers:
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- Laxman Dewangan <ldewangan@nvidia.com>
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description: |
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The Tegra central actmon is the device to monitor activity of various hw devices,
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for e.g. external memory controller hw. It has dedicated actmon device to capture
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activity of each EMC client. Emc clients can be added as child node to parent node.
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For e.g. "mc_all" is one of the client of emc and captures rd/wr memory access by
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all the emc clients. Therefore "mc_all" can be added as child node of the
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"nvidia,tegra<hw>-cactmon" node.
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properties:
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compatible:
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enum:
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- nvidia,tegra234-cactmon
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- nvidia,tegra194-cactmon
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- nvidia,tegra186-cactmon
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reg:
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maxItems: 1
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description: |
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Physical base address and length of registers for actmon HW.
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interrupts:
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maxItems: 1
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description: |
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IRQ number for actmon HW.
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clocks:
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maxItems: 1
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description: |
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Specifies the actmon hw ref clock.
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clock-names:
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description: |
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Specifies the name actmon hw ref clock. Valid name is "actmon".
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resets:
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maxItems: 1
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description: |
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Specifies the reset line.
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reset-names:
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description: |
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Specifies the name of the reset line. Valid name is "actmon_rst".
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nvidia,sample_period:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Actmon sample period.
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required:
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- compatible
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- interrupts
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- nvidia,sample_period
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unevaluatedProperties: false
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patternProperties:
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"^.*-actdev$":
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type: object
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description: |
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Actmon devices for mc clients.
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properties:
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clocks:
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maxItems: 1
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description: |
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Specifies the submodule HW ref clock.
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clock-names:
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description: |
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Specifies the name actmon hw ref clock. Valid name is "actmon".
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nvidia,reg_offs:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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register offset for actmon device
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nvidia,irq_mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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irq mask for actmon debvice.
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nvidia,suspend_freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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actmon device freq when mc client goes in suspend
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nvidia,boost_freq_step:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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base freq of boost freq component
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nvidia,boost_up_coef:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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percentage of times want to boost up the freq
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nvidia,boost_down_coef:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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percentage of times want to boost down the freq
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nvidia,boost_up_threshold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Up threshold, crossing that boost up interrupt triggeres
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nvidia,boost_down_threshold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Down threshold, crossing that boost down interrupt triggeres
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nvidia,up_wmark_window:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Count crossing that many times of boost_up_threshold, boost interrupt triggeres
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nvidia,down_wmark_window:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Count crossing that many times of boost_up_threshold, boost interrupt triggeres
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nvidia,avg_window_log2:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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K value for moving average of 2^k windows
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nvidia,count_weight:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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scaling factor
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nvidia,type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Freq sampler or Load sampler.
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nvidia,max_dram_channels:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Number of DRAM channels if it is MC client.
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required:
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- clocks
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- clock-names
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- nvidia,reg_offs
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- nvidia,irq_mask
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#define TEGRA234_IRQ_ACTMON 210
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#define TEGRA234_RESET_ACTMON 1U
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#define TEGRA234_CLK_ACTMON 1U
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#define TEGRA234_CLK_EMC 31U
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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actmon@d230000 {
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/* tegra194 central actmon */
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compatible = "nvidia,tegra234-cactmon";
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reg = <0x0 0x0d230000 0x0 0x1000>; /* ACTMON_BASE */
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interrupts = <0 TEGRA234_IRQ_ACTMON IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp_clks TEGRA234_CLK_ACTMON>;
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clock-names = "actmon";
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resets = <&bpmp_resets TEGRA234_RESET_ACTMON>;
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reset-names = "actmon_rst";
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nvidia,sample_period = /bits/ 8 <20>;
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mc_all-actdev { /* MC_ALL actmon device */
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nvidia,reg_offs = <0x100>;
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nvidia,irq_mask = <0x2>;
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/* EMC_PLLP_FREQ + 2000 */
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nvidia,suspend_freq = <204000>;
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nvidia,boost_freq_step = <204000>;
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nvidia,boost_up_coef = <200>;
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nvidia,boost_down_coef = <50>;
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nvidia,boost_up_threshold = <30>;
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nvidia,boost_down_threshold = <20>;
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nvidia,up_wmark_window = /bits/ 8 <3>;
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nvidia,down_wmark_window = /bits/ 8 <2>;
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nvidia,avg_window_log2 = /bits/ 8 <6>;
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/*
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* count_weight(W) = no of dram clks needed to access N atoms
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* N = atoms per dvfs pulse = (2^7+1) = 256 atoms
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* 1 atom = 64bytes
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* t194 has 256 max dram width (16 channels x 16 bits per channel)
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* 1 dram clock cycle provides 256*2 bits = 64bytes
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* (i.e) 1 dram clock provides 1 atom
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* so 256 dram clocks needed for 256 atoms
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* W = 256
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*/
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nvidia,count_weight = <0x100>;
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nvidia,max_dram_channels = /bits/ 8 <16>;
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nvidia,type = <1>;
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clocks = <&bpmp_clks TEGRA234_CLK_EMC>;
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clock-names = "emc";
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};
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};
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};
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...
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