mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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platform: tegra: Copy mc-utils driver
mc-utils driver support is needed on T264, and it should be present in nvidia-t264 repo, so as to avoid leaking any information. Also, we need to make sure once T264 is public the existing mc-utils driver can be updated easily for T264 support. Hence first copy the existing mc-utils driver from nvidia-oot into nvidia-t264, then make changes for T264 and finally when T264 is public, just cherry-pick the addional changes in nvidia-oot and clean up driver from nvidia-t264. This change is doing the first step i.e. copying existing mc-utils driver code from nvidia-oot into nvidia-t264. Bug 4090660 Change-Id: I95eff8d3f7fef267a5c0f0e2137c4343a615d4aa Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2911970 Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ketan Patil
413
drivers/platform/tegra/mc-utils/mc-utils.c
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413
drivers/platform/tegra/mc-utils/mc-utils.c
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// SPDX-License-Identifier: GPL-2.0-only
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/**
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <linux/clk.h>
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#include <linux/platform/tegra/mc_utils.h>
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#include <linux/version.h>
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#include <soc/tegra/fuse.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <soc/tegra/virt/hv-ivc.h>
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#define BYTES_PER_CLK_PER_CH 4
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#define CH_16 16
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#define CH_8 8
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#define CH_4 4
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#define CH_16_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_16)
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#define CH_8_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_8)
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#define CH_4_BYTES_PER_CLK (BYTES_PER_CLK_PER_CH * CH_4)
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/* EMC regs */
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#define MC_BASE 0x02c10000
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#define EMC_BASE 0x02c60000
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#define MCB_BASE 0x02c10000
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#define MCB_SIZE 0x10000
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#define EMC_FBIO_CFG5_0 0x100C
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#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0 0xdf8
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#define MC_EMEM_ADR_CFG_0 0x54
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#define MC_ECC_CONTROL_0 0x1880
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#define CH_MASK 0xFFFF /* Change bit counting if this mask changes */
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#define CH4 0xf
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#define CH2 0x3
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#define ECC_MASK 0x1 /* 1 = enabled, 0 = disabled */
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#define RANK_MASK 0x1 /* 1 = 2-RANK, 0 = 1-RANK */
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#define DRAM_MASK 0x3
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/* EMC_FBIO_CFG5_0(1:0) : DRAM_TYPE */
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#define DRAM_LPDDR4 0
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#define DRAM_LPDDR5 1
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#define DRAM_DDR3 2
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#define BR4_MODE 4
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#define BR8_MODE 8
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/* BANDWIDTH LATENCY COMPONENTS */
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#define SMMU_DISRUPTION_DRAM_CLK_LP4 6003
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#define SMMU_DISRUPTION_DRAM_CLK_LP5 9005
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#define RING0_DISRUPTION_MC_CLK_LP4 63
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#define RING0_DISRUPTION_MC_CLK_LP5 63
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#define HUM_DISRUPTION_DRAM_CLK_LP4 1247
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#define HUM_DISRUPTION_DRAM_CLK_LP5 4768
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#define HUM_DISRUPTION_NS_LP4 1406
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#define HUM_DISRUPTION_NS_LP5 1707
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#define EXPIRED_ISO_DRAM_CLK_LP4 424
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#define EXPIRED_ISO_DRAM_CLK_LP5 792
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#define EXPIRED_ISO_NS_LP4 279
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#define EXPIRED_ISO_NS_LP5 279
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#define REFRESH_RATE_LP4 176
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#define REFRESH_RATE_LP5 226
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#define PERIODIC_TRAINING_LP4 380
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#define PERIODIC_TRAINING_LP5 380
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#define CALIBRATION_LP4 30
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#define CALIBRATION_LP5 30
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struct emc_params {
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u32 rank;
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u32 ecc;
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u32 dram;
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};
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static struct emc_params emc_param;
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static u32 ch_num;
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static enum dram_types dram_type;
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static struct mc_utils_ops *ops;
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static unsigned long freq_to_bw(unsigned long freq)
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{
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if (ch_num == CH_16)
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return freq * CH_16_BYTES_PER_CLK;
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if (ch_num == CH_8)
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return freq * CH_8_BYTES_PER_CLK;
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/*4CH and 4CH_ECC*/
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return freq * CH_4_BYTES_PER_CLK;
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}
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static unsigned long bw_to_freq(unsigned long bw)
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{
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if (ch_num == CH_16)
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return (bw + CH_16_BYTES_PER_CLK - 1) / CH_16_BYTES_PER_CLK;
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if (ch_num == CH_8)
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return (bw + CH_8_BYTES_PER_CLK - 1) / CH_8_BYTES_PER_CLK;
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/*4CH and 4CH_ECC*/
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return (bw + CH_4_BYTES_PER_CLK - 1) / CH_4_BYTES_PER_CLK;
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}
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static unsigned long emc_freq_to_bw_t23x(unsigned long freq)
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{
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return freq_to_bw(freq);
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}
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unsigned long emc_freq_to_bw(unsigned long freq)
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{
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return ops->emc_freq_to_bw(freq);
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}
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EXPORT_SYMBOL(emc_freq_to_bw);
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static unsigned long emc_bw_to_freq_t23x(unsigned long bw)
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{
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return bw_to_freq(bw);
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}
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unsigned long emc_bw_to_freq(unsigned long bw)
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{
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return ops->emc_bw_to_freq(bw);
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}
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EXPORT_SYMBOL(emc_bw_to_freq);
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static u8 get_dram_num_channels_t23x(void)
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{
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return ch_num;
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}
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u8 get_dram_num_channels(void)
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{
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return ops->get_dram_num_channels();
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}
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EXPORT_SYMBOL(get_dram_num_channels);
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/* DRAM clock in MHz
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*
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* Return: MC clock in MHz
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*/
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static unsigned long dram_clk_to_mc_clk_t23x(unsigned long dram_clk)
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{
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unsigned long mc_clk;
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if (dram_clk <= 1600)
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mc_clk = (dram_clk + BR4_MODE - 1) / BR4_MODE;
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else
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mc_clk = (dram_clk + BR8_MODE - 1) / BR8_MODE;
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return mc_clk;
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}
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unsigned long dram_clk_to_mc_clk(unsigned long dram_clk)
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{
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return ops->dram_clk_to_mc_clk(dram_clk);
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}
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EXPORT_SYMBOL(dram_clk_to_mc_clk);
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static void set_dram_type(void)
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{
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dram_type = DRAM_TYPE_INVAL;
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switch (emc_param.dram) {
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case DRAM_LPDDR5:
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if (emc_param.ecc) {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_ECC_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_ECC_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_ECC_1RANK;
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}
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} else {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_16CH_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_8CH_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_1RANK;
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}
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}
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if (ch_num < 4) {
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pr_err("DRAM_LPDDR5: Unknown memory channel configuration\n");
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WARN_ON(true);
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}
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break;
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case DRAM_LPDDR4:
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if (emc_param.ecc) {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_ECC_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_ECC_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_4CH_ECC_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_4CH_ECC_1RANK;
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}
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} else {
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if (ch_num == 16) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_16CH_1RANK;
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} else if (ch_num == 8) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR4_8CH_1RANK;
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} else if (ch_num == 4) {
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if (emc_param.rank)
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_2RANK;
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else
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dram_type =
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DRAM_TYPE_LPDDR5_4CH_1RANK;
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}
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}
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if (ch_num < 4) {
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pr_err("DRAM_LPDDR4: Unknown memory channel configuration\n");
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WARN_ON(true);
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}
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break;
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default:
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pr_err("mc_util: ddr config not supported\n");
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WARN_ON(true);
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}
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}
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static enum dram_types tegra_dram_types_t23x(void)
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{
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return dram_type;
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}
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enum dram_types tegra_dram_types(void)
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{
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return ops->tegra_dram_types();
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}
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EXPORT_SYMBOL(tegra_dram_types);
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#if defined(CONFIG_DEBUG_FS)
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static void tegra_mc_utils_debugfs_init(void)
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{
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struct dentry *tegra_mc_debug_root = NULL;
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tegra_mc_debug_root = debugfs_create_dir("tegra_mc_utils", NULL);
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if (IS_ERR_OR_NULL(tegra_mc_debug_root)) {
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pr_err("tegra_mc: Unable to create debugfs dir\n");
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return;
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}
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debugfs_create_u32("dram_type", 0444, tegra_mc_debug_root,
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&dram_type);
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debugfs_create_u32("num_channel", 0444, tegra_mc_debug_root,
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&ch_num);
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}
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#endif
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static u32 get_dram_dt_prop(struct device_node *np, const char *prop)
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{
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u32 val;
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int ret;
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ret = of_property_read_u32(np, prop, &val);
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if (ret) {
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pr_err("failed to read %s\n", prop);
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return ~0U;
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}
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return val;
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}
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static struct mc_utils_ops mc_utils_t23x_ops = {
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.emc_freq_to_bw = emc_freq_to_bw_t23x,
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.emc_bw_to_freq = emc_bw_to_freq_t23x,
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.tegra_dram_types = tegra_dram_types_t23x,
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.get_dram_num_channels = get_dram_num_channels_t23x,
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.dram_clk_to_mc_clk = dram_clk_to_mc_clk_t23x,
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};
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static int __init tegra_mc_utils_init_t23x(void)
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{
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u32 dram, ch, ecc, rank;
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void __iomem *emc_base;
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void __iomem *mcb_base;
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if (!is_tegra_hypervisor_mode()) {
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emc_base = ioremap(EMC_BASE, 0x00010000);
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dram = readl(emc_base + EMC_FBIO_CFG5_0) & DRAM_MASK;
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mcb_base = ioremap(MCB_BASE, MCB_SIZE);
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if (!mcb_base) {
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pr_err("Failed to ioremap\n");
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return -ENOMEM;
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}
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ch = readl(mcb_base + MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0);
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ch &= CH_MASK;
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ecc = readl(mcb_base + MC_ECC_CONTROL_0) & ECC_MASK;
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rank = readl(mcb_base + MC_EMEM_ADR_CFG_0) & RANK_MASK;
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iounmap(emc_base);
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iounmap(mcb_base);
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while (ch) {
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if (ch & 1)
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ch_num++;
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ch >>= 1;
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}
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} else {
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struct device_node *np = of_find_compatible_node(NULL, NULL, "nvidia,tegra234-mc");
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if (!np) {
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pr_err("mc-utils: Not able to find MC DT node\n");
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return -ENODEV;
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}
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ecc = get_dram_dt_prop(np, "dram_ecc");
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rank = get_dram_dt_prop(np, "dram_rank");
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dram = get_dram_dt_prop(np, "dram_lpddr");
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ch_num = get_dram_dt_prop(np, "dram_channels");
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}
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emc_param.ecc = ecc;
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emc_param.rank = rank;
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emc_param.dram = dram;
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set_dram_type();
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#if defined(CONFIG_DEBUG_FS)
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tegra_mc_utils_debugfs_init();
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#endif
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return 0;
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}
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static int __init tegra_mc_utils_init(void)
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{
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if (of_machine_is_compatible("nvidia,tegra234")) {
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ops = &mc_utils_t23x_ops;
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return tegra_mc_utils_init_t23x();
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}
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pr_err("mc-utils: Not able to find SOC DT node\n");
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return -ENODEV;
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}
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module_init(tegra_mc_utils_init);
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static void __exit tegra_mc_utils_exit(void)
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{
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}
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module_exit(tegra_mc_utils_exit);
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MODULE_DESCRIPTION("MC utility provider module");
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MODULE_AUTHOR("Puneet Saxena <puneets@nvidia.com>");
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MODULE_AUTHOR("Ashish Mhetre <amhetre@nvidia.com>");
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MODULE_LICENSE("GPL v2");
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