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git://nv-tegra.nvidia.com/linux-nv-oot.git
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host1x: Emulated Syncpoint KMD Driver
1. Update Host1x-Syncpt - add syncpt-list in syncpoint-pool structure. - add exported "host1x-syncpt-*" interface and supporting private interface. 2. Update Host1x-NvHost - add support for nvhost-syncpt and nvhost-client interface and supporting private interface. - falcon and pm interface not supported 3. Update Host1x-Fence - add exported "host1x-fence-*" interface and supporting private interface. 4. Add Host1x-Poll - Per Pool polling workequeue created - add poll supporting private interface. 5. Add new IOCTL Jira HOSTX-5514 Change-Id: I187fa7ed89a3479e51b79f9d8d438ede75e1a36a Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3136834 Tested-by: Amitabh Dutta <amitabhd@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Amitabh Dutta <amitabhd@nvidia.com>
This commit is contained in:
amitabhd
257
drivers/gpu/host1x-emu/include/linux/nvhost-emu.h
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257
drivers/gpu/host1x-emu/include/linux/nvhost-emu.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#ifndef __LINUX_NVHOST_H
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#define __LINUX_NVHOST_H
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#include <linux/cdev.h>
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#include <linux/device.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/symbol-emu.h>
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/**
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* TODO: Remove header after pre-silicon verification
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* This header is required till emulation driver verification is done on Tho-r
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* VDK platform. Since we are exporting new kernel symbol, header with declarion
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* of modified symbols is required
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*
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* Changed cannot be added in orignal Host1x driver header files ("linux/nvhost.h"
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* and "host1x-next.h") due to Host1x driver and other dependent drivers. Note in
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* Tho-r verification config both the driver will co-exist.
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*
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* Some data structure are also re-delacred in this header for case where client
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* driver wants to verify over emulation driver.
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*/
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struct nvhost_ctrl_sync_fence_info;
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struct nvhost_fence;
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#define NVHOST_MODULE_MAX_CLOCKS 8
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#define NVHOST_MODULE_MAX_IORESOURCE_MEM 5
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enum tegra_emc_request_type {
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TEGRA_SET_EMC_FLOOR, /* lower bound */
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};
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struct nvhost_clock {
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char *name;
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unsigned long default_rate;
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u32 moduleid;
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enum tegra_emc_request_type request_type;
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bool disable_scaling;
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unsigned long devfreq_rate;
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};
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struct nvhost_vm_hwid {
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u64 addr;
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bool dynamic;
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u32 shift;
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};
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/*
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* Defines HW and SW class identifiers.
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*
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* This is module ID mapping between userspace and kernelspace.
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* The values of enum entries' are referred from NvRmModuleID enum defined
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* in below userspace file:
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* $TOP/vendor/nvidia/tegra/core/include/nvrm_module.h
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* Please make sure each entry below has same value as set in above file.
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*/
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enum nvhost_module_identifier {
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/* Specifies external memory (DDR RAM, etc) */
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER = 75,
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};
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enum nvhost_resource_policy {
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RESOURCE_PER_DEVICE = 0,
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RESOURCE_PER_CHANNEL_INSTANCE,
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};
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struct nvhost_device_data {
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int version; /* ip version number of device */
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void __iomem *aperture[NVHOST_MODULE_MAX_IORESOURCE_MEM];
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u32 moduleid; /* Module id for user space API */
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/* interrupt ISR routine for falcon based engines */
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int (*flcn_isr)(struct platform_device *dev);
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int irq;
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int module_irq; /* IRQ bit from general intr reg for module intr */
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bool self_config_flcn_isr; /* skip setting up falcon interrupts */
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u32 class; /* Device class */
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bool keepalive; /* Do not power gate when opened */
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bool serialize; /* Serialize submits in the channel */
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bool push_work_done; /* Push_op done into push buffer */
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bool poweron_reset; /* Reset the engine before powerup */
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char *devfs_name; /* Name in devfs */
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char *devfs_name_family; /* Core of devfs name */
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char *firmware_name; /* Name of firmware */
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bool firmware_not_in_subdir; /* Firmware is not located in
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chip subdirectory */
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bool engine_can_cg; /* True if CG is enabled */
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bool can_powergate; /* True if module can be power gated */
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int autosuspend_delay; /* Delay before power gated */
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struct nvhost_clock clocks[NVHOST_MODULE_MAX_CLOCKS];/* Clock names */
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int num_clks; /* Number of clocks opened for dev */
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struct clk_bulk_data *clks;
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struct mutex lock; /* Power management lock */
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int num_channels; /* Max num of channel supported */
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int num_ppc; /* Number of pixels per clock cycle */
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dev_t cdev_region;
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/* device node for ctrl block */
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struct class *nvhost_class;
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struct device *ctrl_node;
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struct cdev ctrl_cdev;
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const struct file_operations *ctrl_ops; /* ctrl ops for the module */
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struct kobject clk_cap_kobj;
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struct kobj_attribute *clk_cap_attrs;
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struct dentry *debugfs; /* debugfs directory */
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/* Marks if the device is booted when pm runtime is disabled */
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bool booted;
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void *private_data; /* private platform data */
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void *falcon_data; /* store the falcon info */
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struct platform_device *pdev; /* owner platform_device */
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struct host1x *host1x; /* host1x device */
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/* Finalize power on. Can be used for context restore. */
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int (*finalize_poweron)(struct platform_device *dev);
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/* Preparing for power off. Used for context save. */
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int (*prepare_poweroff)(struct platform_device *dev);
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/* paring for power off. Used for context save. */
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int (*aggregate_constraints)(struct platform_device *dev,
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int clk_index,
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unsigned long floor_rate,
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unsigned long pixel_rate,
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unsigned long bw_rate);
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/* Used to add platform specific masks on reloc address */
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dma_addr_t (*get_reloc_phys_addr)(dma_addr_t phys_addr, u32 reloc_type);
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/* engine specific init functions */
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int (*pre_virt_init)(struct platform_device *pdev);
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int (*post_virt_init)(struct platform_device *pdev);
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/* Information related to engine-side synchronization */
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void *syncpt_unit_interface;
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u64 transcfg_addr;
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u32 transcfg_val;
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struct nvhost_vm_hwid vm_regs[13];
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/* Should we map channel at submit time? */
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bool resource_policy;
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/* Should we enable context isolation for this device? */
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bool isolate_contexts;
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/* reset control for this device */
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struct reset_control *reset_control;
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/* icc client id for emc requests */
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int icc_id;
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/* icc_path handle handle */
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struct icc_path *icc_path_handle;
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/* bandwidth manager client id for emc requests */
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int bwmgr_client_id;
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};
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static inline
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struct nvhost_device_data *nvhost_get_devdata(struct platform_device *pdev)
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{
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return (struct nvhost_device_data *)platform_get_drvdata(pdev);
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}
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extern const struct dev_pm_ops nvhost_module_pm_ops;
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HOST1X_EMU_EXPORT_DECL(u32, host1x_readl(struct platform_device *pdev, u32 r));
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HOST1X_EMU_EXPORT_DECL(void, host1x_writel(struct platform_device *pdev, u32 r, u32 v));
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/* public api to return platform_device ptr to the default host1x instance */
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HOST1X_EMU_EXPORT_DECL(struct platform_device*, nvhost_get_default_device(void));
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/* common runtime pm and power domain APIs */
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HOST1X_EMU_EXPORT_DECL(int, nvhost_module_init(struct platform_device *ndev));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_module_deinit(struct platform_device *dev));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_module_reset(struct platform_device *dev, bool reboot));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_module_busy(struct platform_device *dev));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_module_idle(struct platform_device *dev));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_module_idle_mult(struct platform_device *pdev, int refs));
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/* common device management APIs */
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HOST1X_EMU_EXPORT_DECL(int, nvhost_client_device_get_resources(struct platform_device *dev));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_client_device_release(struct platform_device *dev));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_client_device_init(struct platform_device *dev));
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/* public host1x sync-point management APIs */
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_get_syncpt_host_managed(struct platform_device *pdev,
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u32 param, const char *syncpt_name));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_get_syncpt_client_managed(struct platform_device *pdev,
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const char *syncpt_name));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_get_syncpt_gpu_managed(struct platform_device *pdev,
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const char *syncpt_name));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_syncpt_put_ref_ext(struct platform_device *pdev, u32 id));
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HOST1X_EMU_EXPORT_DECL(bool, nvhost_syncpt_is_valid_pt_ext(struct platform_device *dev, u32 id));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_syncpt_is_expired_ext(struct platform_device *dev, u32 id,
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u32 thresh));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_syncpt_set_min_update(struct platform_device *pdev, u32 id, u32 val));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_syncpt_read_ext_check(struct platform_device *dev, u32 id, u32 *val));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_syncpt_read_maxval(struct platform_device *dev, u32 id));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_syncpt_incr_max_ext(struct platform_device *dev, u32 id, u32 incrs));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_syncpt_unit_interface_init(struct platform_device *pdev));
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HOST1X_EMU_EXPORT_DECL(void, nvhost_syncpt_unit_interface_deinit(struct platform_device *pdev));
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HOST1X_EMU_EXPORT_DECL(dma_addr_t, nvhost_syncpt_address(struct platform_device *engine_pdev, u32 id));
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/* public host1x interrupt management APIs */
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HOST1X_EMU_EXPORT_DECL(int, nvhost_intr_register_notifier(struct platform_device *pdev,
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u32 id, u32 thresh,
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void (*callback)(void *),
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void *private_data));
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/* public host1x sync-point management APIs */
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HOST1X_EMU_EXPORT_DECL(struct host1x*, nvhost_get_host1x(struct platform_device *pdev));
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HOST1X_EMU_EXPORT_DECL(int, nvhost_syncpt_unit_interface_get_aperture(
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struct platform_device *host_pdev,
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phys_addr_t *base,
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size_t *size));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id));
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HOST1X_EMU_EXPORT_DECL(u32, nvhost_syncpt_unit_interface_get_byte_offset_ext(
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struct platform_device *host_pdev,
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u32 syncpt_id));
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#endif
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