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media: camera: Build tegra-camera as OOT module
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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17
include/linux/arm64-barrier.h
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17
include/linux/arm64-barrier.h
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/version.h>
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/*
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* Upstream Linux commit bd4fb6d270bc ("arm64: Add support for SB
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* barrier and patch in over DSB; ISB sequences") added speculation
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* macro 'spec_bar' to inhibit speculation. This has since been removed
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* from the upstream kernel starting with Linux v5.13, because there are
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* no current users. Define this macro here for NVIDIA drivers to use.
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*/
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#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \
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SB_BARRIER_INSN"nop\n", \
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ARM64_HAS_SB))
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29
include/linux/platform/tegra/bwmgr_mc.h
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29
include/linux/platform/tegra/bwmgr_mc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __BWMGR_MC_H
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#define __BWMGR_MC_H
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#include <linux/types.h>
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#include <linux/platform/tegra/iso_client.h>
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unsigned long bwmgr_apply_efficiency(
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unsigned long bw, unsigned long iso_bw,
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unsigned long emc_max, u64 usage_flags,
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unsigned long *iso_bw_min, unsigned long iso_bw_nvdis,
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unsigned long iso_bw_vi);
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void bwmgr_eff_init(void);
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unsigned long bwmgr_freq_to_bw(unsigned long freq);
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unsigned long bwmgr_bw_to_freq(unsigned long bw);
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unsigned long bwmgr_get_lowest_iso_emc_freq(long iso_bw,
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long iso_bw_nvdis, long iso_bw_vi);
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u32 tegra_bwmgr_get_max_iso_bw(enum tegra_iso_client);
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u32 bwmgr_dvfs_latency(u32 ufreq);
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int bwmgr_iso_bw_percentage_max(void);
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int bwmgr_get_emc_to_dram_freq_factor(void);
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#endif /* __BWMGR_MC_H */
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204
include/linux/platform/tegra/isomgr.h
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204
include/linux/platform/tegra/isomgr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _INCLUDE_MACH_ISOMGR_H
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#define _INCLUDE_MACH_ISOMGR_H
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <linux/platform/tegra/iso_client.h>
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#define ISOMGR_MAGIC 0x150A1C
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/* handle to identify registered client */
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#define tegra_isomgr_handle void *
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/* callback to client to renegotiate ISO BW allocation */
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typedef void (*tegra_isomgr_renegotiate)(void *priv,
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u32 avail_bw); /* KB/sec */
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struct isoclient_info {
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enum tegra_iso_client client;
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char *name;
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char *dev_name;
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char *emc_clk_name;
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enum tegra_bwmgr_client_id bwmgr_id;
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};
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struct isomgr_client {
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u32 magic; /* magic to identify handle */
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struct kref kref; /* ref counting */
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s32 dedi_bw; /* BW dedicated to this client (KB/sec) */
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s32 rsvd_bw; /* BW reserved for this client (KB/sec) */
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s32 real_bw; /* BW realized for this client (KB/sec) */
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s32 lti; /* Client spec'd Latency Tolerance (usec) */
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s32 lto; /* MC calculated Latency Tolerance (usec) */
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s32 rsvd_mf; /* reserved minimum freq in support of LT */
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s32 real_mf; /* realized minimum freq in support of LT */
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s32 real_mf_rq; /* real_mf requested */
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tegra_isomgr_renegotiate renegotiate; /* ask client to renegotiate */
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bool realize; /* bw realization in progress */
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s32 sleep_bw; /* sleeping for realize */
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s32 margin_bw; /* BW set aside for this client (KB/sec) */
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u8 limit_bw_percentage; /* Insufficient HW buffers cause BW to be
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* limited to this percentage of DRAM BW
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*/
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void *priv; /* client driver's private data */
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struct completion cmpl; /* so we can sleep waiting for delta BW */
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#ifdef CONFIG_COMMON_CLK
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struct tegra_bwmgr_client *bwmgr_handle;
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#else
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struct clk *emc_clk; /* client emc clk for bw */
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#endif
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#ifdef CONFIG_TEGRA_ISOMGR_SYSFS
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struct kobject *client_kobj;
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struct isomgr_client_attrs {
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struct kobj_attribute dedi_bw;
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struct kobj_attribute rsvd_bw;
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struct kobj_attribute real_bw;
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struct kobj_attribute lti;
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struct kobj_attribute lto;
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struct kobj_attribute rsvd_mf;
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struct kobj_attribute real_mf;
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struct kobj_attribute sleep_bw;
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struct kobj_attribute margin_bw;
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} client_attrs;
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#endif /* CONFIG_TEGRA_ISOMGR_SYSFS */
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};
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struct isomgr {
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struct mutex lock; /* to lock ALL isomgr state */
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struct task_struct *task; /* check reentrant/mismatched locks */
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#ifdef CONFIG_COMMON_CLK
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struct tegra_bwmgr_client *bwmgr_handle;
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#else
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struct clk *emc_clk; /* isomgr emc clock for floor freq */
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#endif
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s32 lt_mf; /* min freq to support worst LT */
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s32 lt_mf_rq; /* requested lt_mf */
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s32 avail_bw; /* globally available MC BW */
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s32 dedi_bw; /* total BW 'dedicated' to clients */
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s32 sleep_bw; /* pending bw requirement */
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u32 max_iso_bw; /* max ISO BW MC can accommodate */
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struct kobject *kobj; /* for sysfs linkage */
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struct isomgr_ops *ops; /* ops structure for isomgr*/
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};
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extern struct isoclient_info *isoclient_info;
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/*platform specific flag for requesting max emc floor req for camera client*/
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extern u8 isomgr_camera_max_floor_req;
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extern int isoclients;
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extern bool client_valid[TEGRA_ISO_CLIENT_COUNT];
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extern struct isomgr_client isomgr_clients[TEGRA_ISO_CLIENT_COUNT];
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extern struct isomgr isomgr;
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extern char *cname[];
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struct isomgr_ops {
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void (*isomgr_plat_init)(void);
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bool (*isomgr_plat_register)(u32 dedi_bw,
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enum tegra_iso_client client);
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void (*isomgr_plat_unregister)(struct isomgr_client *cp);
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bool (*isomgr_plat_reserve)(struct isomgr_client *cp,
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u32 bw, enum tegra_iso_client client);
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bool (*isomgr_plat_realize)(struct isomgr_client *cp);
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u32 (*isomgr_max_iso_bw)(enum tegra_iso_client client);
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};
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struct isomgr_ops *pre_t19x_isomgr_init(void);
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struct isomgr_ops *t19x_isomgr_init(void);
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#if defined(CONFIG_TEGRA_ISOMGR)
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/* Register an ISO BW client */
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tegra_isomgr_handle tegra_isomgr_register(enum tegra_iso_client client,
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u32 dedicated_bw, /* KB/sec */
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tegra_isomgr_renegotiate renegotiate,
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void *priv);
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/* Unregister an ISO BW client */
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void tegra_isomgr_unregister(tegra_isomgr_handle handle);
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/* Return the initialization status of isomgr */
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bool tegra_isomgr_init_status(void);
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/* Reserve ISO BW on behalf of client - don't apply, rval is dvfs thresh usec */
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u32 tegra_isomgr_reserve(tegra_isomgr_handle handle,
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u32 bw, /* KB/sec */
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u32 lt); /* usec */
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/* Realize client reservation - apply settings, rval is dvfs thresh usec */
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u32 tegra_isomgr_realize(tegra_isomgr_handle handle);
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/* This sets bw aside for the client specified. */
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int tegra_isomgr_set_margin(enum tegra_iso_client client, u32 bw, bool wait);
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int tegra_isomgr_get_imp_time(enum tegra_iso_client, u32 bw);
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/* returns available in iso bw in KB/sec */
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u32 tegra_isomgr_get_available_iso_bw(void);
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/* returns total iso bw in KB/sec */
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u32 tegra_isomgr_get_total_iso_bw(enum tegra_iso_client client);
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/* Initialize isomgr.
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* This api would be called by .init_machine during boot.
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* isomgr clients, don't call this api.
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*/
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int __init isomgr_init(void);
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#else
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static inline tegra_isomgr_handle tegra_isomgr_register(
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enum tegra_iso_client client,
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u32 dedicated_bw,
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tegra_isomgr_renegotiate renegotiate,
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void *priv)
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{
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/* return a dummy handle to allow client function
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* as if isomgr were enabled.
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*/
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return (tegra_isomgr_handle)1;
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}
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static inline void tegra_isomgr_unregister(tegra_isomgr_handle handle) {}
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static inline u32 tegra_isomgr_reserve(tegra_isomgr_handle handle,
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u32 bw, u32 lt)
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{
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return 1;
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}
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static inline u32 tegra_isomgr_realize(tegra_isomgr_handle handle)
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{
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return 1;
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}
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static inline int tegra_isomgr_set_margin(enum tegra_iso_client client, u32 bw)
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{
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return 0;
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}
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static inline int tegra_isomgr_get_imp_time(enum tegra_iso_client client,
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u32 bw)
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{
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return 0;
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}
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static inline u32 tegra_isomgr_get_available_iso_bw(void)
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{
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return UINT_MAX;
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}
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static inline u32 tegra_isomgr_get_total_iso_bw(enum tegra_iso_client client)
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{
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return UINT_MAX;
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}
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static inline int isomgr_init(void)
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{
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return 0;
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}
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#endif
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#endif /* _INCLUDE_MACH_ISOMGR_H */
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330
include/linux/platform/tegra/latency_allowance.h
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330
include/linux/platform/tegra/latency_allowance.h
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@@ -0,0 +1,330 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2011-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
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#define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
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#define FIRST_DISP_CLIENT_ID TEGRA_LA_DISPLAY_0A
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#define DISP_CLIENT_LA_ID(id) (id - FIRST_DISP_CLIENT_ID)
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/* Note:- When adding new display realted IDs, please add them adjacent/amongst
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the existing display related IDs. This is required because certain
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display related macros/strcuts assume that all display related
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tegra_la_ids are adjacent to each other.
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Please observe the same guidelines as display clients, when adding new
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camera clients. All camera clients need to be located adjacent to each
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other in tegra_la_id. This is required because certain camera related
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macros/structs assume that all camera related tegra_la_ids are
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adjacent to each other. */
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enum tegra_la_id {
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TEGRA_LA_AFIR = 0, /* T30 specific */
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TEGRA_LA_AFIW, /* T30 specific */
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TEGRA_LA_AVPC_ARM7R,
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TEGRA_LA_AVPC_ARM7W,
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TEGRA_LA_DISPLAY_0A,
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TEGRA_LA_DISPLAY_0B,
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TEGRA_LA_DISPLAY_0C,
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TEGRA_LA_DISPLAY_1B, /* T30 specific */
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TEGRA_LA_DISPLAY_HC,
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TEGRA_LA_DISPLAY_0AB,
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TEGRA_LA_DISPLAY_0BB,
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TEGRA_LA_DISPLAY_0CB,
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TEGRA_LA_DISPLAY_1BB, /* T30 specific */
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TEGRA_LA_DISPLAY_HCB,
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TEGRA_LA_DISPLAY_T, /* T14x specific */
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TEGRA_LA_DISPLAYD, /* T14x specific */
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TEGRA_LA_EPPUP,
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TEGRA_LA_EPPU,
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TEGRA_LA_EPPV,
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TEGRA_LA_EPPY,
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TEGRA_LA_G2PR,
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TEGRA_LA_G2SR,
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TEGRA_LA_G2DR,
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TEGRA_LA_G2DW,
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TEGRA_LA_GPUSRD, /* T12x specific */
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TEGRA_LA_GPUSWR, /* T12x specific */
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TEGRA_LA_HOST1X_DMAR,
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TEGRA_LA_HOST1XR,
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TEGRA_LA_HOST1XW,
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TEGRA_LA_HDAR,
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TEGRA_LA_HDAW,
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TEGRA_LA_ISPW,
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TEGRA_LA_MPCORER,
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TEGRA_LA_MPCOREW,
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TEGRA_LA_MPCORE_LPR,
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TEGRA_LA_MPCORE_LPW,
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TEGRA_LA_MPE_UNIFBR, /* T30 specific */
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TEGRA_LA_MPE_IPRED, /* T30 specific */
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TEGRA_LA_MPE_AMEMRD, /* T30 specific */
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TEGRA_LA_MPE_CSRD, /* T30 specific */
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TEGRA_LA_MPE_UNIFBW, /* T30 specific */
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TEGRA_LA_MPE_CSWR, /* T30 specific */
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TEGRA_LA_FDCDRD,
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TEGRA_LA_IDXSRD,
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TEGRA_LA_TEXSRD,
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TEGRA_LA_TEXL2SRD = TEGRA_LA_TEXSRD, /* T11x, T14x specific */
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TEGRA_LA_FDCDWR,
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TEGRA_LA_FDCDRD2,
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TEGRA_LA_IDXSRD2, /* T30 specific */
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TEGRA_LA_TEXSRD2, /* T30 specific */
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TEGRA_LA_FDCDWR2,
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TEGRA_LA_PPCS_AHBDMAR,
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TEGRA_LA_PPCS_AHBSLVR,
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TEGRA_LA_PPCS_AHBDMAW,
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TEGRA_LA_PPCS_AHBSLVW,
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TEGRA_LA_PTCR,
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TEGRA_LA_SATAR, /* T30, T19x */
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TEGRA_LA_SATAW, /* T30, T19x */
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TEGRA_LA_VDE_BSEVR,
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TEGRA_LA_VDE_MBER,
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TEGRA_LA_VDE_MCER,
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TEGRA_LA_VDE_TPER,
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TEGRA_LA_VDE_BSEVW,
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TEGRA_LA_VDE_DBGW,
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TEGRA_LA_VDE_MBEW,
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TEGRA_LA_VDE_TPMW,
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TEGRA_LA_VI_RUV, /* T30 specific */
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TEGRA_LA_VI_WSB,
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TEGRA_LA_VI_WU,
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TEGRA_LA_VI_WV,
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TEGRA_LA_VI_WY,
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TEGRA_LA_MSENCSRD, /* T11x, T14x specific */
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TEGRA_LA_MSENCSWR, /* T11x, T14x specific */
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TEGRA_LA_XUSB_HOSTR, /* T11x, T19x */
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TEGRA_LA_XUSB_HOSTW, /* T11x, T19x */
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TEGRA_LA_XUSB_DEVR, /* T11x, T19x */
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TEGRA_LA_XUSB_DEVW, /* T11x, T19x */
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TEGRA_LA_FDCDRD3, /* T11x specific */
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TEGRA_LA_FDCDRD4, /* T11x specific */
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TEGRA_LA_FDCDWR3, /* T11x specific */
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TEGRA_LA_FDCDWR4, /* T11x specific */
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TEGRA_LA_EMUCIFR, /* T11x, T14x specific */
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TEGRA_LA_EMUCIFW, /* T11x, T14x specific */
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TEGRA_LA_TSECSRD, /* T11x, T14x, T19x */
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TEGRA_LA_TSECSWR, /* T11x, T14x, T19x */
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TEGRA_LA_VI_W, /* T14x specific */
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TEGRA_LA_ISP_RA, /* T14x specific */
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TEGRA_LA_ISP_WA, /* T14x specific */
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TEGRA_LA_ISP_WB, /* T14x specific */
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TEGRA_LA_ISP_RAB, /* T12x specific */
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TEGRA_LA_ISP_WAB, /* T12x specific */
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TEGRA_LA_ISP_WBB, /* T12x specific */
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TEGRA_LA_BBCR, /* T14x specific */
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TEGRA_LA_BBCW, /* T14x specific */
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TEGRA_LA_BBCLLR, /* T14x specific */
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TEGRA_LA_SDMMCR, /* T12x, T19x */
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TEGRA_LA_SDMMCRA, /* T12x, T19x */
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TEGRA_LA_SDMMCRAA, /* T12x specific */
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TEGRA_LA_SDMMCRAB, /* T12x, T19x */
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TEGRA_LA_SDMMCW, /* T12x, T19x */
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TEGRA_LA_SDMMCWA, /* T12x, T19x */
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TEGRA_LA_SDMMCWAA, /* T12x specific */
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TEGRA_LA_SDMMCWAB, /* T12x, T19x */
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TEGRA_LA_VICSRD, /* T12x, T19x */
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TEGRA_LA_VICSWR, /* T12x, T19x */
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||||
|
||||
TEGRA_LA_TSECBSRD, /* T21x specific */
|
||||
TEGRA_LA_TSECBSWR, /* T21x specific */
|
||||
|
||||
TEGRA_LA_NVDECR, /* T21x specific */
|
||||
TEGRA_LA_NVDECW, /* T21x specific */
|
||||
|
||||
TEGRA_LA_AONR, /* T18x, T19x */
|
||||
TEGRA_LA_AONW, /* T18x, T19x */
|
||||
TEGRA_LA_AONDMAR, /* T18x, T19x */
|
||||
TEGRA_LA_AONDMAW, /* T18x, T19x */
|
||||
TEGRA_LA_APEDMAR, /* T18x, T19x */
|
||||
TEGRA_LA_APEDMAW, /* T18x, T19x */
|
||||
TEGRA_LA_APER, /* T18x, T19x */
|
||||
TEGRA_LA_APEW, /* T18x, T19x */
|
||||
TEGRA_LA_AXISR, /* T18x, T19x */
|
||||
TEGRA_LA_AXISW, /* T18x, T19x */
|
||||
TEGRA_LA_BPMPR, /* T18x, T19x */
|
||||
TEGRA_LA_BPMPW, /* T18x, T19x */
|
||||
TEGRA_LA_BPMPDMAR, /* T18x, T19x */
|
||||
TEGRA_LA_BPMPDMAW, /* T18x, T19x */
|
||||
TEGRA_LA_EQOSR, /* T18x, T19x */
|
||||
TEGRA_LA_EQOSW, /* T18x, T19x */
|
||||
TEGRA_LA_ETRR, /* T18x, T19x */
|
||||
TEGRA_LA_ETRW, /* T18x, T19x */
|
||||
TEGRA_LA_GPUSRD2, /* T18x specific */
|
||||
TEGRA_LA_GPUSWR2, /* T18x specific */
|
||||
TEGRA_LA_NVDISPLAYR, /* T18x, T19x */
|
||||
TEGRA_LA_NVENCSRD, /* T18x, T19x */
|
||||
TEGRA_LA_NVENCSWR, /* T18x, T19x */
|
||||
TEGRA_LA_NVJPGSRD, /* T18x, T19x */
|
||||
TEGRA_LA_NVJPGSWR, /* T18x, T19x */
|
||||
TEGRA_LA_SCER, /* T18x, T19x */
|
||||
TEGRA_LA_SCEW, /* T18x, T19x */
|
||||
TEGRA_LA_SCEDMAR, /* T18x, T19x */
|
||||
TEGRA_LA_SCEDMAW, /* T18x, T19x */
|
||||
TEGRA_LA_SESRD, /* T18x, T19x */
|
||||
TEGRA_LA_SESWR, /* T18x, T19x */
|
||||
TEGRA_LA_UFSHCR, /* T18x, T19x */
|
||||
TEGRA_LA_UFSHCW, /* T18x, T19x */
|
||||
|
||||
TEGRA_LA_AXIAPR, /* T19x specific */
|
||||
TEGRA_LA_AXIAPW, /* T19x specific */
|
||||
TEGRA_LA_CIFLL_WR, /* T19x specific */
|
||||
TEGRA_LA_DLA0FALRDB, /* T19x specific */
|
||||
TEGRA_LA_DLA0RDA, /* T19x specific */
|
||||
TEGRA_LA_DLA0FALWRB, /* T19x specific */
|
||||
TEGRA_LA_DLA0WRA, /* T19x specific */
|
||||
TEGRA_LA_DLA0RDA1, /* T19x specific */
|
||||
TEGRA_LA_DLA1RDA1, /* T19x specific */
|
||||
TEGRA_LA_DLA1FALRDB, /* T19x specific */
|
||||
TEGRA_LA_DLA1RDA, /* T19x specific */
|
||||
TEGRA_LA_DLA1FALWRB, /* T19x specific */
|
||||
TEGRA_LA_DLA1WRA, /* T19x specific */
|
||||
TEGRA_LA_HOST1XDMAR, /* T19x specific */
|
||||
TEGRA_LA_ISPFALR, /* T19x specific */
|
||||
TEGRA_LA_ISPRA, /* T19x specific */
|
||||
TEGRA_LA_ISPWA, /* T19x specific */
|
||||
TEGRA_LA_ISPWB, /* T19x specific */
|
||||
TEGRA_LA_ISPFALW, /* T19x specific */
|
||||
TEGRA_LA_ISPRA1, /* T19x specific */
|
||||
TEGRA_LA_MIU0R, /* T19x specific */
|
||||
TEGRA_LA_MIU0W, /* T19x specific */
|
||||
TEGRA_LA_MIU1R, /* T19x specific */
|
||||
TEGRA_LA_MIU1W, /* T19x specific */
|
||||
TEGRA_LA_MIU2R, /* T19x specific */
|
||||
TEGRA_LA_MIU2W, /* T19x specific */
|
||||
TEGRA_LA_MIU3R, /* T19x specific */
|
||||
TEGRA_LA_MIU3W, /* T19x specific */
|
||||
TEGRA_LA_MIU4R, /* T19x specific */
|
||||
TEGRA_LA_MIU4W, /* T19x specific */
|
||||
TEGRA_LA_MIU5R, /* T19x specific */
|
||||
TEGRA_LA_MIU5W, /* T19x specific */
|
||||
TEGRA_LA_MIU6R, /* T19x specific */
|
||||
TEGRA_LA_MIU6W, /* T19x specific */
|
||||
TEGRA_LA_MIU7R, /* T19x specific */
|
||||
TEGRA_LA_MIU7W, /* T19x specific */
|
||||
TEGRA_LA_NVDECSRD, /* T19x specific */
|
||||
TEGRA_LA_NVDECSWR, /* T19x specific */
|
||||
TEGRA_LA_NVDEC1SRD, /* T19x specific */
|
||||
TEGRA_LA_NVDECSRD1, /* T19x specific */
|
||||
TEGRA_LA_NVDEC1SRD1, /* T19x specific */
|
||||
TEGRA_LA_NVDEC1SWR, /* T19x specific */
|
||||
TEGRA_LA_NVENC1SRD, /* T19x specific */
|
||||
TEGRA_LA_NVENC1SWR, /* T19x specific */
|
||||
TEGRA_LA_NVENC1SRD1, /* T19x specific */
|
||||
TEGRA_LA_NVENCSRD1, /* T19x specific */
|
||||
TEGRA_LA_PCIE0R, /* T19x specific */
|
||||
TEGRA_LA_PCIE0W, /* T19x specific */
|
||||
TEGRA_LA_PCIE1R, /* T19x specific */
|
||||
TEGRA_LA_PCIE1W, /* T19x specific */
|
||||
TEGRA_LA_PCIE2AR, /* T19x specific */
|
||||
TEGRA_LA_PCIE2AW, /* T19x specific */
|
||||
TEGRA_LA_PCIE3R, /* T19x specific */
|
||||
TEGRA_LA_PCIE3W, /* T19x specific */
|
||||
TEGRA_LA_PCIE4R, /* T19x specific */
|
||||
TEGRA_LA_PCIE4W, /* T19x specific */
|
||||
TEGRA_LA_PCIE5R, /* T19x specific */
|
||||
TEGRA_LA_PCIE5W, /* T19x specific */
|
||||
TEGRA_LA_PCIE0R1, /* T19x specific */
|
||||
TEGRA_LA_PCIE5R1, /* T19x specific */
|
||||
TEGRA_LA_PVA0RDA, /* T19x specific */
|
||||
TEGRA_LA_PVA0RDB, /* T19x specific */
|
||||
TEGRA_LA_PVA0RDC, /* T19x specific */
|
||||
TEGRA_LA_PVA0WRA, /* T19x specific */
|
||||
TEGRA_LA_PVA0WRB, /* T19x specific */
|
||||
TEGRA_LA_PVA0WRC, /* T19x specific */
|
||||
TEGRA_LA_PVA0RDA1, /* T19x specific */
|
||||
TEGRA_LA_PVA0RDB1, /* T19x specific */
|
||||
TEGRA_LA_PVA1RDA, /* T19x specific */
|
||||
TEGRA_LA_PVA1RDB, /* T19x specific */
|
||||
TEGRA_LA_PVA1RDC, /* T19x specific */
|
||||
TEGRA_LA_PVA1WRA, /* T19x specific */
|
||||
TEGRA_LA_PVA1WRB, /* T19x specific */
|
||||
TEGRA_LA_PVA1WRC, /* T19x specific */
|
||||
TEGRA_LA_PVA1RDA1, /* T19x specific */
|
||||
TEGRA_LA_PVA1RDB1, /* T19x specific */
|
||||
TEGRA_LA_RCEDMAR, /* T19x specific */
|
||||
TEGRA_LA_RCEDMAW, /* T19x specific */
|
||||
TEGRA_LA_RCER, /* T19x specific */
|
||||
TEGRA_LA_RCEW, /* T19x specific */
|
||||
TEGRA_LA_TSECSRDB, /* T19x specific */
|
||||
TEGRA_LA_TSECSWRB, /* T19x specific */
|
||||
TEGRA_LA_VIW, /* T19x specific */
|
||||
TEGRA_LA_VICSRD1, /* T19x specific */
|
||||
TEGRA_LA_VIFALR, /* T19x specific */
|
||||
TEGRA_LA_VIFALW, /* T19x specific */
|
||||
TEGRA_LA_WCAM, /* T19x specific */
|
||||
TEGRA_LA_NVLRHP, /* T19x specific */
|
||||
TEGRA_LA_DGPU, /* T19x specific */
|
||||
TEGRA_LA_IGPU, /* T19x specific */
|
||||
|
||||
TEGRA_LA_MAX_ID
|
||||
};
|
||||
|
||||
enum disp_win_type {
|
||||
TEGRA_LA_DISP_WIN_TYPE_FULL,
|
||||
TEGRA_LA_DISP_WIN_TYPE_FULLA,
|
||||
TEGRA_LA_DISP_WIN_TYPE_FULLB,
|
||||
TEGRA_LA_DISP_WIN_TYPE_SIMPLE,
|
||||
TEGRA_LA_DISP_WIN_TYPE_CURSOR,
|
||||
TEGRA_LA_DISP_WIN_TYPE_NUM_TYPES
|
||||
};
|
||||
|
||||
struct disp_client {
|
||||
enum disp_win_type win_type;
|
||||
unsigned int mccif_size_bytes;
|
||||
unsigned int line_buf_sz_bytes;
|
||||
};
|
||||
|
||||
struct dc_to_la_params {
|
||||
unsigned int thresh_lwm_bytes;
|
||||
unsigned int spool_up_buffering_adj_bytes;
|
||||
unsigned int drain_time_usec_fp;
|
||||
unsigned int total_dc0_bw;
|
||||
unsigned int total_dc1_bw;
|
||||
};
|
||||
|
||||
struct la_to_dc_params {
|
||||
unsigned int fp_factor;
|
||||
unsigned int (*la_real_to_fp)(unsigned int val);
|
||||
unsigned int (*la_fp_to_real)(unsigned int val);
|
||||
unsigned int static_la_minus_snap_arb_to_row_srt_emcclks_fp;
|
||||
unsigned int dram_width_bits;
|
||||
unsigned int disp_catchup_factor_fp;
|
||||
};
|
||||
|
||||
int tegra_set_disp_latency_allowance(enum tegra_la_id id,
|
||||
unsigned long emc_freq_hz,
|
||||
unsigned int bandwidth_in_mbps,
|
||||
struct dc_to_la_params disp_params);
|
||||
|
||||
int tegra_check_disp_latency_allowance(enum tegra_la_id id,
|
||||
unsigned long emc_freq_hz,
|
||||
unsigned int bw_mbps,
|
||||
struct dc_to_la_params disp_params);
|
||||
|
||||
int tegra_set_latency_allowance(enum tegra_la_id id,
|
||||
unsigned int bandwidth_in_mbps);
|
||||
|
||||
int tegra_set_camera_ptsa(enum tegra_la_id id,
|
||||
unsigned int bw_mbps,
|
||||
int is_hiso);
|
||||
|
||||
void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick);
|
||||
|
||||
int tegra_enable_latency_scaling(enum tegra_la_id id,
|
||||
unsigned int threshold_low,
|
||||
unsigned int threshold_mid,
|
||||
unsigned int threshold_high);
|
||||
|
||||
void tegra_disable_latency_scaling(enum tegra_la_id id);
|
||||
|
||||
void mc_pcie_init(void);
|
||||
|
||||
struct la_to_dc_params tegra_get_la_to_dc_params(void);
|
||||
|
||||
extern const struct disp_client *tegra_la_disp_clients_info;
|
||||
|
||||
#endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */
|
||||
Reference in New Issue
Block a user