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media: camera: Build tegra-camera as OOT module

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Port camera drivers below from /kenrel/nvidia to
/kernel/nvidia-oot as OOT modules:
- Fusa-capture driver
- Tegra V4L2 framework driver
- vi/csi driver
- tegra camera platform driver

Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698
Reviewed-by: FNU Raunak <fraunak@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>
Reviewed-by: Shiva Dubey <sdubey@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Frank Chen
2022-09-22 16:01:45 -07:00
committed by mobile promotions
parent e2b55e1a2c
commit 92ac7bc35a
74 changed files with 28226 additions and 0 deletions
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290
include/uapi/linux/nvhost_events.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Eventlib interface for PVA
*
* Copyright (c) 2016-2022, NVIDIA Corporation. All rights reserved.
*/
#ifndef NVHOST_EVENTS_H
#define NVHOST_EVENTS_H
enum {
NVHOST_SCHEMA_VERSION = 1
};
#define NVHOST_EVENT_PROVIDER_NAME "nv_mm_nvhost"
/* Marks that the task is submitted to hardware */
struct nvhost_task_submit {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/* PID */
__u32 pid;
/* TID */
__u32 tid;
/* Channel ID */
__u32 channel_id;
} __packed;
/* Marks that the task is moving to execution */
struct nvhost_task_begin {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/* Channel ID */
__u32 channel_id;
} __packed;
/* Marks that the task is completed */
struct nvhost_task_end {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/* Channel ID */
__u32 channel_id;
} __packed;
struct nvhost_vpu_perf_counter {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/* Identifier for the R5/VPU algorithm executed */
__u32 operation;
/* Algorithm specific identifying tag for the perf counter */
__u32 tag;
__u32 count;
__u32 average;
__u64 variance;
__u32 minimum;
__u32 maximum;
} __packed;
/* Marks the pre/postfence associated with the task */
struct nvhost_task_fence {
/* Engine class ID */
__u32 class_id;
/* Kind (prefence or postfence) */
__u32 kind;
/* Fence-specific type (see nvdev_fence.h) */
__u32 fence_type;
/* Valid for NVDEV_FENCE_TYPE_SYNCPT only */
__u32 syncpt_id;
__u32 syncpt_thresh;
/* The task this fence is associated with */
__u32 task_syncpt_id;
__u32 task_syncpt_thresh;
/* Valid for NVDEV_FENCE_TYPE_SYNC_FD only */
__u32 sync_fd;
/* Valid for NVDEV_FENCE_TYPE_SEMAPHORE
and NVDEV_FENCE_TYPE_SEMAPHORE_TS */
__u32 semaphore_handle;
__u32 semaphore_offset;
__u32 semaphore_value;
} __packed;
struct nvhost_pva_task_state {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/** ID of the VPU on which task was run. 0 or 1 */
__u8 vpu_id;
/** ID of the FW Queue on which the task was run. [0, 7] */
__u8 queue_id;
/* Identifier for the R5/VPU algorithm executed */
__u64 iova;
} __packed;
/* Marks that the task is submitted to hardware */
struct nv_camera_task_submit {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
/* PID */
__u32 pid;
/* TID */
__u32 tid;
} __packed;
/* Marks that the task is moving to execution */
struct nv_camera_task_begin {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
} __packed;
/* Marks that the task is completed */
struct nv_camera_task_end {
/* Engine class ID */
__u32 class_id;
/* Syncpoint ID */
__u32 syncpt_id;
/* Threshold for task completion */
__u32 syncpt_thresh;
} __packed;
/* Marks that we are logging a general task */
struct nv_camera_task_log {
/* Engine class ID */
__u32 class_id;
/* PID */
__u32 pid;
/* TID */
__u32 tid;
} __packed;
enum {
/* struct nvhost_task_submit */
NVHOST_TASK_SUBMIT = 0,
/* struct nvhost_task_begin */
NVHOST_TASK_BEGIN = 1,
/* struct nvhost_task_end */
NVHOST_TASK_END = 2,
/* struct nvhost_task_fence */
NVHOST_TASK_FENCE = 3,
NVHOST_VPU_PERF_COUNTER_BEGIN = 4,
NVHOST_VPU_PERF_COUNTER_END = 5,
/* struct nvhost_pva_task_state */
NVHOST_PVA_QUEUE_BEGIN = 6,
NVHOST_PVA_QUEUE_END = 7,
NVHOST_PVA_PREPARE_BEGIN = 8,
NVHOST_PVA_PREPARE_END = 9,
NVHOST_PVA_VPU0_BEGIN = 10,
NVHOST_PVA_VPU0_END = 11,
NVHOST_PVA_VPU1_BEGIN = 12,
NVHOST_PVA_VPU1_END = 13,
NVHOST_PVA_POST_BEGIN = 14,
NVHOST_PVA_POST_END = 15,
/* struct nv_camera_vi_capture_setup */
NVHOST_CAMERA_VI_CAPTURE_SETUP = 16,
/* struct nv_camera_vi_capture_reset */
NVHOST_CAMERA_VI_CAPTURE_RESET = 17,
/* struct nv_camera_vi_capture_release */
NVHOST_CAMERA_VI_CAPTURE_RELEASE = 18,
/* struct nv_camera_vi_capture_get_info */
NVHOST_CAMERA_VI_CAPTURE_GET_INFO = 19,
/* struct nv_camera_vi_capture_set_config */
NVHOST_CAMERA_VI_CAPTURE_SET_CONFIG = 20,
/* struct nv_camera_vi_capture_request */
NVHOST_CAMERA_VI_CAPTURE_REQUEST = 21,
/* struct nv_camera_vi_capture_status */
NVHOST_CAMERA_VI_CAPTURE_STATUS = 22,
/* struct nv_camera_vi_capture_set_progress_status */
NVHOST_CAMERA_VI_CAPTURE_SET_PROGRESS_STATUS = 24,
/* struct nv_camera_isp_capture_setup */
NVHOST_CAMERA_ISP_CAPTURE_SETUP = 25,
/* struct nv_camera_isp_capture_reset */
NVHOST_CAMERA_ISP_CAPTURE_RESET = 26,
/* struct nv_camera_isp_capture_release */
NVHOST_CAMERA_ISP_CAPTURE_RELEASE = 27,
/* struct nv_camera_isp_capture_get_info */
NVHOST_CAMERA_ISP_CAPTURE_GET_INFO = 28,
/* struct nv_camera_isp_capture_request */
NVHOST_CAMERA_ISP_CAPTURE_REQUEST = 29,
/* struct nv_camera_isp_capture_status */
NVHOST_CAMERA_ISP_CAPTURE_STATUS = 30,
/* struct nv_camera_isp_capture_program_request */
NVHOST_CAMERA_ISP_CAPTURE_PROGRAM_REQUEST = 31,
/* struct nv_camera_isp_capture_program_status */
NVHOST_CAMERA_ISP_CAPTURE_PROGRAM_STATUS = 32,
/* struct nv_camera_isp_capture_request_ex */
NVHOST_CAMERA_ISP_CAPTURE_REQUEST_EX = 33,
/* struct nv_camera_isp_capture_set_progress_status */
NVHOST_CAMERA_ISP_CAPTURE_SET_PROGRESS_STATUS = 34,
/* struct nv_camera_task_log */
NVHOST_CAMERA_TASK_LOG = 35,
NVHOST_NUM_EVENT_TYPES = 36
};
enum {
NVHOST_NUM_CUSTOM_FILTER_FLAGS = 0
};
#endif /* NVHOST_EVENTS_H */

71
include/uapi/linux/nvhost_nvcsi_ioctl.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Tegra NVCSI Driver
*
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
#define __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
#include <linux/ioctl.h>
#include <linux/types.h>
#if !defined(__KERNEL__)
#define __user
#endif
/* Bitmap
*
* | PHY_2 | PHY_1 | PHY_0 |
* | 11 10 | 9 8 | 7 6 | 5 4 | 3 2 | 1 0 |
* | CILB | CILA | CILB | CILA | CILB | CILA |
*/
#define PHY_0_CIL_A_IO0 0
#define PHY_0_CIL_A_IO1 1
#define PHY_0_CIL_B_IO0 2
#define PHY_0_CIL_B_IO1 3
#define PHY_1_CIL_A_IO0 4
#define PHY_1_CIL_A_IO1 5
#define PHY_1_CIL_B_IO0 6
#define PHY_1_CIL_B_IO1 7
#define PHY_2_CIL_A_IO0 8
#define PHY_2_CIL_A_IO1 9
#define PHY_2_CIL_B_IO0 10
#define PHY_2_CIL_B_IO1 11
#define PHY_3_CIL_A_IO0 12
#define PHY_3_CIL_A_IO1 13
#define PHY_3_CIL_B_IO0 14
#define PHY_3_CIL_B_IO1 15
#define NVCSI_PHY_CIL_NUM_LANE 16
#define NVCSI_PHY_0_NVCSI_CIL_A_IO0 (0x1 << PHY_0_CIL_A_IO0)
#define NVCSI_PHY_0_NVCSI_CIL_A_IO1 (0x1 << PHY_0_CIL_A_IO1)
#define NVCSI_PHY_0_NVCSI_CIL_B_IO0 (0x1 << PHY_0_CIL_B_IO0)
#define NVCSI_PHY_0_NVCSI_CIL_B_IO1 (0x1 << PHY_0_CIL_B_IO1)
#define NVCSI_PHY_1_NVCSI_CIL_A_IO0 (0x1 << PHY_1_CIL_A_IO0)
#define NVCSI_PHY_1_NVCSI_CIL_A_IO1 (0x1 << PHY_1_CIL_A_IO1)
#define NVCSI_PHY_1_NVCSI_CIL_B_IO0 (0x1 << PHY_1_CIL_B_IO0)
#define NVCSI_PHY_1_NVCSI_CIL_B_IO1 (0x1 << PHY_1_CIL_B_IO1)
#define NVCSI_PHY_2_NVCSI_CIL_A_IO0 (0x1 << PHY_2_CIL_A_IO0)
#define NVCSI_PHY_2_NVCSI_CIL_A_IO1 (0x1 << PHY_2_CIL_A_IO1)
#define NVCSI_PHY_2_NVCSI_CIL_B_IO0 (0x1 << PHY_2_CIL_B_IO0)
#define NVCSI_PHY_2_NVCSI_CIL_B_IO1 (0x1 << PHY_2_CIL_B_IO1)
#define NVCSI_PHY_3_NVCSI_CIL_A_IO0 (0x1 << PHY_3_CIL_A_IO0)
#define NVCSI_PHY_3_NVCSI_CIL_A_IO1 (0x1 << PHY_3_CIL_A_IO1)
#define NVCSI_PHY_3_NVCSI_CIL_B_IO0 (0x1 << PHY_3_CIL_B_IO0)
#define NVCSI_PHY_3_NVCSI_CIL_B_IO1 (0x1 << PHY_3_CIL_B_IO1)
#define NVCSI_PHY_NUM_BRICKS 4
#define NVHOST_NVCSI_IOCTL_MAGIC 'N'
#define NVHOST_NVCSI_IOCTL_DESKEW_SETUP _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 1, long)
#define NVHOST_NVCSI_IOCTL_DESKEW_APPLY _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 2, long)
#endif

33
include/uapi/linux/nvhost_vi_ioctl.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Tegra VI Driver
*
* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __UAPI_LINUX_NVHOST_VI_IOCTL_H
#define __UAPI_LINUX_NVHOST_VI_IOCTL_H
#include <linux/ioctl.h>
#include <linux/types.h>
#if !defined(__KERNEL__)
#define __user
#endif
#define NVHOST_VI_IOCTL_MAGIC 'V'
/*
* /dev/nvhost-ctrl-vi devices
*
* Opening a '/dev/nvhost-ctrl-vi' device node creates a way to send
* ctrl ioctl to vi driver.
*
* /dev/nvhost-vi is for channel (context specific) operations. We use
* /dev/nvhost-ctrl-vi for global (context independent) operations on
* vi device.
*/
#define NVHOST_VI_IOCTL_ENABLE_TPG _IOW(NVHOST_VI_IOCTL_MAGIC, 1, uint)
#endif

119
include/uapi/media/camera_device.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* camera device driver header
*
* Copyright (c) 2018-2022 NVIDIA Corporation. All rights reserved.
*/
#ifndef __UAPI_CAMERA_DEVICE_H_
#define __UAPI_CAMERA_DEVICE_H_
#include <linux/types.h>
#include <linux/ioctl.h>
#define __CAMERA_DEVICE_ALIGN __aligned(8)
/* Sensor, focuser, iris etc., */
#define MAX_DEVICES_PER_CHANNEL 4
/*
* Increasing below values must validate
* copy_from or copy_to works properly
*/
#define MAX_COMMANDS 256
#define MAX_BLOB_SIZE 2048
struct i2c_bus {
__u32 reg_base;
__u32 clk_rate;
__u32 flags;
__u8 reserved[4];
};
struct i2c_mux {
bool is_mux_valid;
__u8 mux_channel;
__u16 mux_addr;
__u8 reserved[4];
};
struct i2c_dev {
__u16 addr;
__u8 pad[2];
__u32 flags;
};
struct spi_bus {
__u32 reg_base;
__u32 clk_rate;
__u32 flags;
__u8 reserved[4];
};
struct spi_dev {
__u8 port;
__u16 addr;
__u8 pad;
__u32 flags;
__u8 pad1[4];
};
struct i2c_sensor_cfg {
__u32 num_devs;
struct i2c_bus bus;
struct i2c_mux mux;
struct i2c_dev sd[MAX_DEVICES_PER_CHANNEL];
};
struct spi_sensor_cfg {
__u32 num_devs;
struct spi_bus bus;
struct spi_dev sd[MAX_DEVICES_PER_CHANNEL];
};
struct sensor_cfg {
__u8 type; /* SPI or I2C */
__u8 pad[3]; /* for alignment */
union {
struct i2c_sensor_cfg i2c_sensor;
struct spi_sensor_cfg spi_sensor;
} u;
} __CAMERA_DEVICE_ALIGN;
struct sensor_cmd {
__u32 opcode;
__u32 addr;
};
struct sensor_blob {
__u32 num_cmds;
__u32 buf_size;
struct sensor_cmd cmds[MAX_COMMANDS];
__u8 buf[MAX_BLOB_SIZE];
} __CAMERA_DEVICE_ALIGN;
struct sensor_blob_cfg {
__u32 nlines;
struct sensor_blob *blob;
} __CAMERA_DEVICE_ALIGN;
#define CAMERA_DEVICE_NONE 0
#define CAMERA_DEVICE_I2C_SENSOR (0x1 << 1)
#define CAMERA_DEVICE_SPI_SENSOR (0x1 << 2)
/* Future extensions - if necessary */
#define CAMERA_DEVICE_VI (0x1 << 8)
#define CAMERA_DEVICE_CSI (0x1 << 9)
#define CAMERA_DEVICE_ISP (0x1 << 16)
struct camdev_chan_cfg {
__u32 type;
struct sensor_cfg scfg;
} __CAMERA_DEVICE_ALIGN;
/* common functionality */
#define CAMERA_DEVICE_REGISTER _IOW('C', 1, struct camdev_chan_cfg)
#define CAMERA_DEVICE_UNREGISTER _IOW('C', 2, __u32)
/* sensor functionality */
#define SENSOR_BLOB_EXECUTE _IOW('C', 10, struct sensor_blob_cfg)
#endif

21
include/uapi/media/tegra_camera_platform.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _UAPI_TEGRA_CAMERA_PLATFORM_H_
#define _UAPI_TEGRA_CAMERA_PLATFORM_H_
#include <linux/ioctl.h>
#include <linux/types.h>
#define TEGRA_CAMERA_IOCTL_SET_BW _IOW('o', 1, struct bw_info)
#define TEGRA_CAMERA_IOCTL_GET_BW _IOR('o', 2, __u64)
#define TEGRA_CAMERA_IOCTL_GET_CURR_REQ_ISO_BW _IOR('o', 3, __u64)
struct bw_info {
__u8 is_iso;
__u64 bw;
};
#endif