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media: camera: Build tegra-camera as OOT module
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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290
include/uapi/linux/nvhost_events.h
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290
include/uapi/linux/nvhost_events.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Eventlib interface for PVA
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*
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* Copyright (c) 2016-2022, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef NVHOST_EVENTS_H
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#define NVHOST_EVENTS_H
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enum {
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NVHOST_SCHEMA_VERSION = 1
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};
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#define NVHOST_EVENT_PROVIDER_NAME "nv_mm_nvhost"
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/* Marks that the task is submitted to hardware */
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struct nvhost_task_submit {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/* PID */
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__u32 pid;
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/* TID */
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__u32 tid;
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/* Channel ID */
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__u32 channel_id;
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} __packed;
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/* Marks that the task is moving to execution */
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struct nvhost_task_begin {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/* Channel ID */
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__u32 channel_id;
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} __packed;
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/* Marks that the task is completed */
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struct nvhost_task_end {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/* Channel ID */
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__u32 channel_id;
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} __packed;
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struct nvhost_vpu_perf_counter {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/* Identifier for the R5/VPU algorithm executed */
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__u32 operation;
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/* Algorithm specific identifying tag for the perf counter */
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__u32 tag;
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__u32 count;
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__u32 average;
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__u64 variance;
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__u32 minimum;
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__u32 maximum;
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} __packed;
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/* Marks the pre/postfence associated with the task */
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struct nvhost_task_fence {
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/* Engine class ID */
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__u32 class_id;
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/* Kind (prefence or postfence) */
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__u32 kind;
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/* Fence-specific type (see nvdev_fence.h) */
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__u32 fence_type;
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/* Valid for NVDEV_FENCE_TYPE_SYNCPT only */
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__u32 syncpt_id;
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__u32 syncpt_thresh;
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/* The task this fence is associated with */
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__u32 task_syncpt_id;
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__u32 task_syncpt_thresh;
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/* Valid for NVDEV_FENCE_TYPE_SYNC_FD only */
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__u32 sync_fd;
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/* Valid for NVDEV_FENCE_TYPE_SEMAPHORE
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and NVDEV_FENCE_TYPE_SEMAPHORE_TS */
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__u32 semaphore_handle;
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__u32 semaphore_offset;
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__u32 semaphore_value;
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} __packed;
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struct nvhost_pva_task_state {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/** ID of the VPU on which task was run. 0 or 1 */
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__u8 vpu_id;
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/** ID of the FW Queue on which the task was run. [0, 7] */
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__u8 queue_id;
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/* Identifier for the R5/VPU algorithm executed */
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__u64 iova;
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} __packed;
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/* Marks that the task is submitted to hardware */
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struct nv_camera_task_submit {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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/* PID */
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__u32 pid;
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/* TID */
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__u32 tid;
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} __packed;
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/* Marks that the task is moving to execution */
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struct nv_camera_task_begin {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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} __packed;
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/* Marks that the task is completed */
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struct nv_camera_task_end {
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/* Engine class ID */
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__u32 class_id;
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/* Syncpoint ID */
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__u32 syncpt_id;
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/* Threshold for task completion */
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__u32 syncpt_thresh;
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} __packed;
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/* Marks that we are logging a general task */
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struct nv_camera_task_log {
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/* Engine class ID */
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__u32 class_id;
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/* PID */
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__u32 pid;
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/* TID */
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__u32 tid;
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} __packed;
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enum {
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/* struct nvhost_task_submit */
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NVHOST_TASK_SUBMIT = 0,
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/* struct nvhost_task_begin */
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NVHOST_TASK_BEGIN = 1,
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/* struct nvhost_task_end */
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NVHOST_TASK_END = 2,
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/* struct nvhost_task_fence */
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NVHOST_TASK_FENCE = 3,
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NVHOST_VPU_PERF_COUNTER_BEGIN = 4,
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NVHOST_VPU_PERF_COUNTER_END = 5,
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/* struct nvhost_pva_task_state */
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NVHOST_PVA_QUEUE_BEGIN = 6,
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NVHOST_PVA_QUEUE_END = 7,
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NVHOST_PVA_PREPARE_BEGIN = 8,
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NVHOST_PVA_PREPARE_END = 9,
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NVHOST_PVA_VPU0_BEGIN = 10,
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NVHOST_PVA_VPU0_END = 11,
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NVHOST_PVA_VPU1_BEGIN = 12,
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NVHOST_PVA_VPU1_END = 13,
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NVHOST_PVA_POST_BEGIN = 14,
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NVHOST_PVA_POST_END = 15,
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/* struct nv_camera_vi_capture_setup */
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NVHOST_CAMERA_VI_CAPTURE_SETUP = 16,
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/* struct nv_camera_vi_capture_reset */
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NVHOST_CAMERA_VI_CAPTURE_RESET = 17,
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/* struct nv_camera_vi_capture_release */
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NVHOST_CAMERA_VI_CAPTURE_RELEASE = 18,
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/* struct nv_camera_vi_capture_get_info */
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NVHOST_CAMERA_VI_CAPTURE_GET_INFO = 19,
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/* struct nv_camera_vi_capture_set_config */
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NVHOST_CAMERA_VI_CAPTURE_SET_CONFIG = 20,
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/* struct nv_camera_vi_capture_request */
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NVHOST_CAMERA_VI_CAPTURE_REQUEST = 21,
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/* struct nv_camera_vi_capture_status */
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NVHOST_CAMERA_VI_CAPTURE_STATUS = 22,
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/* struct nv_camera_vi_capture_set_progress_status */
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NVHOST_CAMERA_VI_CAPTURE_SET_PROGRESS_STATUS = 24,
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/* struct nv_camera_isp_capture_setup */
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NVHOST_CAMERA_ISP_CAPTURE_SETUP = 25,
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/* struct nv_camera_isp_capture_reset */
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NVHOST_CAMERA_ISP_CAPTURE_RESET = 26,
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/* struct nv_camera_isp_capture_release */
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NVHOST_CAMERA_ISP_CAPTURE_RELEASE = 27,
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/* struct nv_camera_isp_capture_get_info */
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NVHOST_CAMERA_ISP_CAPTURE_GET_INFO = 28,
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/* struct nv_camera_isp_capture_request */
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NVHOST_CAMERA_ISP_CAPTURE_REQUEST = 29,
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/* struct nv_camera_isp_capture_status */
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NVHOST_CAMERA_ISP_CAPTURE_STATUS = 30,
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/* struct nv_camera_isp_capture_program_request */
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NVHOST_CAMERA_ISP_CAPTURE_PROGRAM_REQUEST = 31,
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/* struct nv_camera_isp_capture_program_status */
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NVHOST_CAMERA_ISP_CAPTURE_PROGRAM_STATUS = 32,
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/* struct nv_camera_isp_capture_request_ex */
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NVHOST_CAMERA_ISP_CAPTURE_REQUEST_EX = 33,
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/* struct nv_camera_isp_capture_set_progress_status */
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NVHOST_CAMERA_ISP_CAPTURE_SET_PROGRESS_STATUS = 34,
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/* struct nv_camera_task_log */
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NVHOST_CAMERA_TASK_LOG = 35,
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NVHOST_NUM_EVENT_TYPES = 36
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};
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enum {
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NVHOST_NUM_CUSTOM_FILTER_FLAGS = 0
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};
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#endif /* NVHOST_EVENTS_H */
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71
include/uapi/linux/nvhost_nvcsi_ioctl.h
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71
include/uapi/linux/nvhost_nvcsi_ioctl.h
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@@ -0,0 +1,71 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra NVCSI Driver
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*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#define __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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/* Bitmap
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*
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* | PHY_2 | PHY_1 | PHY_0 |
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* | 11 10 | 9 8 | 7 6 | 5 4 | 3 2 | 1 0 |
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* | CILB | CILA | CILB | CILA | CILB | CILA |
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*/
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#define PHY_0_CIL_A_IO0 0
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#define PHY_0_CIL_A_IO1 1
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#define PHY_0_CIL_B_IO0 2
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#define PHY_0_CIL_B_IO1 3
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#define PHY_1_CIL_A_IO0 4
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#define PHY_1_CIL_A_IO1 5
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#define PHY_1_CIL_B_IO0 6
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#define PHY_1_CIL_B_IO1 7
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#define PHY_2_CIL_A_IO0 8
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#define PHY_2_CIL_A_IO1 9
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#define PHY_2_CIL_B_IO0 10
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#define PHY_2_CIL_B_IO1 11
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#define PHY_3_CIL_A_IO0 12
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#define PHY_3_CIL_A_IO1 13
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#define PHY_3_CIL_B_IO0 14
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#define PHY_3_CIL_B_IO1 15
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#define NVCSI_PHY_CIL_NUM_LANE 16
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO0 (0x1 << PHY_0_CIL_A_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO1 (0x1 << PHY_0_CIL_A_IO1)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO0 (0x1 << PHY_0_CIL_B_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO1 (0x1 << PHY_0_CIL_B_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO0 (0x1 << PHY_1_CIL_A_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO1 (0x1 << PHY_1_CIL_A_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO0 (0x1 << PHY_1_CIL_B_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO1 (0x1 << PHY_1_CIL_B_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO0 (0x1 << PHY_2_CIL_A_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO1 (0x1 << PHY_2_CIL_A_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO0 (0x1 << PHY_2_CIL_B_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO1 (0x1 << PHY_2_CIL_B_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO0 (0x1 << PHY_3_CIL_A_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO1 (0x1 << PHY_3_CIL_A_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO0 (0x1 << PHY_3_CIL_B_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO1 (0x1 << PHY_3_CIL_B_IO1)
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#define NVCSI_PHY_NUM_BRICKS 4
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#define NVHOST_NVCSI_IOCTL_MAGIC 'N'
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#define NVHOST_NVCSI_IOCTL_DESKEW_SETUP _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 1, long)
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#define NVHOST_NVCSI_IOCTL_DESKEW_APPLY _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 2, long)
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#endif
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33
include/uapi/linux/nvhost_vi_ioctl.h
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include/uapi/linux/nvhost_vi_ioctl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra VI Driver
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*
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* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __UAPI_LINUX_NVHOST_VI_IOCTL_H
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#define __UAPI_LINUX_NVHOST_VI_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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#define NVHOST_VI_IOCTL_MAGIC 'V'
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/*
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* /dev/nvhost-ctrl-vi devices
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*
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* Opening a '/dev/nvhost-ctrl-vi' device node creates a way to send
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* ctrl ioctl to vi driver.
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*
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* /dev/nvhost-vi is for channel (context specific) operations. We use
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* /dev/nvhost-ctrl-vi for global (context independent) operations on
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* vi device.
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*/
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#define NVHOST_VI_IOCTL_ENABLE_TPG _IOW(NVHOST_VI_IOCTL_MAGIC, 1, uint)
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#endif
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