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gpu: host1x: Add MLOCK release code on Tegra234

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With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only implement
this on Tegra234 for the time being.

Bug 3724727

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: Icc15ae705844cd26ae3f1d1146ff20f1d9b7a14d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2745956
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Mikko Perttunen
2022-05-15 12:31:34 +03:00
committed by Laxman Dewangan
parent 4354d2bf92
commit 951a3d1efa
2 changed files with 41 additions and 0 deletions
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34
drivers/gpu/host1x/hw/cdma_hw.c
View File

@@ -238,6 +238,37 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr)
cdma_timeout_restart(cdma, getptr); cdma_timeout_restart(cdma, getptr);
} }
static void timeout_release_mlock(struct host1x_cdma *cdma)
{
#if HOST1X_HW >= 8
/* Tegra186 and Tegra194 require a more complicated MLOCK release
* sequence. Furthermore, those chips by default don't enforce MLOCKs,
* so it turns out that if we don't /actually/ need MLOCKs, we can just
* ignore them.
*
* As such, for now just implement this on Tegra234 where things are
* stricter but also easy to implement.
*/
struct host1x_channel *ch = cdma_to_channel(cdma);
struct host1x *host1x = cdma_to_host1x(cdma);
u32 offset;
switch (ch->client->class) {
case HOST1X_CLASS_VIC:
offset = HOST1X_COMMON_VIC_MLOCK;
break;
case HOST1X_CLASS_NVDEC:
offset = HOST1X_COMMON_NVDEC_MLOCK;
break;
default:
WARN(1, "%s was not updated for class %u", __func__, ch->client->class);
return;
}
host1x_common_writel(host1x, 0x0, offset);
#endif
}
/* /*
* If this timeout fires, it indicates the current sync_queue entry has * If this timeout fires, it indicates the current sync_queue entry has
* exceeded its TTL and the userctx should be timed out and remaining * exceeded its TTL and the userctx should be timed out and remaining
@@ -288,6 +319,9 @@ static void cdma_timeout_handler(struct work_struct *work)
/* stop HW, resetting channel/module */ /* stop HW, resetting channel/module */
host1x_hw_cdma_freeze(host1x, cdma); host1x_hw_cdma_freeze(host1x, cdma);
/* release any held MLOCK */
timeout_release_mlock(cdma);
host1x_cdma_update_sync_queue(cdma, ch->dev); host1x_cdma_update_sync_queue(cdma, ch->dev);
mutex_unlock(&cdma->lock); mutex_unlock(&cdma->lock);
} }

7
drivers/gpu/host1x/hw/hw_host1x08_common.h
View File

@@ -2,3 +2,10 @@
/* /*
* Copyright (c) 2022 NVIDIA Corporation. * Copyright (c) 2022 NVIDIA Corporation.
*/ */
#define HOST1X_COMMON_OFA_MLOCK 0x4050
#define HOST1X_COMMON_NVJPG1_MLOCK 0x4070
#define HOST1X_COMMON_VIC_MLOCK 0x4078
#define HOST1X_COMMON_NVENC_MLOCK 0x407c
#define HOST1X_COMMON_NVDEC_MLOCK 0x4080
#define HOST1X_COMMON_NVJPG_MLOCK 0x4084