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ASoC: tegra-alt: fix admaif regmap callback func

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The regmap read, write and volatile callback functions are not
handling the register address checks correctly. Due to this the
regmap dump from sysfs node was not reflecting the correct state
of the register values. Fix the issue and makesure all regmap
register values are reflecting proper values.

Bug 200500656

Change-Id: Ifb5827d1b86384f835c010138275121a87a397ba
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2080753
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mohan Kumar
2019-03-25 14:59:20 +05:30
committed by Sameer Pujar
parent c9afbf06b8
commit 95dd5b9e73
2 changed files with 141 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
sound/soc/tegra-alt/include/tegra210_admaif_alt.h
View File

@@ -27,11 +27,13 @@
#define TEGRA210_ADMAIF_CHANNEL_COUNT 10 #define TEGRA210_ADMAIF_CHANNEL_COUNT 10
#define TEGRA186_ADMAIF_CHANNEL_COUNT 20 #define TEGRA186_ADMAIF_CHANNEL_COUNT 20
#define TEGRA210_ADMAIF_XBAR_TX_ENABLE 0x300 #define TEGRA210_ADMAIF_XBAR_RX_BASE 0x0
#define TEGRA210_ADMAIF_GLOBAL_ENABLE 0x700 #define TEGRA210_ADMAIF_XBAR_TX_BASE 0x300
#define TEGRA210_ADMAIF_GLOBAL_BASE 0x700
#define TEGRA186_ADMAIF_XBAR_TX_ENABLE 0x500 #define TEGRA186_ADMAIF_XBAR_RX_BASE 0x0
#define TEGRA186_ADMAIF_GLOBAL_ENABLE 0xd00 #define TEGRA186_ADMAIF_XBAR_TX_BASE 0x500
#define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00
#define TEGRA_ADMAIF_XBAR_RX_ENABLE 0x0 #define TEGRA_ADMAIF_XBAR_RX_ENABLE 0x0
#define TEGRA_ADMAIF_XBAR_RX_SOFT_RESET 0x4 #define TEGRA_ADMAIF_XBAR_RX_SOFT_RESET 0x4
@@ -43,17 +45,22 @@
#define TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL 0x20 #define TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL 0x20
#define TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL 0x28 #define TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL 0x28
#define TEGRA_ADMAIF_XBAR_RX_FIFO_READ 0x2c #define TEGRA_ADMAIF_XBAR_RX_FIFO_READ 0x2c
#define TEGRA_ADMAIF_GLOBAL_CG_0 (0x8) #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0
#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8
#define TEGRA_ADMAIF_GLOBAL_STATUS 0x10
#define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20
#define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24
#define TEGRA_ADMAIF_XBAR_TX_SOFT_RESET (0x4) #define TEGRA_ADMAIF_XBAR_TX_ENABLE 0x0
#define TEGRA_ADMAIF_XBAR_TX_STATUS (0xc) #define TEGRA_ADMAIF_XBAR_TX_SOFT_RESET 0x4
#define TEGRA_ADMAIF_XBAR_TX_INT_STATUS (0x10) #define TEGRA_ADMAIF_XBAR_TX_STATUS 0xc
#define TEGRA_ADMAIF_XBAR_TX_INT_MASK (0x14) #define TEGRA_ADMAIF_XBAR_TX_INT_STATUS 0x10
#define TEGRA_ADMAIF_XBAR_TX_INT_SET (0x18) #define TEGRA_ADMAIF_XBAR_TX_INT_MASK 0x14
#define TEGRA_ADMAIF_XBAR_TX_INT_CLEAR (0x1c) #define TEGRA_ADMAIF_XBAR_TX_INT_SET 0x18
#define TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL (0x20) #define TEGRA_ADMAIF_XBAR_TX_INT_CLEAR 0x1c
#define TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL (0x28) #define TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL 0x20
#define TEGRA_ADMAIF_XBAR_TX_FIFO_WRITE (0x2c) #define TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL 0x28
#define TEGRA_ADMAIF_XBAR_TX_FIFO_WRITE 0x2c
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_SHIFT 31 #define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_SHIFT 31
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_MASK \ #define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_MASK \
@@ -149,14 +156,8 @@ enum {
}; };
struct admaif_reg_offsets {
unsigned int global_enable;
unsigned int tx_enable;
};
struct tegra_admaif_soc_data { struct tegra_admaif_soc_data {
unsigned int num_ch; unsigned int num_ch;
struct admaif_reg_offsets reg_offsets;
struct snd_soc_dai_driver *codec_dais; struct snd_soc_dai_driver *codec_dais;
struct snd_soc_codec_driver *admaif_codec; struct snd_soc_codec_driver *admaif_codec;
const struct regmap_config *regmap_conf; const struct regmap_config *regmap_conf;
@@ -164,6 +165,9 @@ struct tegra_admaif_soc_data {
unsigned int reg, unsigned int reg,
struct tegra210_xbar_cif_conf *cif_conf); struct tegra210_xbar_cif_conf *cif_conf);
bool is_isomgr_client; bool is_isomgr_client;
unsigned int global_base;
unsigned int tx_base;
unsigned int rx_base;
}; };
struct tegra_admaif { struct tegra_admaif {

190
sound/soc/tegra-alt/tegra210_admaif_alt.c
View File

@@ -40,22 +40,22 @@
#define CH_REG(reg, id) (reg + (TEGRA_ADMAIF_CHANNEL_REG_STRIDE * (id-1))) #define CH_REG(reg, id) (reg + (TEGRA_ADMAIF_CHANNEL_REG_STRIDE * (id-1)))
#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, enable) \ #define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base) \
{ CH_REG(TEGRA_ADMAIF_XBAR_RX_INT_MASK, id), 0x00000001}, \ { CH_REG(TEGRA_ADMAIF_XBAR_RX_INT_MASK, id), 0x00000001}, \
{ CH_REG(TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL, id), 0x00007700}, \ { CH_REG(TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL, id), 0x00007700}, \
{ CH_REG(TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL, id), rx_ctrl}, \ { CH_REG(TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL, id), rx_ctrl}, \
{ CH_REG((enable + TEGRA_ADMAIF_XBAR_TX_INT_MASK), id), 0x00000001}, \ { CH_REG((tx_base + TEGRA_ADMAIF_XBAR_TX_INT_MASK), id), 0x00000001}, \
{ CH_REG((enable + TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL), id), 0x00007700}, \ { CH_REG((tx_base + TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL), id), 0x00007700}, \
{ CH_REG((enable + TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL), id), tx_ctrl} { CH_REG((tx_base + TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL), id), tx_ctrl}
#define ADMAIF_REG_DEFAULTS(id, chip) \ #define ADMAIF_REG_DEFAULTS(id, chip) \
REG_DEFAULTS(id, \ REG_DEFAULTS(id, \
chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \ chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \ chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_XBAR_TX_ENABLE) chip ## _ADMAIF_XBAR_TX_BASE)
static const struct reg_default tegra186_admaif_reg_defaults[] = { static const struct reg_default tegra186_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0+TEGRA186_ADMAIF_GLOBAL_ENABLE), 0x00000003}, {(TEGRA_ADMAIF_GLOBAL_CG_0+TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA186), ADMAIF_REG_DEFAULTS(1, TEGRA186),
ADMAIF_REG_DEFAULTS(2, TEGRA186), ADMAIF_REG_DEFAULTS(2, TEGRA186),
ADMAIF_REG_DEFAULTS(3, TEGRA186), ADMAIF_REG_DEFAULTS(3, TEGRA186),
@@ -79,7 +79,7 @@ static const struct reg_default tegra186_admaif_reg_defaults[] = {
}; };
static const struct reg_default tegra210_admaif_reg_defaults[] = { static const struct reg_default tegra210_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0+TEGRA210_ADMAIF_GLOBAL_ENABLE), 0x00000003}, {(TEGRA_ADMAIF_GLOBAL_CG_0+TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA210), ADMAIF_REG_DEFAULTS(1, TEGRA210),
ADMAIF_REG_DEFAULTS(2, TEGRA210), ADMAIF_REG_DEFAULTS(2, TEGRA210),
ADMAIF_REG_DEFAULTS(3, TEGRA210), ADMAIF_REG_DEFAULTS(3, TEGRA210),
@@ -95,69 +95,113 @@ static const struct reg_default tegra210_admaif_reg_defaults[] = {
static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg) static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
{ {
struct tegra_admaif *admaif = dev_get_drvdata(dev); struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int offset_tx_enable = admaif->soc_data->reg_offsets.tx_enable; unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
reg = reg % TEGRA_ADMAIF_CHANNEL_REG_STRIDE; unsigned int rx_base = admaif->soc_data->rx_base;
unsigned int tx_base = admaif->soc_data->tx_base;
if ((reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) || unsigned int global_base = admaif->soc_data->global_base;
(reg == TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL) || unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET) || unsigned int rx_max = rx_base + (num_ch * ch_stride);
(reg == TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL) || unsigned int tx_max = tx_base + (num_ch * ch_stride);
(reg == offset_tx_enable) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_STATUS)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_SOFT_RESET)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL)) ||
(reg == admaif->soc_data->reg_offsets.global_enable))
return true;
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_XBAR_TX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if (reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE))
return true;
}
return false; return false;
} }
static bool tegra_admaif_rd_reg(struct device *dev, unsigned int reg) static bool tegra_admaif_rd_reg(struct device *dev, unsigned int reg)
{ {
struct tegra_admaif *admaif = dev_get_drvdata(dev); struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int offset_tx_enable = admaif->soc_data->reg_offsets.tx_enable; unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
reg = reg % TEGRA_ADMAIF_CHANNEL_REG_STRIDE; unsigned int rx_base = admaif->soc_data->rx_base;
unsigned int tx_base = admaif->soc_data->tx_base;
if ((reg == TEGRA_ADMAIF_XBAR_RX_STATUS) || unsigned int global_base = admaif->soc_data->global_base;
(reg == TEGRA_ADMAIF_XBAR_RX_INT_STATUS) || unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
(reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) || unsigned int rx_max = rx_base + (num_ch * ch_stride);
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET) || unsigned int tx_max = tx_base + (num_ch * ch_stride);
(reg == TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL) ||
(reg == offset_tx_enable) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_STATUS)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_INT_STATUS)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_SOFT_RESET)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL)) ||
(reg == admaif->soc_data->reg_offsets.global_enable))
return true;
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_RX_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_RX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_TX_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_TX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_XBAR_TX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE)) ||
(reg == (global_base + TEGRA_ADMAIF_GLOBAL_CG_0)) ||
(reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
return true;
}
return false; return false;
} }
static bool tegra_admaif_volatile_reg(struct device *dev, unsigned int reg) static bool tegra_admaif_volatile_reg(struct device *dev, unsigned int reg)
{ {
struct tegra_admaif *admaif = dev_get_drvdata(dev); struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int offset_tx_enable = admaif->soc_data->reg_offsets.tx_enable; unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
if (reg > 0 && (reg < (offset_tx_enable + (admaif->soc_data->num_ch * unsigned int rx_base = admaif->soc_data->rx_base;
TEGRA_ADMAIF_CHANNEL_REG_STRIDE)))) unsigned int tx_base = admaif->soc_data->tx_base;
reg = reg % TEGRA_ADMAIF_CHANNEL_REG_STRIDE; unsigned int global_base = admaif->soc_data->global_base;
unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
if ((reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) || unsigned int rx_max = rx_base + (num_ch * ch_stride);
(reg == TEGRA_ADMAIF_XBAR_RX_STATUS) || unsigned int tx_max = tx_base + (num_ch * ch_stride);
(reg == TEGRA_ADMAIF_XBAR_RX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET) ||
(reg == offset_tx_enable) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_STATUS)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_INT_STATUS)) ||
(reg == (offset_tx_enable+TEGRA_ADMAIF_XBAR_TX_SOFT_RESET)))
return true;
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_RX_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_RX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_RX_SOFT_RESET))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_XBAR_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_XBAR_TX_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_TX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_XBAR_TX_SOFT_RESET))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
return true;
}
return false; return false;
} }
@@ -195,7 +239,7 @@ static int tegra_admaif_sw_reset(struct snd_soc_dai *dai,
int wait = timeout; int wait = timeout;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) { if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
sw_reset_reg = admaif->soc_data->reg_offsets.tx_enable + sw_reset_reg = admaif->soc_data->tx_base +
TEGRA_ADMAIF_XBAR_TX_SOFT_RESET + TEGRA_ADMAIF_XBAR_TX_SOFT_RESET +
(dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
} else { } else {
@@ -222,7 +266,7 @@ static int tegra_admaif_get_status(struct snd_soc_dai *dai,
unsigned int status_reg, val; unsigned int status_reg, val;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) { if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
status_reg = admaif->soc_data->reg_offsets.tx_enable + status_reg = admaif->soc_data->tx_base +
TEGRA_ADMAIF_XBAR_TX_STATUS + TEGRA_ADMAIF_XBAR_TX_STATUS +
(dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
} else { } else {
@@ -386,7 +430,7 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream,
} }
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
reg = admaif->soc_data->reg_offsets.tx_enable + reg = admaif->soc_data->tx_base +
TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL + TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL +
(dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
/* For playback path, the mono input from client channel /* For playback path, the mono input from client channel
@@ -423,7 +467,8 @@ static void tegra_admaif_start_playback(struct snd_soc_dai *dai)
struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai); struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
unsigned int reg; unsigned int reg;
reg = admaif->soc_data->reg_offsets.tx_enable + reg = admaif->soc_data->tx_base +
TEGRA_ADMAIF_XBAR_TX_ENABLE +
(dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
regmap_update_bits(admaif->regmap, reg, regmap_update_bits(admaif->regmap, reg,
TEGRA_ADMAIF_XBAR_TX_ENABLE_MASK, TEGRA_ADMAIF_XBAR_TX_ENABLE_MASK,
@@ -437,7 +482,8 @@ static void tegra_admaif_stop_playback(struct snd_soc_dai *dai)
unsigned int reg; unsigned int reg;
int dcnt = 10, ret; int dcnt = 10, ret;
reg = admaif->soc_data->reg_offsets.tx_enable + reg = admaif->soc_data->tx_base +
TEGRA_ADMAIF_XBAR_TX_ENABLE +
(dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (dai->id * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
regmap_update_bits(admaif->regmap, reg, regmap_update_bits(admaif->regmap, reg,
TEGRA_ADMAIF_XBAR_TX_ENABLE_MASK, TEGRA_ADMAIF_XBAR_TX_ENABLE_MASK,
@@ -596,7 +642,7 @@ static void tegra_admaif_reg_dump(struct tegra_admaif *admaif)
{ {
int i, stride; int i, stride;
int ret; int ret;
int tx_offset = admaif->soc_data->reg_offsets.tx_enable; int tx_offset = admaif->soc_data->tx_base;
ret = pm_runtime_get_sync(admaif->dev->parent); ret = pm_runtime_get_sync(admaif->dev->parent);
if (ret < 0) { if (ret < 0) {
@@ -622,7 +668,7 @@ static void tegra_admaif_reg_dump(struct tegra_admaif *admaif)
TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL + stride)); TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL + stride));
pr_info("TX%d_Enable = %#x\n", i+1, pr_info("TX%d_Enable = %#x\n", i+1,
readl(admaif->base_addr + tx_offset + readl(admaif->base_addr + tx_offset +
stride)); TEGRA_ADMAIF_XBAR_TX_ENABLE + stride));
pr_info("TX%d_STATUS = %#x\n", i+1, pr_info("TX%d_STATUS = %#x\n", i+1,
readl(admaif->base_addr + tx_offset + readl(admaif->base_addr + tx_offset +
TEGRA_ADMAIF_XBAR_TX_STATUS + stride)); TEGRA_ADMAIF_XBAR_TX_STATUS + stride));
@@ -1082,10 +1128,9 @@ static struct tegra_admaif_soc_data soc_data_tegra210 = {
.codec_dais = tegra210_admaif_codec_dais, .codec_dais = tegra210_admaif_codec_dais,
.regmap_conf = &tegra210_admaif_regmap_config, .regmap_conf = &tegra210_admaif_regmap_config,
.set_audio_cif = tegra210_xbar_set_cif, .set_audio_cif = tegra210_xbar_set_cif,
.reg_offsets = { .global_base = TEGRA210_ADMAIF_GLOBAL_BASE,
.global_enable = 0x700, .tx_base = TEGRA210_ADMAIF_XBAR_TX_BASE,
.tx_enable = 0x300, .rx_base = TEGRA210_ADMAIF_XBAR_RX_BASE,
},
.is_isomgr_client = false, .is_isomgr_client = false,
}; };
@@ -1095,10 +1140,9 @@ static struct tegra_admaif_soc_data soc_data_tegra186 = {
.codec_dais = tegra186_admaif_codec_dais, .codec_dais = tegra186_admaif_codec_dais,
.regmap_conf = &tegra186_admaif_regmap_config, .regmap_conf = &tegra186_admaif_regmap_config,
.set_audio_cif = tegra210_xbar_set_cif, .set_audio_cif = tegra210_xbar_set_cif,
.reg_offsets = { .global_base = TEGRA186_ADMAIF_GLOBAL_BASE,
.global_enable = 0xd00, .tx_base = TEGRA186_ADMAIF_XBAR_TX_BASE,
.tx_enable = 0x500, .rx_base = TEGRA186_ADMAIF_XBAR_RX_BASE,
},
.is_isomgr_client = true, .is_isomgr_client = true,
}; };
@@ -1221,7 +1265,7 @@ static int tegra_admaif_probe(struct platform_device *pdev)
for (i = 0; i < admaif->soc_data->num_ch; i++) { for (i = 0; i < admaif->soc_data->num_ch; i++) {
admaif->playback_dma_data[i].addr = res->start + admaif->playback_dma_data[i].addr = res->start +
admaif->soc_data->reg_offsets.tx_enable + admaif->soc_data->tx_base +
TEGRA_ADMAIF_XBAR_TX_FIFO_WRITE + TEGRA_ADMAIF_XBAR_TX_FIFO_WRITE +
(i * TEGRA_ADMAIF_CHANNEL_REG_STRIDE); (i * TEGRA_ADMAIF_CHANNEL_REG_STRIDE);
@@ -1299,8 +1343,8 @@ static int tegra_admaif_probe(struct platform_device *pdev)
goto err_unregister_codec; goto err_unregister_codec;
} }
regmap_update_bits(admaif->regmap, regmap_update_bits(admaif->regmap, admaif->soc_data->global_base +
admaif->soc_data->reg_offsets.global_enable, 1, 1); TEGRA_ADMAIF_GLOBAL_ENABLE, 1, 1);
return 0; return 0;