diff --git a/drivers/platform/tegra/dce/dce-bootstrap.c b/drivers/platform/tegra/dce/dce-bootstrap.c
index 9cab8f2a..d81ad5d2 100644
--- a/drivers/platform/tegra/dce/dce-bootstrap.c
+++ b/drivers/platform/tegra/dce/dce-bootstrap.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+ * Copyright (c) 2019-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
  */
 #include <dce.h>
 #include <dce-util-common.h>
@@ -16,7 +16,7 @@
  */
 inline bool dce_fw_boot_complete(struct tegra_dce *d)
 {
-	return !!(dce_ss_get_state(d, DCE_BOOT_SEMA)
+	return !!(dce_ss_get_state(d, d->hsp_id, DCE_BOOT_SEMA)
 					& DCE_BOOT_COMPLETE);
 }
 
@@ -31,7 +31,7 @@ inline bool dce_fw_boot_complete(struct tegra_dce *d)
 inline void dce_request_fw_boot_complete(struct tegra_dce *d)
 {
 #define DCE_BOOT_INIT_BPOS 31U
-	dce_ss_set(d, DCE_BOOT_INIT_BPOS, DCE_BOOT_SEMA);
+	dce_ss_set(d, DCE_BOOT_INIT_BPOS, d->hsp_id, DCE_BOOT_SEMA);
 #undef DCE_BOOT_INIT_BPOS
 }
 
diff --git a/drivers/platform/tegra/dce/dce-debug.c b/drivers/platform/tegra/dce/dce-debug.c
index 54a8d8e6..d6253a13 100644
--- a/drivers/platform/tegra/dce/dce-debug.c
+++ b/drivers/platform/tegra/dce/dce-debug.c
@@ -504,7 +504,7 @@ static ssize_t dbg_dce_boot_status_fops_read(struct file *file,
 	unsigned long bitmap;
 	struct tegra_dce *d = file->private_data;
 	u32 boot_status = d->boot_status;
-	hsp_sema_t ss = dce_ss_get_state(d, DCE_BOOT_SEMA);
+	hsp_sema_t ss = dce_ss_get_state(d, d->hsp_id, DCE_BOOT_SEMA);
 
 	if (ss & DCE_BOOT_COMPLETE)
 		goto core_boot_done;
@@ -682,7 +682,7 @@ static int dump_hsp_regs_show(struct seq_file *s, void *unused)
 	 * Dump Boot Semaphore Value
 	 */
 	dce_info(d, "DCE_BOOT_SEMA : 0x%x",
-				dce_ss_get_state(d, DCE_BOOT_SEMA));
+				dce_ss_get_state(d, d->hsp_id, DCE_BOOT_SEMA));
 
 	/**
 	 * Dump Shared Mailboxes Values
diff --git a/drivers/platform/tegra/dce/dce-hsp-ss.c b/drivers/platform/tegra/dce/dce-hsp-ss.c
index 4baf98b3..2231356f 100644
--- a/drivers/platform/tegra/dce/dce-hsp-ss.c
+++ b/drivers/platform/tegra/dce/dce-hsp-ss.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2024, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <dce.h>
@@ -60,15 +60,14 @@ __weak u32 (*const ss_state_regs[DCE_MAX_HSP][DCE_MAX_NO_SS])(void) = {
  * dce_ss_get_state - Get the state of ss_#n in the DCE Cluster
  *
  * @d : Pointer to tegra_dce struct.
+ * @hsp_id : ID of hsp instance used
  * @id : Shared Semaphore Id.
  *
  * Return : u32
  */
-u32 dce_ss_get_state(struct tegra_dce *d, u8 id)
+u32 dce_ss_get_state(struct tegra_dce *d, u8 hsp_id, u8 id)
 {
-	u32 hsp = d->hsp_id;
-
-	return dce_readl(d, ss_state_regs[hsp][id]());
+	return dce_readl(d, ss_state_regs[hsp_id][id]());
 }
 
 /**
@@ -76,21 +75,21 @@ u32 dce_ss_get_state(struct tegra_dce *d, u8 id)
  *
  * @d : Pointer to tegra_dce struct.
  * @bpos : bit to be set.
+ * @hsp_id : ID of hsp instance used
  * @id : Shared Semaphore Id.
  *
  * Return : Void
  */
-void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id)
+void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id)
 {
 	unsigned long val = 0U;
-	u32 hsp = d->hsp_id;
 
-	if (hsp >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
-		dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp, id);
+	if (hsp_id >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
+		dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp_id, id);
 		return;
 	}
 
-	val = dce_ss_get_state(d, id);
+	val = dce_ss_get_state(d, d->hsp_id, id);
 
 	/**
 	 * Debug info. please remove
@@ -107,12 +106,12 @@ void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id)
 	 */
 	dce_info(d, "Value after bitmap operation : %lx", val);
 
-	dce_writel(d, ss_set_regs[hsp][id](), (u32)val);
+	dce_writel(d, ss_set_regs[hsp_id][id](), (u32)val);
 
 	/**
 	 * Debug info. please remove
 	 */
-	val = dce_ss_get_state(d, id);
+	val = dce_ss_get_state(d, d->hsp_id, id);
 	dce_info(d, "Current Value in SS#%d : %lx", id, val);
 }
 
@@ -121,23 +120,23 @@ void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id)
  *
  * @d : Pointer to tegra_dce struct.
  * @bpos : bit to be cleared.
+ * @hsp_id : ID of hsp instance used
  * @id : Shared Semaphore Id.
  *
  * Return : Void
  */
-void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 id)
+void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id)
 {
 	unsigned long val;
-	u32 hsp = d->hsp_id;
 
-	if (hsp >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
-		dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp, id);
+	if (hsp_id >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
+		dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp_id, id);
 		return;
 	}
 
-	val = dce_ss_get_state(d, id);
+	val = dce_ss_get_state(d, d->hsp_id, id);
 
 	dce_bitmap_set(&val, bpos, 1);
 
-	dce_writel(d, ss_clear_regs[hsp][id](), val);
+	dce_writel(d, ss_clear_regs[hsp_id][id](), val);
 }
diff --git a/drivers/platform/tegra/dce/dce-ipc-signal.c b/drivers/platform/tegra/dce/dce-ipc-signal.c
index acbaf42e..5b1ee89b 100644
--- a/drivers/platform/tegra/dce/dce-ipc-signal.c
+++ b/drivers/platform/tegra/dce/dce-ipc-signal.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2024, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <dce.h>
@@ -19,7 +19,7 @@ static void dce_ipc_mbox_notify(struct tegra_dce *d,
 	}
 
 	if (s->sema_num < DCE_NUM_SEMA_REGS)
-		dce_ss_set(d, s->sema_bit, s->sema_num);
+		dce_ss_set(d, s->sema_bit, d->hsp_id, s->sema_num);
 
 	dce_mailbox_set_full_interrupt(d, s->form.mbox.mb_type);
 }
@@ -41,12 +41,12 @@ static void dce_ipc_mbox_handle_signal(struct tegra_dce *d, void *data)
 
 	for (cur_s = s; cur_s != NULL; cur_s = cur_s->next) {
 		if (cur_s->sema_num < DCE_NUM_SEMA_REGS) {
-			sema_val = dce_ss_get_state(d, cur_s->sema_num);
+			sema_val = dce_ss_get_state(d, d->hsp_id, cur_s->sema_num);
 			if ((sema_val & BIT(cur_s->sema_bit)) == 0)
 				continue;
 		}
 
-		dce_ss_clear(d, cur_s->sema_num, BIT(cur_s->sema_bit));
+		dce_ss_clear(d, cur_s->sema_num, d->hsp_id, BIT(cur_s->sema_bit));
 
 		ch = cur_s->signal->ch;
 
diff --git a/drivers/platform/tegra/dce/include/dce-hsp.h b/drivers/platform/tegra/dce/include/dce-hsp.h
index 634c4413..a44fac1b 100644
--- a/drivers/platform/tegra/dce/include/dce-hsp.h
+++ b/drivers/platform/tegra/dce/include/dce-hsp.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2024, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #ifndef DCE_HSP_H
@@ -14,9 +14,9 @@ struct tegra_dce;
  * DCE HSP Shared Semaphore Utility functions. Description
  * can be found with function definitions.
  */
-u32 dce_ss_get_state(struct tegra_dce *d, u8 id);
-void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id);
-void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 id);
+u32 dce_ss_get_state(struct tegra_dce *d, u8 hsp_id, u8 id);
+void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id);
+void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 hsp_id, u8 id);
 
 /**
  * DCE HSP Shared Mailbox Utility functions.  Description