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drivers: pva: Update channel and descriptor limit

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Update code to account for t26x channel and descriptor limits.

Also, the reserved descriptors for all generations of PVA HW are
at indices 60-63. Update KMD checks to ensure the reserved descriptors
are never patched, and are not linked to either during SW sequencing
or HW sequencing.

Jira PVAAS-13055

Change-Id: I276490d51d65648a406fabed06c47e45d9e6978a
Signed-off-by: abhinayaa <abhinayaa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2908053
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2999158
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
Tested-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
abhinayaa
2023-04-18 00:25:09 +00:00
committed by mobile promotions
parent 5d5f42c1b1
commit 97f5252632
6 changed files with 94 additions and 29 deletions
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27
include/uapi/linux/nvpva_ioctl.h
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@@ -516,12 +516,31 @@ union nvpva_set_vpu_print_buffer_size_args {
struct nvpva_set_vpu_print_buffer_size_in_arg in;
};
/* There are 64 DMA descriptors in T19x and T23x. But R5 FW reserves
/**
* There are 64 DMA descriptors in T19x. But R5 FW reserves
* 4 DMA descriptors for internal use.
*/
#define NVPVA_TASK_MAX_DMA_DESCRIPTORS (60U)
#define NVPVA_TASK_MAX_DMA_DESCRIPTORS_T19X (60U)
/**
* There are 64 DMA descriptors in T23x. But R5 FW reserves
* 4 DMA descriptors for internal use.
*/
#define NVPVA_TASK_MAX_DMA_DESCRIPTORS_T23X (60U)
/**
* Number of DMA descriptors reserved for R5 FW's
* internal use
*/
#define NVPVA_NUM_RESERVED_DESCRIPTORS (4U)
/**
* Index of the first reserved DMA descriptor
*/
#define NVPVA_RESERVED_DESCRIPTORS_START_IDX (60U)
/*TODO: Remove NVPVA_TASK_MAX_DMA_CHANNELS */
/*There are 14 DMA channels in T19x and 16 DMA channels in T23X.
/**
* There are 14 DMA channels in T19x and 16 DMA channels in T23X.
* R5 FW reserves one DMA channel for internal use.
*/
#define NVPVA_TASK_MAX_DMA_CHANNELS 16U
@@ -597,7 +616,7 @@ union nvpva_set_vpu_print_buffer_size_args {
NVPVA_MAX_FENCE_TYPES * sizeof(struct nvpva_fence_action) + \
NVPVA_TASK_MAX_INPUT_STATUS * sizeof(struct nvpva_mem) + \
NVPVA_TASK_MAX_OUTPUT_STATUS * sizeof(struct nvpva_mem) + \
NVPVA_TASK_MAX_DMA_DESCRIPTORS * \
NVPVA_TASK_MAX_DMA_DESCRIPTORS_T23X * \
sizeof(struct nvpva_dma_descriptor) + \
NVPVA_TASK_MAX_DMA_CHANNELS * sizeof(struct nvpva_dma_channel) + \
sizeof(struct nvpva_hwseq_config) + \