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rtcpu: set op point via sysfs
Create and register set and get operating point sysfs functions. The operating point notification will contain the requested operating point. The nvcap resource manager will extract the operating point from the notfication and send it to rce via the hsp command interface. In turn, rce will apply the operating point by adjusting the functional clock frequencies for the following camera ip: - rce hardware - vi hardware - isp hardware - nvcsi Jira CAMERASW-26378 Signed-off-by: Robert Kelly <rkelly@nvidia.com> Change-Id: Ia814b2716d3738efb3cbc37307a267140b555f42 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3179593 (cherry picked from commit d259727a57ecf4b9463030b3418715891b3b1209) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3189078 Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Frank Chen <frankc@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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/**
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@@ -464,6 +464,48 @@
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*/
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#define CAMRTC_HSP_PROTOCOL MK_U32(0x47)
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/**
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* @brief SET_OP_POINT message
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*
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* The CAMRTC_HSP_SET_OP_POINT message is used to apply the
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* specified operating point to Camera IP. Two operating points
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* are supported:
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*
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* Operating Point 0: Camera IP runs at maximum clock speeds.
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* Operating Point 6: Camera IP runs at reduced clock speeds.
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*
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* Camera IP:
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* - RCE HW
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* - VI HW
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* - ISP HW
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* - NVCSI
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*
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* @pre @ref CAMRTC_HSP_HELLO exchange has been completed.
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*
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* @par Request
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* @rststar
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* +-------+---------------------------------------------------+
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* | Bits | Description |
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* +=======+===================================================+
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* | 30:24 | CAMRTC_HSP_SET_OP_POINT |
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* +-------+---------------------------------------------------+
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* | 23:0 | Operating Point {0, 6} |
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* +-------+---------------------------------------------------+
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* @endrst
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*
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* @par Response
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* @rststar
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* +-------+---------------------------------------------------+
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* | Bits | Description |
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* +=======+===================================================+
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* | 30:24 | CAMRTC_HSP_SET_OP_POINT |
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* +-------+---------------------------------------------------+
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* | 23:0 | 0x000000 |
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* +-------+---------------------------------------------------+
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* @endrst
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*/
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#define CAMRTC_HSP_SET_OP_POINT MK_U32(0x48)
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/** Reserved, not to be used. */
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#define CAMRTC_HSP_RESERVED_5E MK_U32(0x5E) /* bug 200395605 */
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