diff --git a/drivers/platform/tegra/nvadsp/amc.h b/drivers/platform/tegra/nvadsp/amc.h index eeac6e96..832eaafa 100644 --- a/drivers/platform/tegra/nvadsp/amc.h +++ b/drivers/platform/tegra/nvadsp/amc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /** - * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2024, NVIDIA CORPORATION. All rights reserved. */ #ifndef __TEGRA_NVADSP_AMC_H @@ -20,6 +20,26 @@ #define AMC_INT_INVALID_REG_ACCESS (1 << 1) #define AMC_ERROR_ADDR 0x14 +#define AMC_EVP_RESET_VEC_0 0x700 +#define AMC_EVP_UNDEF_VEC_0 0x704 +#define AMC_EVP_SWI_VEC_0 0x708 +#define AMC_EVP_PREFETCH_ABORT_VEC_0 0x70c +#define AMC_EVP_DATA_ABORT_VEC_0 0x710 +#define AMC_EVP_RSVD_VEC_0 0x714 +#define AMC_EVP_IRQ_VEC_0 0x718 +#define AMC_EVP_FIQ_VEC_0 0x71c +#define AMC_EVP_RESET_ADDR_0 0x720 +#define AMC_EVP_UNDEF_ADDR_0 0x724 +#define AMC_EVP_SWI_ADDR_0 0x728 +#define AMC_EVP_PREFETCH_ABORT_ADDR_0 0x72c +#define AMC_EVP_DATA_ABORT_ADDR_0 0x730 +#define AMC_EVP_RSVD_ADDR_0 0x734 +#define AMC_EVP_IRQ_ADDR_0 0x738 +#define AMC_EVP_FIQ_ADDR_0 0x73c + +#define AMC_EVP_SIZE (AMC_EVP_FIQ_ADDR_0 - AMC_EVP_RESET_VEC_0 + 4) +#define AMC_EVP_WSIZE (AMC_EVP_SIZE >> 2) + #define AMC_ERROR_ADDR_IGNORE SZ_4K #define AMC_REGS 0x1000 diff --git a/drivers/platform/tegra/nvadsp/dev-t18x.c b/drivers/platform/tegra/nvadsp/dev-t18x.c index 7334146d..f1510184 100644 --- a/drivers/platform/tegra/nvadsp/dev-t18x.c +++ b/drivers/platform/tegra/nvadsp/dev-t18x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /** - * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2024, NVIDIA CORPORATION. All rights reserved. */ #include @@ -21,6 +21,22 @@ #include "dev.h" #include "dev-t18x.h" +#include "amisc.h" +#include "amc.h" +#include "adsp_shared_struct.h" +#include "hwmailbox.h" +#include "log_state.h" + +/* macros used to find the current mode of ADSP */ +#define MODE_MASK 0x1f +#define MODE_USR 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_MON 0x16 +#define MODE_ABT 0x17 +#define MODE_UND 0x1b +#define MODE_SYS 0x1f #ifdef CONFIG_PM static int nvadsp_t18x_clocks_disable(struct platform_device *pdev) @@ -135,7 +151,7 @@ static int __nvadsp_t18x_runtime_idle(struct device *dev) return 0; } -int nvadsp_pm_t18x_init(struct platform_device *pdev) +static int nvadsp_pm_t18x_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; @@ -150,6 +166,323 @@ int nvadsp_pm_t18x_init(struct platform_device *pdev) } #endif /* CONFIG_PM */ +static void print_arm_mode_regs(struct nvadsp_drv_data *drv_data) +{ + struct nvadsp_exception_context *excep_context; + struct arm_fault_frame_shared *shared_frame; + struct arm_mode_regs_shared *shared_regs; + struct nvadsp_shared_mem *shared_mem; + struct device *dev = &drv_data->pdev->dev; + + shared_mem = drv_data->shared_adsp_os_data; + excep_context = &shared_mem->exception_context; + shared_frame = &excep_context->frame; + shared_regs = &excep_context->regs; + + dev_err(dev, "dumping arm mode register data...\n"); + dev_err(dev, "%c fiq r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_FIQ) ? '*' : ' ', + shared_regs->fiq_r13, shared_regs->fiq_r14); + dev_err(dev, "%c irq r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_IRQ) ? '*' : ' ', + shared_regs->irq_r13, shared_regs->irq_r14); + dev_err(dev, "%c svc r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_SVC) ? '*' : ' ', + shared_regs->svc_r13, shared_regs->svc_r14); + dev_err(dev, "%c und r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_UND) ? '*' : ' ', + shared_regs->und_r13, shared_regs->und_r14); + dev_err(dev, "%c sys r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_SYS) ? '*' : ' ', + shared_regs->sys_r13, shared_regs->sys_r14); + dev_err(dev, "%c abt r13 0x%08x r14 0x%08x\n", + ((shared_frame->spsr & MODE_MASK) == MODE_ABT) ? '*' : ' ', + shared_regs->abt_r13, shared_regs->abt_r14); +} + +static void print_arm_fault_frame(struct nvadsp_drv_data *drv_data) +{ + struct nvadsp_exception_context *excep_context; + struct arm_fault_frame_shared *shared_frame; + struct nvadsp_shared_mem *shared_mem; + struct device *dev = &drv_data->pdev->dev; + + shared_mem = drv_data->shared_adsp_os_data; + excep_context = &shared_mem->exception_context; + shared_frame = &excep_context->frame; + + dev_err(dev, "dumping fault frame...\n"); + dev_err(dev, "r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n", + shared_frame->r[0], shared_frame->r[1], shared_frame->r[2], + shared_frame->r[3]); + dev_err(dev, "r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", + shared_frame->r[4], shared_frame->r[5], shared_frame->r[6], + shared_frame->r[7]); + dev_err(dev, "r8 0x%08x r9 0x%08x r10 0x%08x r11 0x%08x\n", + shared_frame->r[8], shared_frame->r[9], shared_frame->r[10], + shared_frame->r[11]); + dev_err(dev, "r12 0x%08x usp 0x%08x ulr 0x%08x pc 0x%08x\n", + shared_frame->r[12], shared_frame->usp, shared_frame->ulr, + shared_frame->pc); + dev_err(dev, "spsr 0x%08x\n", shared_frame->spsr); + +} + +static void dump_thread_name(struct platform_device *pdev, u32 val) +{ + dev_info(&pdev->dev, "%s: adsp current thread: %c%c%c%c\n", + __func__, + (val >> 24) & 0xFF, (val >> 16) & 0xFF, + (val >> 8) & 0xFF, (val >> 0) & 0xFF); +} + +static void dump_irq_num(struct platform_device *pdev, u32 val) +{ + dev_info(&pdev->dev, "%s: adsp current/last irq : %d\n", + __func__, val); +} + +static void get_adsp_state(struct nvadsp_drv_data *drv_data) +{ + struct device *dev; + uint32_t val; + const char *msg; + + if (!drv_data->pdev) { + pr_err("ADSP Driver is not initialized\n"); + return; + } + + dev = &drv_data->pdev->dev; + + if (drv_data->chip_data->adsp_state_hwmbox == 0) { + dev_info(dev, "%s: No state hwmbox available\n", __func__); + return; + } + + val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_state_hwmbox); + dev_info(dev, "%s: adsp state hwmbox value: 0x%X\n", __func__, val); + + switch (val) { + + case ADSP_LOADER_MAIN_ENTRY: + msg = "loader_main: entry to loader_main"; + break; + case ADSP_LOADER_MAIN_CACHE_DISABLE_COMPLETE: + msg = "loader_main: Cache has been disabled"; + break; + case ADSP_LOADER_MAIN_CONFIGURE_MMU_COMPLETE: + msg = "loader_main: MMU configuration is complete"; + break; + case ADSP_LOADER_MAIN_CACHE_ENABLE_COMPLETE: + msg = "loader_main: Cache has been enabled"; + break; + case ADSP_LOADER_MAIN_FPU_ENABLE_COMPLETE: + msg = "loader_main: FPU has been enabled"; + break; + case ADSP_LOADER_MAIN_DECOMPRESSION_COMPLETE: + msg = "loader_main: ADSP FW decompression is complete"; + break; + case ADSP_LOADER_MAIN_EXIT: + msg = "loader_main: exiting loader_main function"; + break; + + case ADSP_START_ENTRY_AT_RESET: + msg = "start: ADSP is at reset"; + break; + case ADSP_START_CPU_EARLY_INIT: + msg = "start: ADSP to do cpu_early_init"; + break; + case ADSP_START_FIRST_BOOT: + msg = "start: ADSP is booting for first time," + "initializing DATA and clearing BSS"; + break; + case ADSP_START_LK_MAIN_ENTRY: + msg = "start: ADSP about to enter lk_main"; + break; + + case ADSP_LK_MAIN_ENTRY: + msg = "lk_main: entry to lk_main"; + break; + case ADSP_LK_MAIN_EARLY_THREAD_INIT_COMPLETE: + msg = "lk_main: early_thread_init has been completed"; + break; + case ADSP_LK_MAIN_EARLY_ARCH_INIT_COMPLETE: + msg = "lk_main: early_arch_init has been completed"; + break; + case ADSP_LK_MAIN_EARLY_PLATFORM_INIT_COMPLETE: + msg = "lk_main: early_platform_init has been completed"; + break; + case ADSP_LK_MAIN_EARLY_TARGET_INIT_COMPLETE: + msg = "lk_main: early_target_init has been completed"; + break; + case ADSP_LK_MAIN_CONSTRUCTOR_INIT_COMPLETE: + msg = "lk_main: constructors has been called"; + break; + case ADSP_LK_MAIN_HEAP_INIT_COMPLETE: + msg = "lk_main: heap has been initialized"; + break; + case ADSP_LK_MAIN_KERNEL_INIT_COMPLETE: + msg = "lk_main: ADSP kernel has been initialized"; + break; + case ADSP_LK_MAIN_CPU_RESUME_ENTRY: + msg = "lk_main: ADSP is about to resume from suspend"; + break; + + case ADSP_BOOTSTRAP2_ARCH_INIT_COMPLETE: + msg = "bootstrap2: ADSP arch_init is complete"; + break; + case ADSP_BOOTSTRAP2_PLATFORM_INIT_COMPLETE: + msg = "bootstrap2: platform has been initialized"; + break; + case ADSP_BOOTSTRAP2_TARGET_INIT_COMPLETE: + msg = "bootstrap2: target has been initialized"; + break; + case ADSP_BOOTSTRAP2_APP_MODULE_INIT_COMPLETE: + msg = "bootstrap2: APP modules initialized"; + break; + case ADSP_BOOTSTRAP2_APP_INIT_COMPLETE: + msg = "bootstrap2: APP init is complete"; + break; + case ADSP_BOOTSTRAP2_STATIC_APP_INIT_COMPLETE: + msg = "bootstrap2: Static apps has been initialized"; + break; + case ADSP_BOOTSTRAP2_OS_LOAD_COMPLETE: + msg = "bootstrap2: ADSP OS successfully loaded"; + break; + case ADSP_SUSPEND_BEGINS: + msg = "suspend: begins"; + break; + case ADSP_SUSPEND_MBX_SEND_COMPLETE: + msg = "suspend: mbox send complete"; + break; + case ADSP_SUSPEND_DISABLED_TIMERS: + msg = "suspend: timers disabled"; + break; + case ADSP_SUSPEND_DISABLED_INTS: + msg = "suspend: interrupts disabled"; + break; + case ADSP_SUSPEND_ARAM_SAVED: + msg = "suspend: aram saved"; + break; + case ADSP_SUSPEND_AMC_SAVED: + msg = "suspend: amc saved"; + break; + case ADSP_SUSPEND_AMISC_SAVED: + msg = "suspend: amisc saved"; + break; + case ADSP_SUSPEND_L1_CACHE_DISABLED: + msg = "suspend: l1 cache disabled"; + break; + case ADSP_SUSPEND_L2_CACHE_DISABLED: + msg = "suspend: l2 cache disabled"; + break; + case ADSP_RESUME_ADSP: + msg = "resume: beings"; + break; + case ADSP_RESUME_AMISC_RESTORED: + msg = "resume: amisc restored"; + break; + case ADSP_RESUME_AMC_RESTORED: + msg = "resume: amc restored"; + break; + case ADSP_RESUME_ARAM_RESTORED: + msg = "resume: aram restored"; + break; + case ADSP_RESUME_COMPLETE: + msg = "resume: complete"; + break; + case ADSP_WFI_ENTER: + msg = "WFI: Entering WFI"; + break; + case ADSP_WFI_EXIT: + msg = "WFI: Exiting WFI, Failed to Enter"; + break; + case ADSP_DFS_MBOX_RECV: + msg = "DFS: mbox received"; + break; + case ADSP_DFS_MBOX_SENT: + msg = "DFS: mbox sent"; + break; + default: + msg = "Unrecognized ADSP state!!"; + break; + } + + dev_info(dev, "%s: %s\n", __func__, msg); + + val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_thread_hwmbox); + dump_thread_name(drv_data->pdev, val); + + val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_irq_hwmbox); + dump_irq_num(drv_data->pdev, val); +} + +static void __dump_core_state_t18x(struct nvadsp_drv_data *drv_data) +{ + print_arm_fault_frame(drv_data); + print_arm_mode_regs(drv_data); + get_adsp_state(drv_data); +} + +static int __set_boot_vec_t18x(struct nvadsp_drv_data *drv_data) +{ + struct platform_device *pdev = drv_data->pdev; + struct device *dev = &pdev->dev; + void *to = drv_data->state.evp_ptr; + const void *from = drv_data->state.evp; + int i, sz = AMC_EVP_SIZE; + + dev_dbg(dev, "Copying EVP...\n"); + for (i = 0; i < sz; i += 4) { + u32 val = *(u32 *)(from + i); + writel(val, (void __iomem *)(to + i)); + } + + return 0; +} + +static int __set_boot_freqs_t18x(struct nvadsp_drv_data *drv_data) +{ + struct nvadsp_shared_mem *shared_mem = drv_data->shared_adsp_os_data; + struct nvadsp_os_args *os_args = &shared_mem->os_args; + struct platform_device *pdev = drv_data->pdev; + struct device *dev = &pdev->dev; + unsigned long max_adsp_freq; + unsigned long adsp_freq; + int ret = 0; + + if (!drv_data->adsp_clk) + return -EINVAL; + + adsp_freq = drv_data->adsp_freq_hz; /* in Hz*/ + + /* round rate shall be used with adsp parent clk i.e. aclk */ + max_adsp_freq = clk_round_rate(drv_data->aclk_clk, ULONG_MAX); + + /* Set max adsp boot freq */ + if (!adsp_freq) + adsp_freq = max_adsp_freq; + + /* set rate shall be used with adsp parent clk i.e. aclk */ + ret = clk_set_rate(drv_data->aclk_clk, adsp_freq); + if (ret) { + dev_err(dev, "setting adsp_freq:%luHz failed.\n", adsp_freq); + dev_err(dev, "max_adsp_freq:%luHz\n", max_adsp_freq); + goto end; + } + + drv_data->adsp_freq = adsp_freq / 1000; /* adsp_freq in KHz*/ + drv_data->adsp_freq_hz = adsp_freq; + + /* adspos uses os_args->adsp_freq_hz for EDF */ + os_args->adsp_freq_hz = drv_data->adsp_freq_hz; +end: + dev_dbg(dev, "adsp cpu freq %luKHz\n", + clk_get_rate(drv_data->adsp_clk) / 1000); + return ret; +} + static int __assert_t18x_adsp(struct nvadsp_drv_data *d) { struct platform_device *pdev = d->pdev; @@ -262,7 +595,35 @@ static int __virt_deassert_t18x_adsp(struct nvadsp_drv_data *d) } #endif -int nvadsp_reset_t18x_init(struct platform_device *pdev) +static bool __check_wfi_status_t18x(struct nvadsp_drv_data *d) +{ + int cnt = 0; + bool wfi_status = true; + u32 adsp_status; + + /* + * Check L2_IDLE and L2_CLKSTOPPED in ADSP_STATUS + * NOTE: Standby mode in ADSP L2CC Power Control + * register should be enabled for this + */ + do { + adsp_status = amisc_readl(d, AMISC_ADSP_STATUS); + if ((adsp_status & AMISC_ADSP_L2_IDLE) && + (adsp_status & AMISC_ADSP_L2_CLKSTOPPED)) + break; + cnt++; + mdelay(1); + } while (cnt < 5); + + if (cnt >= 5) { + pr_err("ADSP L2C clock not halted: 0x%x\n", adsp_status); + wfi_status = false; + } + + return wfi_status; +} + +static int nvadsp_dev_t18x_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; @@ -278,6 +639,11 @@ int nvadsp_reset_t18x_init(struct platform_device *pdev) } #endif + d->set_boot_vec = __set_boot_vec_t18x; + d->set_boot_freqs = __set_boot_freqs_t18x; + d->check_wfi_status = __check_wfi_status_t18x; + d->dump_core_state = __dump_core_state_t18x; + d->assert_adsp = __assert_t18x_adsp; d->deassert_adsp = __deassert_t18x_adsp; d->adspall_rst = devm_reset_control_get(dev, "adspall"); @@ -294,3 +660,64 @@ int nvadsp_reset_t18x_init(struct platform_device *pdev) end: return ret; } + +struct nvadsp_chipdata tegrat18x_adsp_chipdata = { + .hwmb = { + .reg_idx = AHSP, + .hwmbox0_reg = 0x00000, + .hwmbox1_reg = 0X08000, + .hwmbox2_reg = 0X10000, + .hwmbox3_reg = 0X18000, + .hwmbox4_reg = 0X20000, + .hwmbox5_reg = 0X28000, + .hwmbox6_reg = 0X30000, + .hwmbox7_reg = 0X38000, + .empty_int_ie = 0x8, + }, + .adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */ + .adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */ + .adsp_os_config_hwmbox = 0X28000, /* HWMBOX5 */ + .adsp_state_hwmbox = 0x30000, /* HWMBOX6 */ + .adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */ + .acast_init = nvadsp_acast_t18x_init, + .dev_init = nvadsp_dev_t18x_init, + .os_init = nvadsp_os_t18x_init, +#ifdef CONFIG_PM + .pm_init = nvadsp_pm_t18x_init, +#endif + + .amc_err_war = true, + .num_irqs = NVADSP_VIRQ_MAX, +}; + +struct nvadsp_chipdata tegra239_adsp_chipdata = { + .hwmb = { + .reg_idx = AHSP, + .hwmbox0_reg = 0x00000, + .hwmbox1_reg = 0X08000, + .hwmbox2_reg = 0X10000, + .hwmbox3_reg = 0X18000, + .hwmbox4_reg = 0X20000, + .hwmbox5_reg = 0X28000, + .hwmbox6_reg = 0X30000, + .hwmbox7_reg = 0X38000, + .empty_int_ie = 0x8, + }, + .adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */ + .adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */ + .adsp_os_config_hwmbox = 0X28000, /* HWMBOX5 */ + .adsp_state_hwmbox = 0x30000, /* HWMBOX6 */ + .adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */ + .acast_init = nvadsp_acast_t18x_init, + .dev_init = nvadsp_dev_t18x_init, + .os_init = nvadsp_os_t18x_init, +#ifdef CONFIG_PM + .pm_init = nvadsp_pm_t18x_init, +#endif + + .amc_err_war = false, + + /* Populate Chip ID Major Revision as well */ + .chipid_ext = 0x9, + .num_irqs = NVADSP_VIRQ_MAX, +}; diff --git a/drivers/platform/tegra/nvadsp/dev-t18x.h b/drivers/platform/tegra/nvadsp/dev-t18x.h index af589861..ab572a01 100644 --- a/drivers/platform/tegra/nvadsp/dev-t18x.h +++ b/drivers/platform/tegra/nvadsp/dev-t18x.h @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /** - * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2024, NVIDIA CORPORATION. All rights reserved. */ #ifndef __TEGRA_NVADSP_DEV_T18X_H #define __TEGRA_NVADSP_DEV_T18X_H int nvadsp_acast_t18x_init(struct platform_device *pdev); -int nvadsp_reset_t18x_init(struct platform_device *pdev); int nvadsp_os_t18x_init(struct platform_device *pdev); -int nvadsp_pm_t18x_init(struct platform_device *pdev); #endif /* __TEGRA_NVADSP_DEV_T18X_H */ diff --git a/drivers/platform/tegra/nvadsp/dev.c b/drivers/platform/tegra/nvadsp/dev.c index 6606dbb2..3e4d42ab 100644 --- a/drivers/platform/tegra/nvadsp/dev.c +++ b/drivers/platform/tegra/nvadsp/dev.c @@ -23,12 +23,9 @@ #include "dev.h" #include "hwmailbox.h" #include "os.h" -#include "amc.h" #include "ape_actmon.h" #include "aram_manager.h" -#include "dev-t18x.h" - #define MAX_DEV_STR_LEN (20) struct nvadsp_handle_node { @@ -543,7 +540,7 @@ static int __init nvadsp_probe(struct platform_device *pdev) if (ret) goto err; - ret = nvadsp_reset_init(pdev); + ret = nvadsp_dev_init(pdev); if (ret) { dev_err(dev, "Failed initialize resets\n"); goto err; @@ -628,68 +625,11 @@ static int nvadsp_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_OF -static struct nvadsp_chipdata tegrat18x_adsp_chipdata = { - .hwmb = { - .reg_idx = AHSP, - .hwmbox0_reg = 0x00000, - .hwmbox1_reg = 0X08000, - .hwmbox2_reg = 0X10000, - .hwmbox3_reg = 0X18000, - .hwmbox4_reg = 0X20000, - .hwmbox5_reg = 0X28000, - .hwmbox6_reg = 0X30000, - .hwmbox7_reg = 0X38000, - .empty_int_ie = 0x8, - }, - .adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */ - .adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */ - .adsp_os_config_hwmbox = 0X28000, /*HWMBOX5 */ - .adsp_state_hwmbox = 0x30000, /* HWMBOX6 */ - .adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */ - .acast_init = nvadsp_acast_t18x_init, - .reset_init = nvadsp_reset_t18x_init, - .os_init = nvadsp_os_t18x_init, -#ifdef CONFIG_PM - .pm_init = nvadsp_pm_t18x_init, -#endif - - .amc_err_war = true, - .num_irqs = NVADSP_VIRQ_MAX, -}; - -static struct nvadsp_chipdata tegra239_adsp_chipdata = { - .hwmb = { - .reg_idx = AHSP, - .hwmbox0_reg = 0x00000, - .hwmbox1_reg = 0X08000, - .hwmbox2_reg = 0X10000, - .hwmbox3_reg = 0X18000, - .hwmbox4_reg = 0X20000, - .hwmbox5_reg = 0X28000, - .hwmbox6_reg = 0X30000, - .hwmbox7_reg = 0X38000, - .empty_int_ie = 0x8, - }, - .adsp_shared_mem_hwmbox = 0x18000, /* HWMBOX3 */ - .adsp_thread_hwmbox = 0x20000, /* HWMBOX4 */ - .adsp_os_config_hwmbox = 0X28000, /* HWMBOX5 */ - .adsp_state_hwmbox = 0x30000, /* HWMBOX6 */ - .adsp_irq_hwmbox = 0x38000, /* HWMBOX7 */ - .acast_init = nvadsp_acast_t18x_init, - .reset_init = nvadsp_reset_t18x_init, - .os_init = nvadsp_os_t18x_init, -#ifdef CONFIG_PM - .pm_init = nvadsp_pm_t18x_init, -#endif - - .amc_err_war = false, - - /* Populate Chip ID Major Revision as well */ - .chipid_ext = 0x9, - .num_irqs = NVADSP_VIRQ_MAX, -}; - +/** + * List of compatibles and associated chip data + */ +extern struct nvadsp_chipdata tegrat18x_adsp_chipdata; +extern struct nvadsp_chipdata tegra239_adsp_chipdata; static const struct of_device_id nvadsp_of_match[] = { { .compatible = "nvidia,tegra18x-adsp", @@ -701,7 +641,6 @@ static const struct of_device_id nvadsp_of_match[] = { }, }; MODULE_DEVICE_TABLE(of, nvadsp_of_match); -#endif static struct platform_driver nvadsp_driver __refdata = { .driver = { diff --git a/drivers/platform/tegra/nvadsp/dev.h b/drivers/platform/tegra/nvadsp/dev.h index a27e6f49..c248bd4b 100644 --- a/drivers/platform/tegra/nvadsp/dev.h +++ b/drivers/platform/tegra/nvadsp/dev.h @@ -128,7 +128,7 @@ struct nvadsp_cluster_mem { }; typedef int (*acast_init) (struct platform_device *pdev); -typedef int (*reset_init) (struct platform_device *pdev); +typedef int (*dev_init) (struct platform_device *pdev); typedef int (*os_init) (struct platform_device *pdev); #ifdef CONFIG_PM typedef int (*pm_init) (struct platform_device *pdev); @@ -143,7 +143,7 @@ struct nvadsp_chipdata { u32 adsp_os_config_hwmbox; u32 adsp_boot_config_hwmbox; acast_init acast_init; - reset_init reset_init; + dev_init dev_init; os_init os_init; #ifdef CONFIG_PM pm_init pm_init; @@ -216,6 +216,7 @@ struct nvadsp_drv_data { int (*set_boot_freqs)(struct nvadsp_drv_data *drv_data); bool (*check_wfi_status)(struct nvadsp_drv_data *drv_data); int (*map_hwmbox_interrupts)(struct nvadsp_drv_data *drv_data); + void (*dump_core_state)(struct nvadsp_drv_data *drv_data); struct nvadsp_pm_state state; bool adsp_os_running; @@ -331,12 +332,12 @@ static inline int __init nvadsp_pm_init(struct platform_device *pdev) return -EINVAL; } #endif -static inline int __init nvadsp_reset_init(struct platform_device *pdev) +static inline int __init nvadsp_dev_init(struct platform_device *pdev) { struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev); - if (drv_data->chip_data->reset_init) - return drv_data->chip_data->reset_init(pdev); + if (drv_data->chip_data->dev_init) + return drv_data->chip_data->dev_init(pdev); return -EINVAL; } diff --git a/drivers/platform/tegra/nvadsp/os.c b/drivers/platform/tegra/nvadsp/os.c index 6be15b78..832b0d40 100644 --- a/drivers/platform/tegra/nvadsp/os.c +++ b/drivers/platform/tegra/nvadsp/os.c @@ -28,14 +28,12 @@ #include -#include "amisc.h" #include "ape_actmon.h" #include "os.h" #include "dev.h" #include "dram_app_mem_manager.h" #include "adsp_console_dbfs.h" #include "hwmailbox.h" -#include "log_state.h" #define MAILBOX_REGION ".mbox_shared_data" #define DEBUG_RAM_REGION ".debug_mem_logs" @@ -543,15 +541,6 @@ static void *get_mailbox_shared_region(struct nvadsp_os_data *priv, return nvadsp_da_to_va_mappings(drv_data, addr, size); } -static void copy_io_in_l(void *to, const void *from, int sz) -{ - int i; - for (i = 0; i < sz; i += 4) { - u32 val = *(u32 *)(from + i); - writel(val, (void __iomem *)(to + i)); - } -} - static int nvadsp_os_elf_load(struct nvadsp_os_data *priv, const struct firmware *fw) { @@ -1336,104 +1325,6 @@ static int nvadsp_set_ape_freq(struct nvadsp_drv_data *drv_data) return ret; } -static int nvadsp_t210_set_clks_and_prescalar(struct nvadsp_drv_data *drv_data) -{ - struct nvadsp_os_data *priv = drv_data->os_priv; - struct nvadsp_shared_mem *shared_mem = drv_data->shared_adsp_os_data; - struct nvadsp_os_args *os_args = &shared_mem->os_args; - struct device *dev = &priv->pdev->dev; - unsigned long max_adsp_freq; - unsigned long adsp_freq; - u32 max_index; - u32 cur_index; - int ret = 0; - - adsp_freq = drv_data->adsp_freq * 1000; /* in Hz*/ - - max_adsp_freq = clk_round_rate(drv_data->adsp_cpu_abus_clk, - ULONG_MAX); - max_index = max_adsp_freq / MIN_ADSP_FREQ; - cur_index = adsp_freq / MIN_ADSP_FREQ; - - - if (!adsp_freq) - /* Set max adsp boot freq */ - cur_index = max_index; - - if (adsp_freq % MIN_ADSP_FREQ) { - if (cur_index >= max_index) - cur_index = max_index; - else - cur_index++; - } else if (cur_index >= max_index) - cur_index = max_index; - - /* - * timer interval = (prescalar + 1) * (count + 1) / periph_freq - * therefore for 0 count, - * 1 / TIMER_CLK_HZ = (prescalar + 1) / periph_freq - * Hence, prescalar = periph_freq / TIMER_CLK_HZ - 1 - */ - os_args->timer_prescalar = cur_index - 1; - - adsp_freq = cur_index * MIN_ADSP_FREQ; - - ret = clk_set_rate(drv_data->adsp_cpu_abus_clk, adsp_freq); - if (ret) - goto end; - - drv_data->adsp_freq = adsp_freq / 1000; /* adsp_freq in KHz*/ - drv_data->adsp_freq_hz = adsp_freq; - - /* adspos uses os_args->adsp_freq_hz for EDF */ - os_args->adsp_freq_hz = adsp_freq; - -end: - dev_dbg(dev, "adsp cpu freq %luKHz\n", - clk_get_rate(drv_data->adsp_cpu_abus_clk) / 1000); - dev_dbg(dev, "timer prescalar %x\n", os_args->timer_prescalar); - - return ret; -} - -static int nvadsp_set_adsp_clks(struct nvadsp_drv_data *drv_data) -{ - struct nvadsp_shared_mem *shared_mem = drv_data->shared_adsp_os_data; - struct nvadsp_os_args *os_args = &shared_mem->os_args; - struct platform_device *pdev = drv_data->pdev; - struct device *dev = &pdev->dev; - unsigned long max_adsp_freq; - unsigned long adsp_freq; - int ret = 0; - - adsp_freq = drv_data->adsp_freq_hz; /* in Hz*/ - - /* round rate shall be used with adsp parent clk i.e. aclk */ - max_adsp_freq = clk_round_rate(drv_data->aclk_clk, ULONG_MAX); - - /* Set max adsp boot freq */ - if (!adsp_freq) - adsp_freq = max_adsp_freq; - - /* set rate shall be used with adsp parent clk i.e. aclk */ - ret = clk_set_rate(drv_data->aclk_clk, adsp_freq); - if (ret) { - dev_err(dev, "setting adsp_freq:%luHz failed.\n", adsp_freq); - dev_err(dev, "max_adsp_freq:%luHz\n", max_adsp_freq); - goto end; - } - - drv_data->adsp_freq = adsp_freq / 1000; /* adsp_freq in KHz*/ - drv_data->adsp_freq_hz = adsp_freq; - - /* adspos uses os_args->adsp_freq_hz for EDF */ - os_args->adsp_freq_hz = adsp_freq; -end: - dev_dbg(dev, "adsp cpu freq %luKHz\n", - clk_get_rate(drv_data->adsp_clk) / 1000); - return ret; -} - static int __deassert_adsp(struct nvadsp_drv_data *d) { struct platform_device *pdev = d->pdev; @@ -1496,53 +1387,24 @@ static int nvadsp_assert_adsp(struct nvadsp_drv_data *drv_data) static int nvadsp_set_boot_vec(struct nvadsp_drv_data *drv_data) { - struct platform_device *pdev = drv_data->pdev; - struct device *dev = &pdev->dev; - if (drv_data->set_boot_vec) return drv_data->set_boot_vec(drv_data); - else { - dev_dbg(dev, "Copying EVP...\n"); - copy_io_in_l(drv_data->state.evp_ptr, - drv_data->state.evp, - AMC_EVP_SIZE); - } return 0; } static int nvadsp_set_boot_freqs(struct nvadsp_drv_data *drv_data) { - struct nvadsp_os_data *priv = drv_data->os_priv; - struct device *dev = &priv->pdev->dev; - struct device_node *node = dev->of_node; int ret = 0; - if (drv_data->set_boot_freqs) - return drv_data->set_boot_freqs(drv_data); - /* on Unit-FPGA do not set clocks, return success */ if (drv_data->adsp_unit_fpga) return 0; - if (of_device_is_compatible(node, "nvidia,tegra210-adsp")) { - if (drv_data->adsp_cpu_abus_clk) { - ret = nvadsp_t210_set_clks_and_prescalar(drv_data); - if (ret) - goto end; - } else { - ret = -EINVAL; + if (drv_data->set_boot_freqs) { + ret = drv_data->set_boot_freqs(drv_data); + if (ret) goto end; - } - } else { - if (drv_data->adsp_clk) { - ret = nvadsp_set_adsp_clks(drv_data); - if (ret) - goto end; - } else { - ret = -EINVAL; - goto end; - } } if (drv_data->ape_clk) { @@ -1695,9 +1557,9 @@ static void dump_adsp_logs(struct nvadsp_os_data *priv) dev_err(dev, "End of ADSP log dump .....\n"); } +#ifdef CONFIG_AGIC_EXT_APIS static void print_agic_irq_states(struct nvadsp_os_data *priv) { -#ifdef CONFIG_AGIC_EXT_API struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv->pdev); int start_irq = drv_data->chip_data->start_irq; int end_irq = drv_data->chip_data->end_irq; @@ -1711,266 +1573,8 @@ static void print_agic_irq_states(struct nvadsp_os_data *priv) tegra_agic_irq_is_active(i) ? "active" : "not active"); } +} #endif // CONFIG_AGIC_EXT_APIS -} - -static void print_arm_mode_regs(struct nvadsp_os_data *priv) -{ - struct nvadsp_exception_context *excep_context; - struct arm_fault_frame_shared *shared_frame; - struct arm_mode_regs_shared *shared_regs; - struct nvadsp_shared_mem *shared_mem; - struct device *dev = &priv->pdev->dev; - struct nvadsp_drv_data *drv_data; - - drv_data = platform_get_drvdata(priv->pdev); - shared_mem = drv_data->shared_adsp_os_data; - excep_context = &shared_mem->exception_context; - shared_frame = &excep_context->frame; - shared_regs = &excep_context->regs; - - dev_err(dev, "dumping arm mode register data...\n"); - dev_err(dev, "%c fiq r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_FIQ) ? '*' : ' ', - shared_regs->fiq_r13, shared_regs->fiq_r14); - dev_err(dev, "%c irq r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_IRQ) ? '*' : ' ', - shared_regs->irq_r13, shared_regs->irq_r14); - dev_err(dev, "%c svc r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_SVC) ? '*' : ' ', - shared_regs->svc_r13, shared_regs->svc_r14); - dev_err(dev, "%c und r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_UND) ? '*' : ' ', - shared_regs->und_r13, shared_regs->und_r14); - dev_err(dev, "%c sys r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_SYS) ? '*' : ' ', - shared_regs->sys_r13, shared_regs->sys_r14); - dev_err(dev, "%c abt r13 0x%08x r14 0x%08x\n", - ((shared_frame->spsr & MODE_MASK) == MODE_ABT) ? '*' : ' ', - shared_regs->abt_r13, shared_regs->abt_r14); -} - -static void print_arm_fault_frame(struct nvadsp_os_data *priv) -{ - struct nvadsp_exception_context *excep_context; - struct arm_fault_frame_shared *shared_frame; - struct nvadsp_shared_mem *shared_mem; - struct device *dev = &priv->pdev->dev; - struct nvadsp_drv_data *drv_data; - - drv_data = platform_get_drvdata(priv->pdev); - shared_mem = drv_data->shared_adsp_os_data; - excep_context = &shared_mem->exception_context; - shared_frame = &excep_context->frame; - - dev_err(dev, "dumping fault frame...\n"); - dev_err(dev, "r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n", - shared_frame->r[0], shared_frame->r[1], shared_frame->r[2], - shared_frame->r[3]); - dev_err(dev, "r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", - shared_frame->r[4], shared_frame->r[5], shared_frame->r[6], - shared_frame->r[7]); - dev_err(dev, "r8 0x%08x r9 0x%08x r10 0x%08x r11 0x%08x\n", - shared_frame->r[8], shared_frame->r[9], shared_frame->r[10], - shared_frame->r[11]); - dev_err(dev, "r12 0x%08x usp 0x%08x ulr 0x%08x pc 0x%08x\n", - shared_frame->r[12], shared_frame->usp, shared_frame->ulr, - shared_frame->pc); - dev_err(dev, "spsr 0x%08x\n", shared_frame->spsr); - -} - -static void dump_thread_name(struct platform_device *pdev, u32 val) -{ - dev_info(&pdev->dev, "%s: adsp current thread: %c%c%c%c\n", - __func__, - (val >> 24) & 0xFF, (val >> 16) & 0xFF, - (val >> 8) & 0xFF, (val >> 0) & 0xFF); -} - -static void dump_irq_num(struct platform_device *pdev, u32 val) -{ - dev_info(&pdev->dev, "%s: adsp current/last irq : %d\n", - __func__, val); -} - -static void get_adsp_state(struct nvadsp_os_data *priv) -{ - struct nvadsp_drv_data *drv_data; - struct device *dev; - uint32_t val; - const char *msg; - - if (!priv->pdev) { - pr_err("ADSP Driver is not initialized\n"); - return; - } - - drv_data = platform_get_drvdata(priv->pdev); - dev = &priv->pdev->dev; - - if (drv_data->chip_data->adsp_state_hwmbox == 0) { - dev_info(dev, "%s: No state hwmbox available\n", __func__); - return; - } - - val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_state_hwmbox); - dev_info(dev, "%s: adsp state hwmbox value: 0x%X\n", __func__, val); - - switch (val) { - - case ADSP_LOADER_MAIN_ENTRY: - msg = "loader_main: entry to loader_main"; - break; - case ADSP_LOADER_MAIN_CACHE_DISABLE_COMPLETE: - msg = "loader_main: Cache has been disabled"; - break; - case ADSP_LOADER_MAIN_CONFIGURE_MMU_COMPLETE: - msg = "loader_main: MMU configuration is complete"; - break; - case ADSP_LOADER_MAIN_CACHE_ENABLE_COMPLETE: - msg = "loader_main: Cache has been enabled"; - break; - case ADSP_LOADER_MAIN_FPU_ENABLE_COMPLETE: - msg = "loader_main: FPU has been enabled"; - break; - case ADSP_LOADER_MAIN_DECOMPRESSION_COMPLETE: - msg = "loader_main: ADSP FW decompression is complete"; - break; - case ADSP_LOADER_MAIN_EXIT: - msg = "loader_main: exiting loader_main function"; - break; - - case ADSP_START_ENTRY_AT_RESET: - msg = "start: ADSP is at reset"; - break; - case ADSP_START_CPU_EARLY_INIT: - msg = "start: ADSP to do cpu_early_init"; - break; - case ADSP_START_FIRST_BOOT: - msg = "start: ADSP is booting for first time," - "initializing DATA and clearing BSS"; - break; - case ADSP_START_LK_MAIN_ENTRY: - msg = "start: ADSP about to enter lk_main"; - break; - - case ADSP_LK_MAIN_ENTRY: - msg = "lk_main: entry to lk_main"; - break; - case ADSP_LK_MAIN_EARLY_THREAD_INIT_COMPLETE: - msg = "lk_main: early_thread_init has been completed"; - break; - case ADSP_LK_MAIN_EARLY_ARCH_INIT_COMPLETE: - msg = "lk_main: early_arch_init has been completed"; - break; - case ADSP_LK_MAIN_EARLY_PLATFORM_INIT_COMPLETE: - msg = "lk_main: early_platform_init has been completed"; - break; - case ADSP_LK_MAIN_EARLY_TARGET_INIT_COMPLETE: - msg = "lk_main: early_target_init has been completed"; - break; - case ADSP_LK_MAIN_CONSTRUCTOR_INIT_COMPLETE: - msg = "lk_main: constructors has been called"; - break; - case ADSP_LK_MAIN_HEAP_INIT_COMPLETE: - msg = "lk_main: heap has been initialized"; - break; - case ADSP_LK_MAIN_KERNEL_INIT_COMPLETE: - msg = "lk_main: ADSP kernel has been initialized"; - break; - case ADSP_LK_MAIN_CPU_RESUME_ENTRY: - msg = "lk_main: ADSP is about to resume from suspend"; - break; - - case ADSP_BOOTSTRAP2_ARCH_INIT_COMPLETE: - msg = "bootstrap2: ADSP arch_init is complete"; - break; - case ADSP_BOOTSTRAP2_PLATFORM_INIT_COMPLETE: - msg = "bootstrap2: platform has been initialized"; - break; - case ADSP_BOOTSTRAP2_TARGET_INIT_COMPLETE: - msg = "bootstrap2: target has been initialized"; - break; - case ADSP_BOOTSTRAP2_APP_MODULE_INIT_COMPLETE: - msg = "bootstrap2: APP modules initialized"; - break; - case ADSP_BOOTSTRAP2_APP_INIT_COMPLETE: - msg = "bootstrap2: APP init is complete"; - break; - case ADSP_BOOTSTRAP2_STATIC_APP_INIT_COMPLETE: - msg = "bootstrap2: Static apps has been initialized"; - break; - case ADSP_BOOTSTRAP2_OS_LOAD_COMPLETE: - msg = "bootstrap2: ADSP OS successfully loaded"; - break; - case ADSP_SUSPEND_BEGINS: - msg = "suspend: begins"; - break; - case ADSP_SUSPEND_MBX_SEND_COMPLETE: - msg = "suspend: mbox send complete"; - break; - case ADSP_SUSPEND_DISABLED_TIMERS: - msg = "suspend: timers disabled"; - break; - case ADSP_SUSPEND_DISABLED_INTS: - msg = "suspend: interrupts disabled"; - break; - case ADSP_SUSPEND_ARAM_SAVED: - msg = "suspend: aram saved"; - break; - case ADSP_SUSPEND_AMC_SAVED: - msg = "suspend: amc saved"; - break; - case ADSP_SUSPEND_AMISC_SAVED: - msg = "suspend: amisc saved"; - break; - case ADSP_SUSPEND_L1_CACHE_DISABLED: - msg = "suspend: l1 cache disabled"; - break; - case ADSP_SUSPEND_L2_CACHE_DISABLED: - msg = "suspend: l2 cache disabled"; - break; - case ADSP_RESUME_ADSP: - msg = "resume: beings"; - break; - case ADSP_RESUME_AMISC_RESTORED: - msg = "resume: amisc restored"; - break; - case ADSP_RESUME_AMC_RESTORED: - msg = "resume: amc restored"; - break; - case ADSP_RESUME_ARAM_RESTORED: - msg = "resume: aram restored"; - break; - case ADSP_RESUME_COMPLETE: - msg = "resume: complete"; - break; - case ADSP_WFI_ENTER: - msg = "WFI: Entering WFI"; - break; - case ADSP_WFI_EXIT: - msg = "WFI: Exiting WFI, Failed to Enter"; - break; - case ADSP_DFS_MBOX_RECV: - msg = "DFS: mbox received"; - break; - case ADSP_DFS_MBOX_SENT: - msg = "DFS: mbox sent"; - break; - default: - msg = "Unrecognized ADSP state!!"; - break; - } - - dev_info(dev, "%s: %s\n", __func__, msg); - - val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_thread_hwmbox); - dump_thread_name(priv->pdev, val); - - val = hwmbox_readl(drv_data, drv_data->chip_data->adsp_irq_hwmbox); - dump_irq_num(priv->pdev, val); -} static void _nvadsp_dump_adsp_sys(struct nvadsp_handle *nvadsp_handle) { @@ -1987,12 +1591,16 @@ static void _nvadsp_dump_adsp_sys(struct nvadsp_handle *nvadsp_handle) dump_adsp_logs(priv); dump_mailbox_regs(drv_data); - print_arm_fault_frame(priv); - print_arm_mode_regs(priv); - get_adsp_state(priv); + + if (drv_data->dump_core_state) + drv_data->dump_core_state(drv_data); + if (priv->adma_dump_ch_reg) (*priv->adma_dump_ch_reg)(); + +#ifdef CONFIG_AGIC_EXT_APIS print_agic_irq_states(priv); +#endif } static void nvadsp_free_os_interrupts(struct nvadsp_os_data *priv) @@ -2239,34 +1847,10 @@ end: static bool nvadsp_check_wfi_status(struct nvadsp_drv_data *drv_data) { - int cnt = 0; - bool wfi_status = true; - u32 adsp_status; - if (drv_data->check_wfi_status) - wfi_status = drv_data->check_wfi_status(drv_data); - else { - /* - * Check L2_IDLE and L2_CLKSTOPPED in ADSP_STATUS - * NOTE: Standby mode in ADSP L2CC Power Control - * register should be enabled for this - */ - do { - adsp_status = amisc_readl(drv_data, AMISC_ADSP_STATUS); - if ((adsp_status & AMISC_ADSP_L2_IDLE) && - (adsp_status & AMISC_ADSP_L2_CLKSTOPPED)) - break; - cnt++; - mdelay(1); - } while (cnt < 5); + return drv_data->check_wfi_status(drv_data); - if (cnt >= 5) { - pr_err("ADSP L2C clock not halted: 0x%x\n", adsp_status); - wfi_status = false; - } - } - - return wfi_status; + return true; } static int __nvadsp_os_suspend(struct nvadsp_os_data *priv) diff --git a/drivers/platform/tegra/nvadsp/os.h b/drivers/platform/tegra/nvadsp/os.h index 48c4b379..a3efea98 100644 --- a/drivers/platform/tegra/nvadsp/os.h +++ b/drivers/platform/tegra/nvadsp/os.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /** - * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2024, NVIDIA CORPORATION. All rights reserved. */ #ifndef __TEGRA_NVADSP_OS_H @@ -17,42 +17,9 @@ #define SYM_NAME_SZ 128 -#define AMC_EVP_RESET_VEC_0 0x700 -#define AMC_EVP_UNDEF_VEC_0 0x704 -#define AMC_EVP_SWI_VEC_0 0x708 -#define AMC_EVP_PREFETCH_ABORT_VEC_0 0x70c -#define AMC_EVP_DATA_ABORT_VEC_0 0x710 -#define AMC_EVP_RSVD_VEC_0 0x714 -#define AMC_EVP_IRQ_VEC_0 0x718 -#define AMC_EVP_FIQ_VEC_0 0x71c -#define AMC_EVP_RESET_ADDR_0 0x720 -#define AMC_EVP_UNDEF_ADDR_0 0x724 -#define AMC_EVP_SWI_ADDR_0 0x728 -#define AMC_EVP_PREFETCH_ABORT_ADDR_0 0x72c -#define AMC_EVP_DATA_ABORT_ADDR_0 0x730 -#define AMC_EVP_RSVD_ADDR_0 0x734 -#define AMC_EVP_IRQ_ADDR_0 0x738 -#define AMC_EVP_FIQ_ADDR_0 0x73c - -#define AMC_EVP_SIZE (AMC_EVP_FIQ_ADDR_0 - AMC_EVP_RESET_VEC_0 + 4) -#define AMC_EVP_WSIZE (AMC_EVP_SIZE >> 2) - #define OS_LOAD_TIMEOUT 5000 /* ms */ #define ADSP_COM_MBOX_ID 2 -#define MIN_ADSP_FREQ 38400000lu /* in Hz */ - -/* macros used to find the current mode of ADSP */ -#define MODE_MASK 0x1f -#define MODE_USR 0x10 -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_MON 0x16 -#define MODE_ABT 0x17 -#define MODE_UND 0x1b -#define MODE_SYS 0x1f - /* * ADSP OS Config *