nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 09:11:26 +03:00
Code Issues Packages Projects Releases Wiki Activity

tegra: prod: use legacy prod settings

Browse Source 
Remove references to upstream prod settings and use legacy prod.

Bug 4765671

Change-Id: Iafe36bdeab027ae121a99bfda665cc28089907c6
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3186209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Krishna Yarlagadda
2024-08-01 01:13:49 +00:00
committed by mobile promotions
parent 2ca08ce7f4
commit 9dc14f1027
8 changed files with 39 additions and 209 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/net/can/mttcan/hal/m_ttcan.c
View File

@@ -291,7 +291,7 @@ inline u32 ttcan_read_ecr(struct ttcan_controller *ttcan)
return ttcan_read32(ttcan, ADR_MTTCAN_ECR);
}
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#if defined(CONFIG_TEGRA_PROD_LEGACY)
static void tegra_mttcan_config_prod_settings(struct mttcan_priv *priv)
{
struct ttcan_controller *ttcan = priv->ttcan;
@@ -315,47 +315,6 @@ static void tegra_mttcan_config_prod_settings(struct mttcan_priv *priv)
if (ret == 0)
dev_dbg(priv->device, "setting prod: %s\n", prod_name);
}
#else
static void tegra_mttcan_write_prod_settings(struct mttcan_priv *priv, const char *prod_name)
{
struct ttcan_controller *ttcan = priv->ttcan;
struct tegra_prod_reg_info *reg_info;
struct tegra_prod_cfg_info *prod_cfg;
u32 rval;
int i;
prod_cfg = tegra_prod_get_by_name_from_list(priv->device, ttcan->prod_list, prod_name);
if (prod_cfg == NULL)
return;
reg_info = prod_cfg->reg_info;
for (i = 0; i < prod_cfg->num_reg_info; ++i) {
rval = ttcan_read32(ttcan, reg_info[i].reg_offset);
rval &= ~reg_info[i].reg_mask;
rval |= reg_info[i].reg_value;
ttcan_write32(ttcan, reg_info[i].reg_offset, rval);
}
}
static void tegra_mttcan_config_prod_settings(struct mttcan_priv *priv)
{
struct ttcan_controller *ttcan = priv->ttcan;
char *prod_name;
switch (ttcan->bt_config.data.bitrate) {
case MTTCAN_SPEED_5MBPS:
prod_name = "prod_c_can_5m";
break;
case MTTCAN_SPEED_8MBPS:
prod_name = "prod_c_can_8m";
break;
default:
prod_name = "prod_c_can_2m_1m";
break;
}
tegra_mttcan_write_prod_settings(priv, prod_name);
}
#endif
int ttcan_set_bitrate(struct mttcan_priv *priv)
@@ -411,8 +370,10 @@ int ttcan_set_bitrate(struct mttcan_priv *priv)
return ret;
}
#if defined(CONFIG_TEGRA_PROD_LEGACY)
if (ttcan->prod_list)
tegra_mttcan_config_prod_settings(priv);
#endif
temp_reg = cccr_reg = ttcan_read32(ttcan, ADR_MTTCAN_CCCR);
if (ttcan->bt_config.fd_flags & CAN_FD_FLAG)

4
drivers/net/can/mttcan/include/m_ttcan.h
View File

@@ -287,10 +287,8 @@ struct ttcan_controller {
struct list_head rx_q1;
struct list_head rx_b;
struct list_head tx_evt;
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#if defined(CONFIG_TEGRA_PROD_LEGACY)
struct tegra_prod *prod_list;
#else
struct tegra_prod_cfg_list *prod_list;
#endif
void __iomem *base; /* controller regs space should be remapped. */
void __iomem *xbase; /* extra registers are mapped */

4
drivers/net/can/mttcan/include/m_ttcan_linux.h
View File

@@ -31,7 +31,9 @@
#include <linux/net_tstamp.h>
#include <linux/spinlock.h>
#include <linux/clocksource.h>
#include <linux/tegra-oot-prod.h>
#if defined(CONFIG_TEGRA_PROD_LEGACY)
#include <linux/tegra_prod.h>
#endif
#include <linux/platform/tegra/ptp-notifier.h>
#include <linux/mailbox_client.h>
#ifdef CONFIG_CLK_SRC_TEGRA18_US_TIMER

28
drivers/net/can/mttcan/native/m_ttcan_linux.c
View File

@@ -12,28 +12,6 @@
#define CAN_MSG_FLUSH_TIMEOUT 100
static void mttcan_start(struct net_device *dev);
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#define MTTCAN_PROD_FIELD(name, rindex, roffset, fname) \
{ \
.field_name = name, \
.reg_index = rindex, \
.reg_offset = roffset, \
.field_start = fname##_FIELD_START, \
.field_len = fname##_FIELD_WIDTH, \
}
static const struct tegra_prod_dev_reg_field mttcan_prod_dev_reg_field[] = {
MTTCAN_PROD_FIELD("nvidia,can-enable-tdc-dbtp", 0, ADR_MTTCAN_DBTP, MTTCAN_CORE_DBTP_TDC),
MTTCAN_PROD_FIELD("nvidia,can-tdco-value-tdcr", 0, ADR_MTTCAN_TDCR, MTTCAN_CORE_TDCR_TDCO),
};
static const struct tegra_prod_dev_info mttcan_prod_dev_info = {
.num_total_dev_reg = 2,
.num_dev_reg_field = ARRAY_SIZE(mttcan_prod_dev_reg_field),
.dev_reg_field = mttcan_prod_dev_reg_field,
};
#endif
/* We are reading cntvct_el0 for TSC time. We are not issuing ISB
* before reading the counter as by the time CAN irq comes and
* CAN softirq is executed, we would have lot of instruction executed.
@@ -1877,15 +1855,13 @@ static int mttcan_probe(struct platform_device *pdev)
if (ret)
goto exit_free_device;
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#if defined(CONFIG_TEGRA_PROD_LEGACY)
priv->ttcan->prod_list = devm_tegra_prod_get(&pdev->dev);
#else
priv->ttcan->prod_list = devm_tegra_prod_get_list(&pdev->dev, &mttcan_prod_dev_info);
#endif
if (IS_ERR_OR_NULL(priv->ttcan->prod_list)) {
dev_dbg(&pdev->dev, "Prod-setting not available\n");
priv->ttcan->prod_list = NULL;
}
#endif
ret = register_mttcan_dev(dev);
if (ret) {

8
drivers/pinctrl/pinctrl-tegra194-pexclk-padctrl.c
View File

@@ -13,7 +13,9 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/tegra-oot-prod.h>
#if defined(CONFIG_TEGRA_PROD_LEGACY)
#include <linux/tegra_prod.h>
#endif
#define PCIE_PEXCLK_PADCTL1_REFCLK_OVRD_0 0x8
#define CFG2TMC_SW_CTL BIT(0)
@@ -57,7 +59,9 @@ struct t194_pexclk_padctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *regs[2];
#if defined(CONFIG_TEGRA_PROD_LEGACY)
struct tegra_prod *prod_list;
#endif
struct t194_pexclk_pads *pads;
int num_pads;
struct pinctrl_desc pinctrl_desc;
@@ -198,6 +202,7 @@ static int t194_pexclk_padctrl_probe(struct platform_device *pdev)
}
}
#if defined(CONFIG_TEGRA_PROD_LEGACY)
pexclk->prod_list = devm_tegra_prod_get(&pdev->dev);
if (IS_ERR(pexclk->prod_list)) {
dev_dbg(&pdev->dev, "Prod-settngs not available\n");
@@ -210,6 +215,7 @@ static int t194_pexclk_padctrl_probe(struct platform_device *pdev)
return ret;
}
}
#endif
pexclk->pads = t194_pexclk_pads;
pexclk->num_pads = ARRAY_SIZE(t194_pexclk_pads);

67
drivers/scsi/ufs/ufs-tegra-common.c
View File

@@ -40,29 +40,6 @@
#include "ufs-tegra.h"
#include "ufs-provision.h"
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#define UFS_PROD_FIELD(name, rindex, roffset, fname) \
{ \
.field_name = name, \
.reg_index = rindex, \
.reg_offset = roffset, \
.field_start = fname##_FIELD_START, \
.field_len = fname##_FIELD_LEN, \
}
static const struct tegra_prod_dev_reg_field ufs_prod_dev_reg_field[] = {
UFS_PROD_FIELD("nvidia,tx_hs_equilizer_setting", 0,
MPHY_TX_APB_TX_ATTRIBUTE_34_37_0, TX_HS_Equalizer_Setting),
};
static const struct tegra_prod_dev_info ufs_prod_dev_info = {
.num_total_dev_reg = 1,
.num_dev_reg_field = ARRAY_SIZE(ufs_prod_dev_reg_field),
.dev_reg_field = ufs_prod_dev_reg_field,
};
#endif
static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra);
#ifdef CONFIG_DEBUG_FS
@@ -1843,44 +1820,14 @@ static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd086, 0x0U), 0x80U);
}
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
static void tegra_ufs_write_prod_settings(struct ufs_tegra_host *ufs_tegra, const char *prod_name)
{
struct tegra_prod_reg_info *reg_info;
struct tegra_prod_cfg_info *prod_cfg;
u32 rval;
int i;
prod_cfg = tegra_prod_get_by_name_from_list(ufs_tegra->hba->dev, ufs_tegra->prod_list, prod_name);
if (prod_cfg == NULL)
return;
reg_info = prod_cfg->reg_info;
for (i = 0; i < prod_cfg->num_reg_info; ++i) {
rval = mphy_readl(ufs_tegra->mphy_l0_base, reg_info[i].reg_offset);
rval &= ~reg_info[i].reg_mask;
rval |= reg_info[i].reg_value;
mphy_writel(ufs_tegra->mphy_l0_base, rval, reg_info[i].reg_offset);
if (ufs_tegra->x2config) {
rval = mphy_readl(ufs_tegra->mphy_l1_base, reg_info[i].reg_offset);
rval &= ~reg_info[i].reg_mask;
rval |= reg_info[i].reg_value;
mphy_writel(ufs_tegra->mphy_l1_base, rval, reg_info[i].reg_offset);
}
}
}
#endif
#if defined(CONFIG_TEGRA_PROD_LEGACY)
static void ufs_tegra_prod_settings(struct ufs_tegra_host *ufs_tegra)
{
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
int err;
#endif
if (!ufs_tegra->prod_list)
return;
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
err = tegra_prod_set_by_name(&ufs_tegra->mphy_l0_base, "prod", ufs_tegra->prod_list);
if (err < 0) {
dev_info_once(ufs_tegra->hba->dev,
@@ -1894,11 +1841,9 @@ static void ufs_tegra_prod_settings(struct ufs_tegra_host *ufs_tegra)
dev_info_once(ufs_tegra->hba->dev,
"Prod config not found for mphy1: %d\n", err);
}
#else
tegra_ufs_write_prod_settings(ufs_tegra, "prod");
#endif
return;
}
#endif
/**
* ufs_tegra_init - bind phy with controller
@@ -2006,15 +1951,13 @@ static int ufs_tegra_init(struct ufs_hba *hba)
}
}
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#if defined(CONFIG_TEGRA_PROD_LEGACY)
ufs_tegra->prod_list = devm_tegra_prod_get(dev);
#else
ufs_tegra->prod_list = devm_tegra_prod_get_list(dev, &ufs_prod_dev_info);
#endif
if (IS_ERR(ufs_tegra->prod_list)) {
dev_dbg(dev, "No Prod list\n");
ufs_tegra->prod_list = NULL;
}
#endif
/*
* Clocks are not present on VDK
@@ -2104,8 +2047,10 @@ end:
}
}
#if defined(CONFIG_TEGRA_PROD_LEGACY)
/* Configure prod values */
ufs_tegra_prod_settings(ufs_tegra);
#endif
#ifdef CONFIG_DEBUG_FS
ufs_tegra_init_debugfs(hba);

8
drivers/scsi/ufs/ufs-tegra.h
View File

@@ -7,7 +7,9 @@
#include <linux/io.h>
#include <soc/tegra/fuse.h>
#include <linux/tegra-oot-prod.h>
#if defined(CONFIG_TEGRA_PROD_LEGACY)
#include <linux/tegra_prod.h>
#endif
#define NV_ADDRESS_MAP_MPHY_L0_BASE 0x02470000
#define NV_ADDRESS_MAP_MPHY_L1_BASE 0x02480000
@@ -397,9 +399,7 @@ struct ufs_tegra_host {
u32 ref_clk_freq;
struct ufs_tegra_soc_data *soc;
u32 streamid;
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
struct tegra_prod_cfg_list *prod_list;
#else
#if defined(CONFIG_TEGRA_PROD_LEGACY)
struct tegra_prod *prod_list;
#endif

82
drivers/spi/spi-tegra210-quad.c
View File

@@ -25,7 +25,9 @@
#include <linux/acpi.h>
#include <linux/property.h>
#include <linux/version.h>
#include <linux/tegra-oot-prod.h>
#if defined(CONFIG_TEGRA_PROD_LEGACY)
#include <linux/tegra_prod.h>
#endif
#define QSPI_COMMAND1 0x000
#define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
@@ -255,47 +257,11 @@ struct tegra_qspi {
dma_addr_t tx_dma_phys;
struct dma_async_tx_descriptor *tx_dma_desc;
const struct tegra_qspi_soc_data *soc_data;
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
struct tegra_prod_cfg_list *prod_list;
#else
#if defined(CONFIG_TEGRA_PROD_LEGACY)
struct tegra_prod *prod_list;
#endif
};
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#define QSPI_PROD_FIELD(name, rindex, roffset, fname) \
{ \
.field_name = name, \
.reg_index = rindex, \
.reg_offset = roffset, \
.field_start = fname##_FIELD_START, \
.field_len = fname##_FIELD_LEN, \
}
static const struct tegra_prod_dev_reg_field qspi_prod_dev_reg_field[] = {
QSPI_PROD_FIELD("nvidia,qspi-rx-tap-delay", 0,
QSPI_COMMAND2, QSPI_RX_TAP_DELAY),
QSPI_PROD_FIELD("nvidia,qspi-tx-tap-delay", 0,
QSPI_COMMAND2, QSPI_TX_TAP_DELAY),
QSPI_PROD_FIELD("nvidia,qspi-sel-vreg", 0,
QSPI_TRIM_CTRL, QSPI_TRIM_VSEL),
QSPI_PROD_FIELD("nvidia,qspi-clk-override", 0,
QSPI_MISC_REG, QSPI_MISC_CLEKEN_OVERRIDE),
QSPI_PROD_FIELD("nvidia,qspi-comp-pad-drv-dn-ovr", 0,
QSPI_COMP_CONTROL, QSPI_COMP_CONTROL_DRVDN_OVR),
QSPI_PROD_FIELD("nvidia,qspi-comp-pad-drv-up-ovr", 0,
QSPI_COMP_CONTROL, QSPI_COMP_CONTROL_DRVUP_OVR),
QSPI_PROD_FIELD("nvidia,qspi-comp-pad-e-input", 0,
QSPI_COMP_CONTROL, QSPI_COMP_CONTROL_PAD_E_INPUT),
};
static const struct tegra_prod_dev_info qspi_prod_dev_info = {
.num_total_dev_reg = 4,
.num_dev_reg_field = ARRAY_SIZE(qspi_prod_dev_reg_field),
.dev_reg_field = qspi_prod_dev_reg_field,
};
#endif
static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset)
{
return readl(tqspi->base + offset);
@@ -967,33 +933,10 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
return command1;
}
#if defined(CONFIG_TEGRA_PROD_NEXT_GEN)
static void tegra_qspi_write_prod_settings(struct tegra_qspi *tqspi, const char *prod_name)
{
struct tegra_prod_reg_info *reg_info;
struct tegra_prod_cfg_info *prod_cfg;
u32 rval;
int i;
prod_cfg = tegra_prod_get_by_name_from_list(tqspi->dev, tqspi->prod_list, prod_name);
if (prod_cfg == NULL)
return;
reg_info = prod_cfg->reg_info;
for (i = 0; i < prod_cfg->num_reg_info; ++i) {
rval = tegra_qspi_readl(tqspi, reg_info[i].reg_offset);
rval &= ~reg_info[i].reg_mask;
rval |= reg_info[i].reg_value;
tegra_qspi_writel(tqspi, rval, reg_info[i].reg_offset);
}
}
#endif
#if defined(CONFIG_TEGRA_PROD_LEGACY)
static void tegra_qspi_set_gr_registers(struct tegra_qspi *tqspi)
{
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
int err;
#endif
if (!tqspi->prod_list)
goto regs_por;
@@ -1001,14 +944,10 @@ static void tegra_qspi_set_gr_registers(struct tegra_qspi *tqspi)
/* If available, initialise the config registers
* for QSPI with the values mentioned in prod list.
*/
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
err = tegra_prod_set_by_name(&tqspi->base, "prod", tqspi->prod_list);
if (err < 0)
dev_info_once(tqspi->dev,
"Prod config not found for QSPI: %d\n", err);
#else
tegra_qspi_write_prod_settings(tqspi, "prod");
#endif
return;
regs_por:
@@ -1019,6 +958,7 @@ regs_por:
tegra_qspi_writel(tqspi, tqspi->spi_cs_timing1, QSPI_CS_TIMING1);
tegra_qspi_writel(tqspi, tqspi->spi_cs_timing2, QSPI_CS_TIMING2);
}
#endif
static int tegra_qspi_start_transfer_one(struct spi_device *spi,
struct spi_transfer *t, u32 command1)
@@ -1741,15 +1681,13 @@ static int tegra_qspi_probe(struct platform_device *pdev)
tqspi->controller = controller;
tqspi->dev = &pdev->dev;
#if !defined(CONFIG_TEGRA_PROD_NEXT_GEN)
#if defined(CONFIG_TEGRA_PROD_LEGACY)
tqspi->prod_list = devm_tegra_prod_get(&pdev->dev);
#else
tqspi->prod_list = devm_tegra_prod_get_list(&pdev->dev, &qspi_prod_dev_info);
#endif
if (IS_ERR_OR_NULL(tqspi->prod_list)) {
dev_info(&pdev->dev, "Prod settings list not found\n");
tqspi->prod_list = NULL;
}
#endif
spin_lock_init(&tqspi->lock);
@@ -1813,7 +1751,9 @@ static int tegra_qspi_probe(struct platform_device *pdev)
tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
#if defined(CONFIG_TEGRA_PROD_LEGACY)
tegra_qspi_set_gr_registers(tqspi);
#endif
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
@@ -1879,7 +1819,9 @@ static int __maybe_unused tegra_qspi_resume(struct device *dev)
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2);
#if defined(CONFIG_TEGRA_PROD_LEGACY)
tegra_qspi_set_gr_registers(tqspi);
#endif
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
pm_runtime_put(dev);