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DCE-KMD: Update DCE OS abstraction - Part 5

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Modules covered in this CL: dce-os-ivc

This is not a functional CL. It does the following:
1) Move os/include/linux-kmd/os-ivc.h to
   os/linux/include/dce-os-ivc.h

2) s/os_ivc/dce_os_ivc/g

3) Delete old intermediate header os/include/os-ivc.h and include
   <dce-os-ivc.h> directly.

JIRA TDS-16126

Change-Id: Ib6264a39910dbb4a107fd2261005c5e593b4b9b7
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3228545
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
This commit is contained in:
anupamg
2024-10-11 23:19:51 +00:00
committed by Jon Hunter
parent 562347a94e
commit 9f31ca7c42
4 changed files with 26 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/platform/tegra/dce/dce-ipc.c
View File

@@ -242,8 +242,8 @@ int dce_ipc_channel_init_unlocked(struct tegra_dce *d, u32 ch_type)
}
q_info = &ch->q_info;
msg_sz = os_ivc_align(q_info->frame_sz);
q_sz = os_ivc_total_queue_size(msg_sz * q_info->nframes);
msg_sz = dce_os_ivc_align(q_info->frame_sz);
q_sz = dce_os_ivc_total_queue_size(msg_sz * q_info->nframes);
r = &d->d_ipc.region;
if (!r->base) {
@@ -251,7 +251,7 @@ int dce_ipc_channel_init_unlocked(struct tegra_dce *d, u32 ch_type)
goto out_lock_destroy;
}
ret = os_ivc_init(&ch->d_ivc,
ret = dce_os_ivc_init(&ch->d_ivc,
(char *)r->base + r->s_offset, (char *)r->base + r->s_offset + q_sz,
r->iova + r->s_offset, r->iova + r->s_offset + q_sz,
q_info->nframes, msg_sz);
@@ -346,7 +346,7 @@ bool dce_ipc_channel_is_ready(struct tegra_dce *d, u32 ch_type)
dce_os_mutex_lock(&ch->lock);
is_est = (os_ivc_notified(&ch->d_ivc) ? false : true);
is_est = (dce_os_ivc_notified(&ch->d_ivc) ? false : true);
ch->signal.notify(d, &ch->signal.to_d);
@@ -393,7 +393,7 @@ void dce_ipc_channel_reset(struct tegra_dce *d, u32 ch_type)
dce_os_mutex_lock(&ch->lock);
os_ivc_reset(&ch->d_ivc);
dce_os_ivc_reset(&ch->d_ivc);
trace_ivc_channel_reset_triggered(d, ch);
@@ -430,7 +430,7 @@ static int _dce_ipc_get_next_write_buff(struct dce_ipc_channel *ch)
int err = 0;
if (ch != NULL)
err = os_ivc_get_next_write_frame(&ch->d_ivc, &ch->obuff);
err = dce_os_ivc_get_next_write_frame(&ch->d_ivc, &ch->obuff);
else
err = -EINVAL;
@@ -476,7 +476,7 @@ static int _dce_ipc_write_channel(struct dce_ipc_channel *ch,
memcpy(ch->obuff, data, size);
#endif
return os_ivc_write_advance(&ch->d_ivc);
return dce_os_ivc_write_advance(&ch->d_ivc);
}
/**
@@ -534,7 +534,7 @@ static int _dce_ipc_get_next_read_buff(struct dce_ipc_channel *ch)
int err = 0;
if (ch != NULL)
err = os_ivc_get_next_read_frame(&ch->d_ivc, &ch->ibuff);
err = dce_os_ivc_get_next_read_frame(&ch->d_ivc, &ch->ibuff);
else
err = -EINVAL;
@@ -579,7 +579,7 @@ static int _dce_ipc_read_channel(struct dce_ipc_channel *ch,
memcpy(data, ch->ibuff, size);
#endif
return os_ivc_read_advance(&ch->d_ivc);
return dce_os_ivc_read_advance(&ch->d_ivc);
}
/**
@@ -728,7 +728,7 @@ bool dce_ipc_is_data_available(struct tegra_dce *d, u32 ch_type)
dce_os_mutex_lock(&ch->lock);
err = os_ivc_get_next_read_frame(&ch->d_ivc, &frame);
err = dce_os_ivc_get_next_read_frame(&ch->d_ivc, &frame);
if (err == 0)
ret = true;

4
drivers/platform/tegra/dce/include/dce-ipc.h
View File

@@ -8,7 +8,7 @@
#include <dce-os-lock.h>
#include <dce-os-types.h>
#include <os-ivc.h>
#include <dce-os-ivc.h>
#include <interface/dce-admin-cmds.h>
#include <interface/dce-core-interface-ipc-types.h>
@@ -129,7 +129,7 @@ struct dce_ipc_channel {
void *ibuff;
void *obuff;
#endif
os_ivc_t d_ivc;
dce_os_ivc_t d_ivc;
struct tegra_dce *d;
struct dce_os_mutex lock;
struct dce_ipc_signal signal;

24
drivers/platform/tegra/dce/os/include/os-ivc.h
View File

@@ -1,24 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
*
* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
* property and proprietary rights in and to this material, related
* documentation and any modifications thereto. Any use, reproduction,
* disclosure or distribution of this material and related documentation
* without an express license agreement from NVIDIA CORPORATION or
* its affiliates is strictly prohibited.
*/
#ifndef NVDISPLAY_SERVER_OS_IVC_H
#define NVDISPLAY_SERVER_OS_IVC_H
#ifdef __KERNEL__
#include <linux-kmd/os-ivc.h>
#elif defined(NVDISPLAY_SERVER_HVRTOS)
#include <hvrtos/os-ivc.h>
#else
#error "OS Not Supported"
#endif
#endif /* NVDISPLAY_SERVER_OS_IVC_H */

35
drivers/platform/tegra/dce/os/include/linux-kmd/os-ivc.h → drivers/platform/tegra/dce/os/linux/include/dce-os-ivc.h
View File

@@ -1,22 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
*
* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
* property and proprietary rights in and to this material, related
* documentation and any modifications thereto. Any use, reproduction,
* disclosure or distribution of this material and related documentation
* without an express license agreement from NVIDIA CORPORATION or
* its affiliates is strictly prohibited.
*/
#ifndef NVDISPLAY_SERVER_OS_IVC_LINUX_H
#define NVDISPLAY_SERVER_OS_IVC_LINUX_H
#ifndef DCE_OS_IVC_H
#define DCE_OS_IVC_H
#include <soc/tegra/ivc.h>
#include <nvidia/conftest.h>
typedef struct tegra_ivc os_ivc_t;
typedef struct tegra_ivc dce_os_ivc_t;
/*
* Kernel API tegra_ivc_init() needs notify function as non NULL.
@@ -30,7 +23,7 @@ static void ivc_signal_target(struct tegra_ivc *ivc, void *data)
/* Returns 0 on success, or a negative error value if failed. */
static inline int os_ivc_init(os_ivc_t *ivc,
static inline int dce_os_ivc_init(dce_os_ivc_t *ivc,
void *recv_base, void *send_base,
dma_addr_t rx_phys, dma_addr_t tx_phys, /* TODO: Confirm if it's ok to remove IOVA args. These shouldn't be required here. */
unsigned int num_frames, size_t frame_size)
@@ -52,13 +45,13 @@ static inline int os_ivc_init(os_ivc_t *ivc,
ivc_signal_target, NULL);
}
static inline void os_ivc_reset(os_ivc_t *ivc)
static inline void dce_os_ivc_reset(dce_os_ivc_t *ivc)
{
return tegra_ivc_reset(ivc);
}
/* Returns 0 on success, or a negative error value if failed. */
static inline int os_ivc_notified(os_ivc_t *ivc)
static inline int dce_os_ivc_notified(dce_os_ivc_t *ivc)
{
return tegra_ivc_notified(ivc);
}
@@ -68,7 +61,7 @@ static inline int os_ivc_notified(os_ivc_t *ivc)
* This function will populate address of next write frame
* info functions ppframe input argument.
*/
static inline int os_ivc_get_next_write_frame(os_ivc_t *ivc, void **ppframe)
static inline int dce_os_ivc_get_next_write_frame(dce_os_ivc_t *ivc, void **ppframe)
{
int err = 0;
@@ -97,7 +90,7 @@ done:
}
/* Returns 0, or a negative error value if failed. */
static inline int os_ivc_write_advance(os_ivc_t *ivc)
static inline int dce_os_ivc_write_advance(dce_os_ivc_t *ivc)
{
return tegra_ivc_write_advance(ivc);
}
@@ -107,7 +100,7 @@ static inline int os_ivc_write_advance(os_ivc_t *ivc)
* This function will populate address of next read frame
* info functions ppframe input argument.
*/
static inline int os_ivc_get_next_read_frame(os_ivc_t *ivc, void **ppframe)
static inline int dce_os_ivc_get_next_read_frame(dce_os_ivc_t *ivc, void **ppframe)
{
int err = 0;
@@ -136,20 +129,20 @@ done:
}
/* Returns 0, or a negative error value if failed. */
static inline int os_ivc_read_advance(os_ivc_t *ivc)
static inline int dce_os_ivc_read_advance(dce_os_ivc_t *ivc)
{
return tegra_ivc_read_advance(ivc);
}
/* TODO: Need safe coversion between size_t and uint32_t types. */
static inline uint32_t os_ivc_align(uint32_t size)
static inline uint32_t dce_os_ivc_align(uint32_t size)
{
return (uint32_t)tegra_ivc_align((size_t) size);
}
static inline uint32_t os_ivc_total_queue_size(uint32_t size)
static inline uint32_t dce_os_ivc_total_queue_size(uint32_t size)
{
return tegra_ivc_total_queue_size(size);
}
#endif /* NVDISPLAY_SERVER_OS_IVC_LINUX_H */
#endif /* DCE_OS_IVC_H */