From a2ee9f655fa96a7fe977c7a3abd90d1c89380d4f Mon Sep 17 00:00:00 2001 From: Mark Mendez Date: Sun, 29 Dec 2024 12:08:14 -0800 Subject: [PATCH] PCT: Create devicetree validation schema This is the output of the automated scripts created to parse the dtb and dts files congruently Jira ESDP-27666 Change-Id: Ic82a3f813bcbe6e78ba5f9b68875293c5d4bc6d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274878 Tested-by: Mark Mendez Reviewed-by: Laxman Dewangan --- .../nvidia,tegra-hv-oops-storage.yaml | 95 + .../nvidia,tegra-hv-storage.yaml | 104 + .../tegra_virt_storage/nvidia,tegra-hv.yaml | 55 + .../bus/nvidia,tegra264-aocluster.yaml | 64 + .../bindings/clocksource/arm,armv8-timer.yaml | 86 + .../clocksource/nvidia,tegra234-timer.yaml | 102 + .../nvidia,tegra264-ccplex-cluster.yaml | 80 + .../bindings/cpuidle/arm,idle-state.yaml | 85 + .../bindings/cpuidle/arm,psci-1.0.yaml | 60 + .../cpuidle/nvidia,cpuidle-tegra-auto.yaml | 49 + .../nvidia,tegra-se-5.1-hv-vse-safety.yaml | 86 + .../crypto/tegra/nvidia,tegra264-kds.yaml | 102 + .../crypto/tegra/nvidia,tegra264-se-aes.yaml | 123 ++ .../crypto/tegra/nvidia,tegra264-se-hash.yaml | 123 ++ .../crypto/tegra/nvidia,tegra264-se-sm4.yaml | 123 ++ .../bindings/dma/nvidia,tegra264-adma.yaml | 210 ++ .../bindings/dma/nvidia,tegra264-gpcdma.yaml | 163 ++ .../tegra/nvidia,tegra194-safe-bpmp-hv.yaml | 104 + .../gpio/nvidia,tegra264-gpio-aon.yaml | 132 ++ .../gpio/nvidia,tegra264-gpio-main.yaml | 160 ++ .../gpio/nvidia,tegra264-gpio-uphy.yaml | 148 ++ .../gpio/nvidia,tegra264-pinmux-main.yaml | 78 + .../gpio/nvidia,tegra264-pinmux-uphy.yaml | 77 + .../gpu/drm/tegra/nvidia,tegra234-vi.yaml | 117 ++ ...nvidia,tegra264-host1x-virtual-engine.yaml | 135 ++ .../gpu/drm/tegra/nvidia,tegra264-host1x.yaml | 289 +++ .../bindings/hte/nvidia,tegra264-gte-aon.yaml | 115 ++ .../bindings/hte/nvidia,tegra264-gte-lic.yaml | 111 ++ .../devicetree/bindings/hwmon/ti,tmp451.yaml | 107 ++ .../arm,embedded-trace-extension.yaml | 68 + .../coresight/arm,trace-buffer-extension.yaml | 74 + .../i2c/busses/nvidia,tegra264-i2c.yaml | 244 +++ .../bindings/input/keyboard/gpio-keys.yaml | 58 + .../mailbox/nvidia,tegra264-hsp-hv.yaml | 141 ++ .../bindings/mailbox/nvidia,tegra264-hsp.yaml | 142 ++ .../cam_fsync/nvidia,tegra264-cdi-tsc.yaml | 89 + .../nvidia,tegra-camrtc-capture-isp.yaml | 67 + .../nvidia,tegra-camrtc-capture-vi.yaml | 101 + .../platform/tegra/cdi/nvidia,cdi-mgr.yaml | 59 + .../platform/tegra/cdi/nvidia,cim_ver.yaml | 62 + .../platform/tegra/isc/nvidia,isc-mgr.yaml | 91 + .../memory/tegra/nvidia,tegra264-emc.yaml | 144 ++ .../private-soc/nvidia,t264-smmu-hwpm.yaml | 80 + .../nvidia,tegra-t264-mc-hwpm.yaml | 92 + .../nvidia,tegra-t264-mem-qual.yaml | 102 + .../private-soc/nvidia,tegra-t26x-mc.yaml | 76 + .../devicetree/bindings/mfd/cache.yaml | 260 +++ .../bindings/mfd/nvidia,vrs-pseq.yaml | 101 + .../bindings/misc/arm,armv8-pmuv3.yaml | 74 + .../misc/arm,coresight-dynamic-funnel.yaml | 103 + .../arm,coresight-dynamic-replicator.yaml | 103 + .../bindings/misc/arm,coresight-stm.yaml | 113 ++ .../bindings/misc/arm,coresight-tmc.yaml | 124 ++ .../bindings/misc/mods/nvidia,mods_smmu.yaml | 187 ++ .../misc/mods/nvidia,mods_tegra_dma.yaml | 133 ++ .../bindings/misc/mods/nvidia,mods_test.yaml | 51 + .../bindings/misc/mods/simple-bus.yaml | 71 + .../misc/nvidia,csi-isp-map-config.yaml | 70 + .../misc/nvidia,dulink-connection.yaml | 125 ++ .../bindings/misc/nvidia,fsi-carveout.yaml | 103 + .../misc/nvidia,generic_carveout.yaml | 83 + .../bindings/misc/nvidia,mods-clocks.yaml | 1693 +++++++++++++++++ .../bindings/misc/nvidia,smmu_test.yaml | 68 + .../bindings/misc/nvidia,t264-soc-hwpm.yaml | 228 +++ .../nvidia,tegra-SafetyServiceConfig.yaml | 79 + .../misc/nvidia,tegra-bpmp-dummy.yaml | 64 + .../misc/nvidia,tegra-fsicom-CcplexApp.yaml | 54 + .../misc/nvidia,tegra-fsicom-EPD.yaml | 57 + .../misc/nvidia,tegra-fsicom-channels.yaml | 75 + .../misc/nvidia,tegra-fsicom-sampleApp1.yaml | 54 + .../misc/nvidia,tegra-fsicom-sampleAppGR.yaml | 54 + .../misc/nvidia,tegra186-hsp-mailbox.yaml | 85 + .../misc/nvidia,tegra194-pva0-hsp.yaml | 50 + .../misc/nvidia,tegra264-aconnect.yaml | 95 + .../misc/nvidia,tegra264-adsp-audio-hv.yaml | 74 + .../bindings/misc/nvidia,tegra264-agic.yaml | 140 ++ .../nvidia,tegra264-audio-graph-card.yaml | 105 + .../misc/nvidia,tegra264-bpmp-i2c.yaml | 71 + .../misc/nvidia,tegra264-bpmp-shmem.yaml | 82 + .../misc/nvidia,tegra264-display-niso.yaml | 72 + .../misc/nvidia,tegra264-display.yaml | 551 ++++++ .../bindings/misc/nvidia,tegra264-hda.yaml | 165 ++ .../misc/nvidia,tegra264-isp-thi.yaml | 82 + .../misc/nvidia,tegra264-mixer-control.yaml | 52 + .../bindings/misc/nvidia,tegra264-rce.yaml | 293 +++ .../bindings/misc/nvidia,tegra264-rtc.yaml | 130 ++ .../bindings/misc/nvidia,tegra264-tsec.yaml | 167 ++ .../misc/nvidia,tegra264-virt-pcm-oot.yaml | 144 ++ .../bindings/misc/nvidia,tegra26x-ist.yaml | 51 + .../nvidia,tegra-nvscic2c-pcie-epc.yaml | 97 + .../nvidia,tegra-nvscic2c-pcie-epf.yaml | 102 + .../bindings/misc/sha-carveout.yaml | 51 + .../mmc/host/nvidia,tegra264-sdhci.yaml | 309 +++ .../nvidia,tegra-virt-mtd-storage.yaml | 86 + .../bindings/mtd/spi-nor/jedec,spi-nor.yaml | 80 + .../mttcan/native/nvidia,tegra264-mttcan.yaml | 186 ++ .../bindings/nvmem/nvidia,tegra264-efuse.yaml | 103 + .../bindings/nvpmodel/nvidia,nvpmodel.yaml | 81 + .../bindings/nvpps/nvidia,tegra264-nvpps.yaml | 84 + .../devicetree/bindings/of/ramoops.yaml | 116 ++ .../bindings/of/shared-dma-pool.yaml | 87 + .../pci/controller/arm,gic-v3-its.yaml | 95 + .../bindings/pci/controller/arm,gic-v3.yaml | 153 ++ .../pci/controller/pci-host-ecam-generic.yaml | 207 ++ .../private-soc/nvidia,tegra264-pcie-ep.yaml | 230 +++ .../private-soc/nvidia,tegra264-pcie.yaml | 233 +++ .../bindings/perf/arm,smmu-v3-pmcg.yaml | 117 ++ .../devicetree/bindings/perf/arm,smmu-v3.yaml | 132 ++ ...rm,statistical-profiling-extension-v1.yaml | 74 + .../perf/arm_cspmu/arm,coresight-pmu.yaml | 120 ++ .../tegra/nvidia,tegra264-xusb-padctl.yaml | 135 ++ .../phy/tegra/nvidia,tegra264-xusb.yaml | 240 +++ .../pinctrl/nvidia,tegra234-misc.yaml | 77 + .../nvidia,tegra264-misc-dpaux-padctl.yaml | 76 + .../tegra/nvidia,tegra264-pinmux-aon.yaml | 77 + .../tegra/dce/nvidia,tegra264-dce.yaml | 128 ++ .../mc-utils/nvidia,tegra264-mc-utils.yaml | 57 + .../tegra/mc-utils/nvidia,tegra264-mc.yaml | 203 ++ .../tegra/nvadsp/nvidia,tegra264-adsp.yaml | 249 +++ .../tegra/nvadsp/nvidia,tegra264-adsp1.yaml | 249 +++ .../tegra/nvadsp/nvidia,tegra264-aon.yaml | 242 +++ .../tegra/nvidia,tegra234-epl-client.yaml | 148 ++ .../tegra/nvidia,tegra234-fsicom-client.yaml | 125 ++ .../tegra/nvidia,tegra23x-hsierrrptinj.yaml | 74 + .../tegra/nvidia,tegra264-cactmon-mc-all.yaml | 102 + .../platform/tegra/nvidia,tegra_bl_debug.yaml | 54 + .../tegra/psc/nvidia,tegra234-psc.yaml | 201 ++ .../rtcpu/nvidia,tegra-camrtc-hsp-vm.yaml | 81 + .../nvidia,tegra186-camera-diagnostics.yaml | 83 + ...6-camera-ivc-protocol-capture-control.yaml | 83 + ...,tegra186-camera-ivc-protocol-capture.yaml | 83 + ...idia,tegra186-camera-ivc-protocol-dbg.yaml | 83 + ...ia,tegra186-camera-ivc-protocol-debug.yaml | 114 ++ ...dia,tegra186-camera-ivc-protocol-echo.yaml | 83 + .../pwm/nvidia,pwm-tegra264-tachometer.yaml | 150 ++ .../bindings/pwm/nvidia,tegra264-pwm.yaml | 146 ++ .../devicetree/bindings/ras/arm,armv8.yaml | 149 ++ .../scsi/ufs/tegra264,ufs_variant.yaml | 314 +++ .../cbb/nvidia,tegra264-sys-cbb-fabric.yaml | 105 + .../cbb/nvidia,tegra264-top0-cbb-fabric.yaml | 105 + .../cbb/nvidia,tegra264-uphy0-cbb-fabric.yaml | 105 + .../nvidia,tegra264-vision-cbb-fabric.yaml | 105 + .../tegra/fuse/nvidia,efuse-nvmem-helper.yaml | 63 + .../soc/tegra/nvidia,tegra264-pmc.yaml | 123 ++ .../spi/nvidia,tegra186-spi-slave.yaml | 225 +++ .../bindings/spi/nvidia,tegra234-qspi.yaml | 235 +++ .../bindings/spi/nvidia,tegra234-spi.yaml | 230 +++ .../devicetree/bindings/spi/tegra-spidev.yaml | 73 + .../thermal/nvidia,tegra234-oc-event.yaml | 55 + .../tegra/nvidia,tegra186-bpmp-thermal.yaml | 57 + .../bindings/tty/serial/arm,pl011.yaml | 220 +++ .../bindings/tty/serial/arm,sbsa-uart.yaml | 119 ++ .../tty/serial/nvidia,tegra264-utc.yaml | 116 ++ .../usb/gadget/udc/nvidia,tegra264-xudc.yaml | 201 ++ .../usb/host/nvidia,tegra264-xusb-vf1.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf2.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf3.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf4.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf5.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf6.yaml | 128 ++ .../usb/host/nvidia,tegra264-xusb-vf7.yaml | 128 ++ .../host/capture/nvidia,tegra234-vi-thi.yaml | 79 + .../host/capture/nvidia,tegra264-isp-thi.yaml | 79 + .../tegra/host/isp/nvidia,tegra264-isp.yaml | 158 ++ .../host/nvcsi/nvidia,tegra194-nvcsi.yaml | 103 + .../nvidia,pva-tegra264-iommu-context.yaml | 80 + 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a/Documentation/devicetree/bindings/block/tegra_oops_virt_storage/nvidia,tegra-hv-oops-storage.yaml b/Documentation/devicetree/bindings/block/tegra_oops_virt_storage/nvidia,tegra-hv-oops-storage.yaml new file mode 100644 index 00000000..415d4eee --- /dev/null +++ b/Documentation/devicetree/bindings/block/tegra_oops_virt_storage/nvidia,tegra-hv-oops-storage.yaml @@ -0,0 +1,95 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_virt_storage88/nvidia,tegra-hv-oops-storage.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-hv-oops-storage is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/block/tegra_oops_virt_storage/tegra_hv_vblk_oops.c + + The following nodes use this compatibility + - /tegra_virt_storage88 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-hv-oops-storage + + required: + - compatible + +properties: + + pstore_max_reason: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + pstore_kmsg_size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + instance: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1f + maximum: 0x1f + + ivc: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0x45 + + mempool: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1d + maximum: 0x1d + + partition-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - gos0-crashlogs + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - iommus + +examples: + - | + tegra_virt_storage88 { + }; diff --git a/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv-storage.yaml b/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv-storage.yaml new file mode 100644 index 00000000..4e3eba22 --- /dev/null +++ b/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv-storage.yaml @@ -0,0 +1,104 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_virt_storage79/nvidia,tegra-hv-storage.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-hv-storage is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/block/tegra_virt_storage/tegra_hv_vblk.c + + The following nodes use this compatibility + - /tegra_virt_storage79 + - /tegra_virt_storage80 + - /tegra_virt_storage81 + - /tegra_virt_storage82 + - /tegra_virt_storage84 + - /tegra_virt_storage85 + - /tegra_virt_storage86 + - /tegra_virt_storage87 + - /tegra_virt_storage89 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-hv-storage + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + instance: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x3c + + ivc: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0x46 + + mempool: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x13 + maximum: 0x1e + + partition-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - gos0-shared-pers + - gos0-ufs + - gos0_nvlog + - pers-ota + - ist-runtimeinfo + - ist-resultdata + - gos0-fs + - gos0-rw-overlay + - custom + + + read-only: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - iommus + +examples: + - | + tegra_virt_storage79 { + }; diff --git a/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv.yaml b/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv.yaml new file mode 100644 index 00000000..03478f26 --- /dev/null +++ b/Documentation/devicetree/bindings/block/tegra_virt_storage/nvidia,tegra-hv.yaml @@ -0,0 +1,55 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hyp/nvidia,tegra-hv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-hv is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/block/tegra_virt_storage/tegra_hv_vblk.c + - /kernel/nvidia-oot/drivers/block/tegra_oops_virt_storage/tegra_hv_vblk_oops.c + - /kernel/nvidia-oot/drivers/virt/tegra/tegra_hv_vcpu_yield.c + - /kernel/nvidia-oot/drivers/virt/tegra/tegra_hv.c + - /kernel/nvidia-oot/drivers/virt/tegra/tegra_hv_pm_ctl.c + - /kernel/nvidia-oot/drivers/platform/tegra/tegra-hv-xhci-debug.c + - /kernel/nvidia-oot/drivers/platform/tegra/tegra-hv-xhci.c + + The following nodes use this compatibility + - /hyp + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-hv + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + hyp { + }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra264-aocluster.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra264-aocluster.yaml new file mode 100644 index 00000000..19529eae --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra264-aocluster.yaml @@ -0,0 +1,64 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/aocluster@c000000/nvidia,tegra264-aocluster.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-aocluster is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/bus/tegra-aocluster.c + + The following nodes use this compatibility + - /bus@0/aocluster@c000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-aocluster + + required: + - compatible + +properties: + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + +examples: + - | + aocluster@c000000 { + compatible = "nvidia,tegra264-aocluster"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0xc000000 0x0 0xc000000 0x0 0x1000000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/clocksource/arm,armv8-timer.yaml b/Documentation/devicetree/bindings/clocksource/arm,armv8-timer.yaml new file mode 100644 index 00000000..1788b640 --- /dev/null +++ b/Documentation/devicetree/bindings/clocksource/arm,armv8-timer.yaml @@ -0,0 +1,86 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,armv8-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,armv8-timer is mentioned in the following drivers + - /kernel/kernel-oot/drivers/clocksource/arm_arch_timer.c + + The following nodes use this compatibility + - /timer + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,armv8-timer + + required: + - compatible + +properties: + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0xe + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + always-on: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - interrupts + +examples: + - | + timer { + compatible = "arm,armv8-timer"; + status = "disabled"; + interrupts = , + , + , + , + ; + interrupt-parent = <&gic>; + always-on; + }; diff --git a/Documentation/devicetree/bindings/clocksource/nvidia,tegra234-timer.yaml b/Documentation/devicetree/bindings/clocksource/nvidia,tegra234-timer.yaml new file mode 100644 index 00000000..cbba043a --- /dev/null +++ b/Documentation/devicetree/bindings/clocksource/nvidia,tegra234-timer.yaml @@ -0,0 +1,102 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer@8000000/nvidia,tegra234-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-timer is mentioned in the following drivers + - /kernel/kernel-oot/drivers/clocksource/timer-tegra186.c + + The following nodes use this compatibility + - /bus@0/timer@8000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-timer + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000000 + maximum: 0x8000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x140000 + maximum: 0x140000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x305 + maximum: 0x308 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + +required: + - compatible + - reg + - interrupts + +examples: + - | + timer@8000000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x0 0x08000000 0x0 0x00140000>; + interrupts = , + , + , + ; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra264-ccplex-cluster.yaml b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra264-ccplex-cluster.yaml new file mode 100644 index 00000000..ee06398d --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra264-ccplex-cluster.yaml @@ -0,0 +1,80 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ccplex@8120000000/nvidia,tegra264-ccplex-cluster.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-ccplex-cluster is mentioned in the following drivers + - /kernel/kernel-oot/drivers/cpufreq/tegra194-cpufreq.c + + The following nodes use this compatibility + - /bus@0/ccplex@8120000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-ccplex-cluster + + required: + - compatible + +properties: + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32" + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x30000000 + maximum: 0x30000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xcf0000 + maximum: 0xcf0000 + +required: + - compatible + - reg + +examples: + - | + ccplex@8120000000 { + compatible = "nvidia,tegra264-ccplex-cluster"; + status = "disabled"; + nvidia,bpmp = <&bpmp>; + reg = <0x81 0x30000000 0x0 0xcf0000>; + }; diff --git a/Documentation/devicetree/bindings/cpuidle/arm,idle-state.yaml b/Documentation/devicetree/bindings/cpuidle/arm,idle-state.yaml new file mode 100644 index 00000000..2aae99df --- /dev/null +++ b/Documentation/devicetree/bindings/cpuidle/arm,idle-state.yaml @@ -0,0 +1,85 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cc7/arm,idle-state.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,idle-state is mentioned in the following drivers + - /kernel/kernel-oot/drivers/cpuidle/cpuidle-psci.c + - /kernel/kernel-oot/drivers/cpuidle/cpuidle-big_little.c + - /kernel/kernel-oot/drivers/cpuidle/cpuidle-arm.c + + The following nodes use this compatibility + - /cpus/idle-states/cc7 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,idle-state + + required: + - compatible + +properties: + + state-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - Cluster Powergate + + + entry-latency-us: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1388 + maximum: 0x1388 + + exit-latency-us: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1388 + maximum: 0x1388 + + min-residency-us: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x61a8 + maximum: 0x61a8 + + arm,psci-suspend-param: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000007 + maximum: 0x40000007 + +required: + - compatible + +examples: + - | + cc7 { + compatible = "arm,idle-state"; + state-name = "Cluster Powergate"; + entry-latency-us = <5000>; + exit-latency-us = <5000>; + min-residency-us = <25000>; + arm,psci-suspend-param = <0x40000007>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/cpuidle/arm,psci-1.0.yaml b/Documentation/devicetree/bindings/cpuidle/arm,psci-1.0.yaml new file mode 100644 index 00000000..bf7f1ebe --- /dev/null +++ b/Documentation/devicetree/bindings/cpuidle/arm,psci-1.0.yaml @@ -0,0 +1,60 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/psci/arm,psci-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,psci-1.0 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/cpuidle/cpuidle-psci-domain.c + - /kernel/kernel-oot/drivers/firmware/psci/psci.c + + The following nodes use this compatibility + - /psci + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,psci-1.0 + + required: + - compatible + +properties: + + method: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - smc + + +required: + - compatible + +examples: + - | + psci { + compatible = "arm,psci-1.0"; + status = "disabled"; + method = "smc"; + }; diff --git a/Documentation/devicetree/bindings/cpuidle/nvidia,cpuidle-tegra-auto.yaml b/Documentation/devicetree/bindings/cpuidle/nvidia,cpuidle-tegra-auto.yaml new file mode 100644 index 00000000..470096d7 --- /dev/null +++ b/Documentation/devicetree/bindings/cpuidle/nvidia,cpuidle-tegra-auto.yaml @@ -0,0 +1,49 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpuidle/nvidia,cpuidle-tegra-auto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,cpuidle-tegra-auto is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/cpuidle/cpuidle-tegra-auto.c + + The following nodes use this compatibility + - /cpuidle + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,cpuidle-tegra-auto + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + cpuidle { + }; diff --git a/Documentation/devicetree/bindings/crypto/nvidia,tegra-se-5.1-hv-vse-safety.yaml b/Documentation/devicetree/bindings/crypto/nvidia,tegra-se-5.1-hv-vse-safety.yaml new file mode 100644 index 00000000..caa171aa --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/nvidia,tegra-se-5.1-hv-vse-safety.yaml @@ -0,0 +1,86 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vse@C0110000/nvidia,tegra-se-5.1-hv-vse-safety.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-se-5.1-hv-vse-safety is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/crypto/tegra-hv-vse-safety.c + + The following nodes use this compatibility + - /vse@C0110000 + - /vse@C0120000 + - /vse@C0140000 + - /vse@C2430000 + - /vse@C2440000 + - /vse@C2460000 + - /vse@C24A0000 + - /vse@C24B0000 + - /vse@C24D0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-se-5.1-hv-vse-safety + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + se-engine-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xc + + nvidia,ivccfg_cnt: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,ivccfg: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xffffff + +required: + - compatible + - iommus + +examples: + - | + vse@C0110000 { + }; diff --git a/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-kds.yaml b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-kds.yaml new file mode 100644 index 00000000..c91627d8 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-kds.yaml @@ -0,0 +1,102 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto@8189880000/nvidia,tegra264-kds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-kds is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/crypto/tegra/tegra-se-kds.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/crypto@8189880000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-kds + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x89880000 + maximum: 0x89880000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x25 + maximum: 0x25 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - se + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + crypto@8189880000 { + compatible = "nvidia,tegra264-kds"; + reg = <0x81 0x89880000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_SE>; + clock-names = "se"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-aes.yaml b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-aes.yaml new file mode 100644 index 00000000..edb057c7 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-aes.yaml @@ -0,0 +1,123 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto@8188120000/nvidia,tegra264-se-aes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-se-aes is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/crypto/tegra/tegra-se-main.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/crypto@8188120000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-se-aes + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88120000 + maximum: 0x88120000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x25 + maximum: 0x25 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - se + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1802 + maximum: 0x1802 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - clocks + - clock-names + - iommus + +examples: + - | + crypto@8188120000 { + compatible = "nvidia,tegra264-se-aes"; + reg = <0x81 0x88120000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_SE>; + clock-names = "se"; + iommus = <&smmu1_mmu TEGRA_SID_SE_SE2>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-hash.yaml b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-hash.yaml new file mode 100644 index 00000000..917a4a76 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-hash.yaml @@ -0,0 +1,123 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto@8188140000/nvidia,tegra264-se-hash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-se-hash is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/crypto/tegra/tegra-se-main.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/crypto@8188140000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-se-hash + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88140000 + maximum: 0x88140000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x25 + maximum: 0x25 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - se + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1804 + maximum: 0x1804 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - clocks + - clock-names + - iommus + +examples: + - | + crypto@8188140000 { + compatible = "nvidia,tegra264-se-hash"; + reg = <0x81 0x88140000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_SE>; + clock-names = "se"; + iommus = <&smmu1_mmu TEGRA_SID_SE_SE4>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-sm4.yaml b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-sm4.yaml new file mode 100644 index 00000000..70da714e --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/tegra/nvidia,tegra264-se-sm4.yaml @@ -0,0 +1,123 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto@8188110000/nvidia,tegra264-se-sm4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-se-sm4 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/crypto/tegra/tegra-se-main.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/crypto@8188110000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-se-sm4 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88110000 + maximum: 0x88110000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x25 + maximum: 0x25 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - se + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1801 + maximum: 0x1801 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - clocks + - clock-names + - iommus + +examples: + - | + crypto@8188110000 { + compatible = "nvidia,tegra264-se-sm4"; + reg = <0x81 0x88110000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_SE>; + clock-names = "se"; + iommus = <&smmu1_mmu TEGRA_SID_SE_SE1>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra264-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra264-adma.yaml new file mode 100644 index 00000000..15f18fc4 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra264-adma.yaml @@ -0,0 +1,210 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma-controller@9440000/nvidia,tegra264-adma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-adma is mentioned in the following drivers + - /kernel/kernel-oot/drivers/dma/tegra210-adma.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000/dma-controller@9440000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-adma + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9450000 + maximum: 0x9450000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x90 + maximum: 0xbf + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + '#dma-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa3 + maximum: 0xa3 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - d_audio + + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vm + + + dma-channel-mask: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xffff + maximum: 0xffffffff + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + dma-controller@9440000 { + compatible = "nvidia,tegra264-adma"; + reg = <0x0 0x9440000 0x0 0xb0000>; + interrupt-parent = <&agic_page0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + clocks = <&bpmp TEGRA264_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra264-gpcdma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra264-gpcdma.yaml new file mode 100644 index 00000000..10f30044 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra264-gpcdma.yaml @@ -0,0 +1,163 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma-controller@8400000/nvidia,tegra264-gpcdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gpcdma is mentioned in the following drivers + - /kernel/kernel-oot/drivers/dma/tegra186-gpc-dma.c + + The following nodes use this compatibility + - /bus@0/dma-controller@8400000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gpcdma + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8400000 + maximum: 0x8400000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x210000 + maximum: 0x210000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x248 + maximum: 0x267 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + '#dma-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800 + maximum: 0x800 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + dma-channel-mask: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf70dc3fe + maximum: 0xf70dc3fe + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + dma-controller@8400000 { + compatible = "nvidia,tegra264-gpcdma"; + status = "disabled"; + reg = <0x0 0x08400000 0x0 0x210000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <3>; + iommus = <&smmu1_mmu 0x00000800>; + dma-coherent; + dma-channel-mask = <0xfffffffe>; + }; diff --git a/Documentation/devicetree/bindings/firmware/tegra/nvidia,tegra194-safe-bpmp-hv.yaml b/Documentation/devicetree/bindings/firmware/tegra/nvidia,tegra194-safe-bpmp-hv.yaml new file mode 100644 index 00000000..98ec2070 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/tegra/nvidia,tegra194-safe-bpmp-hv.yaml @@ -0,0 +1,104 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bpmp/nvidia,tegra194-safe-bpmp-hv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra194-safe-bpmp-hv is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/firmware/tegra/bpmp-tegra186-hv.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/virt.c + + The following nodes use this compatibility + - /bpmp + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra194-safe-bpmp-hv + + required: + - compatible + +properties: + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x13 + maximum: 0x13 + + '#clock-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#reset-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#power-domain-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + ivc_queue: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xf + + mempool: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + +required: + - compatible + +examples: + - | + bpmp { + compatible = "nvidia,tegra264-bpmp", + "nvidia,tegra234-bpmp", + "nvidia,tegra186-bpmp"; + status = "disabled"; + mboxes = <&top_hsp0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; + memory-region = <&dram_cpu_bpmp_mail>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + numa-node-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-aon.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-aon.yaml new file mode 100644 index 00000000..d60a1521 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-aon.yaml @@ -0,0 +1,132 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio@cf00000/nvidia,tegra264-gpio-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gpio-aon is mentioned in the following drivers + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + + The following nodes use this compatibility + - /bus@0/gpio@cf00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gpio-aon + + required: + - compatible + +properties: + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - security + - gpio + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xcf00000 + maximum: 0xcf10000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x21a + maximum: 0x21d + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + gpio-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#gpio-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - reg + - interrupts + +examples: + - | + gpio@cf00000 { + reg-names = "security, gpio"; + compatible = "nvidia,tegra264-gpio-aon"; + status = "disabled"; + reg = <0x0 0x0cf00000 0x0 0x10000>, + <0x0 0x0cf10000 0x0 0x1000>; + interrupts = , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-main.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-main.yaml new file mode 100644 index 00000000..dfe466d0 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-main.yaml @@ -0,0 +1,160 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio@810c300000/nvidia,tegra264-gpio-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gpio-main is mentioned in the following drivers + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + + The following nodes use this compatibility + - /bus@0/gpio@810c300000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gpio-main + + required: + - compatible + +properties: + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - security + - gpio + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc300000 + maximum: 0xc310000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4000 + maximum: 0x4000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5b + maximum: 0x7a + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + gpio-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#gpio-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - reg + - interrupts + +examples: + - | + gpio@810c300000 { + reg-names = "security, gpio"; + compatible = "nvidia,tegra264-gpio-main"; + status = "disabled"; + reg = <0x81 0x0c300000 0x0 0x4000>, + <0x81 0x0c310000 0x0 0x4000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-uphy.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-uphy.yaml new file mode 100644 index 00000000..3a1716a7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-gpio-uphy.yaml @@ -0,0 +1,148 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio@a808300000/nvidia,tegra264-gpio-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gpio-uphy is mentioned in the following drivers + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + + The following nodes use this compatibility + - /bus@0/gpio@a808300000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gpio-uphy + + required: + - compatible + +properties: + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - security + - gpio + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8300000 + maximum: 0x8310000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000 + maximum: 0x2000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x34b + maximum: 0x35a + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + gpio-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#gpio-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + pinctrl-node: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + +examples: + - | + gpio@a808300000 { + reg-names = "security, gpio"; + compatible = "nvidia,tegra264-gpio-uphy"; + status = "disabled"; + reg = <0xa8 0x08300000 0x0 0x2000>, + <0xa8 0x08310000 0x0 0x2000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-node = <&padctl_uphy>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-main.yaml new file mode 100644 index 00000000..333f4ec9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-main.yaml @@ -0,0 +1,78 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinmux@810c281000/nvidia,tegra264-pinmux-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pinmux-main is mentioned in the following drivers + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + - /kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264-generic.c + - /kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264.c + + The following nodes use this compatibility + - /bus@0/pinmux@810c281000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pinmux-main + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc281000 + maximum: 0xc281000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc000 + maximum: 0xc000 + +required: + - compatible + - reg + +examples: + - | + pinmux@810c281000 { + compatible = "nvidia,tegra264-pinmux-main"; + status = "disabled"; + reg = <0x81 0x0c281000 0x0 0xc000>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-uphy.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-uphy.yaml new file mode 100644 index 00000000..3ae434c3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra264-pinmux-uphy.yaml @@ -0,0 +1,77 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinmux@a8082e0000/nvidia,tegra264-pinmux-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pinmux-uphy is mentioned in the following drivers + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + - /kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264-generic.c + + The following nodes use this compatibility + - /bus@0/pinmux@a8082e0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pinmux-uphy + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x82e0000 + maximum: 0x82e0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4000 + maximum: 0x4000 + +required: + - compatible + - reg + +examples: + - | + pinmux@a8082e0000 { + compatible = "nvidia,tegra264-pinmux-uphy"; + status = "disabled"; + reg = <0xa8 0x082e0000 0x0 0x4000>; + }; diff --git a/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra234-vi.yaml b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra234-vi.yaml new file mode 100644 index 00000000..04ea8e61 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra234-vi.yaml @@ -0,0 +1,117 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vi0@8188400000/nvidia,tegra234-vi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-vi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/drm.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/vic.c + - /kernel/nvidia-oot/drivers/video/tegra/host/capture/capture-support.c + - /kernel/nvidia-oot/drivers/video/tegra/host/vi/vi5.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/vi0@8188400000 + - /bus@0/host1x@8181200000/vi1@8188c00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-vi + + required: + - compatible + +properties: + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2e + maximum: 0x2f + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vi + - vi2 + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x39 + maximum: 0x39 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vi + + + nvidia,vi-falcon-device: + $ref: "/schemas/types.yaml#/definitions/uint32" + + non-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - resets + - reset-names + - clocks + - clock-names + +examples: + - | + vi0@8188400000 { + compatible = "nvidia,tegra234-vi"; + resets = <&bpmp TEGRA264_RESET_VI>; + reset-names = "vi"; + clocks = <&bpmp TEGRA264_CLK_VI>; + clock-names = "vi"; + nvidia,vi-falcon-device = <&vi0_thi>; + iommus = <&smmu0_mmu TEGRA_SID_VI_VM1>; + non-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x-virtual-engine.yaml b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x-virtual-engine.yaml new file mode 100644 index 00000000..f4eb9bf3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x-virtual-engine.yaml @@ -0,0 +1,135 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vic@8188050000/nvidia,tegra264-host1x-virtual-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-host1x-virtual-engine is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/virt.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/drm.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/vic@8188050000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-host1x-virtual-engine + + required: + - compatible + +properties: + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3b + maximum: 0x3b + + interconnects: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6c + maximum: 0x6d + - $ref: "/schemas/types.yaml#/definitions/uint32" + + interconnect-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dma-mem + - write + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3000 + maximum: 0x3000 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,class: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5d + maximum: 0x5d + + nvidia,module-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - clocks + - iommus + +examples: + - | + vic@8188050000 { + compatible = "nvidia,tegra264-vic"; + reg = <0x81 0x88050000 0x00 0x40000>; + interrupts = ; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_VIC>; + resets = <&bpmp TEGRA264_RESET_VIC>; + reset-names = "vic"; + clocks = <&bpmp TEGRA264_CLK_VIC>; + clock-names = "vic"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_VICR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_VICW &emc>; + interconnect-names = "dma-mem, write"; + iommus = <&smmu1_mmu TEGRA_SID_VIC>; + dma-coherent; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x.yaml b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x.yaml new file mode 100644 index 00000000..6eb151fc --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/drm/tegra/nvidia,tegra264-host1x.yaml @@ -0,0 +1,289 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/host1x@8181200000/nvidia,tegra264-host1x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-host1x is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/virt.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/drm.c + - /kernel/nvidia-oot/drivers/gpu/host1x-nvhost/nvhost.c + - /kernel/nvidia-oot/drivers/gpu/host1x-fence/dev.c + - /kernel/nvidia-oot/drivers/gpu/host1x/dev.c + - /kernel/nvidia-oot/drivers/crypto/tegra-hv-vse-safety.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-host1x + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81240000 + maximum: 0x81320000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x20000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vm + - actmon + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x145 + maximum: 0x14e + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - syncpt0 + - syncpt1 + - syncpt2 + - syncpt3 + - syncpt4 + - syncpt5 + - syncpt6 + - syncpt7 + - host1x + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0xe + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - host1x + - actmon + + + interconnects: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x16 + - $ref: "/schemas/types.yaml#/definitions/uint32" + + interconnect-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dma-mem + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xb01 + maximum: 0xb01 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + iommu-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x7 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3001 + maximum: 0x3008 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,channels: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x1d + + nvidia,syncpoints: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x240 + + nvidia,server-ivc: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0x2a + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - iommus + +examples: + - | + host1x@8181200000 { + compatible = "nvidia,tegra264-host1x"; + reg = <0x81 0x81200000 0x0 0x10000>, + <0x81 0x81210000 0x0 0x10000>, + <0x81 0x81240000 0x0 0x10000>, + <0x81 0x81320000 0x0 0x20000>; + reg-names = "common, hypervisor, vm, actmon"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "syncpt0", + "syncpt1", + "syncpt2", + "syncpt3", + "syncpt4", + "syncpt5", + "syncpt6", + "syncpt7", + "host1x"; + clocks = <&bpmp TEGRA264_CLK_HOST1X>, + <&bpmp TEGRA264_CLK_OSC>; + clock-names = "host1x, actmon"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HOST1XR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu1_mmu TEGRA_SID_HOST1X>; + dma-coherent; + #address-cells = <0x2>; + #size-cells = <0x2>; + iommu-map = <0x0 &smmu1_mmu (TEGRA_SID_VIC+0x1) 0x1>, + <0x1 &smmu1_mmu (TEGRA_SID_VIC+0x2) 0x1>, + <0x2 &smmu1_mmu (TEGRA_SID_VIC+0x3) 0x1>, + <0x3 &smmu1_mmu (TEGRA_SID_VIC+0x4) 0x1>, + <0x4 &smmu1_mmu (TEGRA_SID_VIC+0x5) 0x1>, + <0x5 &smmu1_mmu (TEGRA_SID_VIC+0x6) 0x1>, + <0x6 &smmu1_mmu (TEGRA_SID_VIC+0x7) 0x1>, + <0x7 &smmu1_mmu (TEGRA_SID_VIC+0x8) 0x1>; + ranges = <0x81 0x81200000 0x81 0x81200000 0x00 0x10000>, + <0x81 0x81210000 0x81 0x81210000 0x00 0x10000>, + <0x81 0x81240000 0x81 0x81240000 0x00 0x10000>, + <0x81 0x88150000 0x81 0x88150000 0x00 0x40000>, + <0x81 0x88050000 0x81 0x88050000 0x00 0x40000>, + <0x81 0x8c000000 0x81 0x8c000000 0x00 0x900000>, + <0x00 0x10700000 0x00 0x10700000 0x00 0x100000>, + <0x81 0x88140000 0x81 0x88140000 0x00 0x10000>, + <0x81 0x88120000 0x81 0x88120000 0x00 0x10000>, + <0x81 0x88110000 0x81 0x88110000 0x00 0x10000>, + <0x81 0x89880000 0x81 0x89880000 0x00 0x10000>, + <0x81 0x88800000 0x81 0x88800000 0x00 0x300000>; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-aon.yaml b/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-aon.yaml new file mode 100644 index 00000000..8ecb9050 --- /dev/null +++ b/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-aon.yaml @@ -0,0 +1,115 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hardware-timestamp@c2b0000/nvidia,tegra264-gte-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gte-aon is mentioned in the following drivers + - /kernel/kernel-oot/drivers/hte/hte-tegra194.c + + The following nodes use this compatibility + - /bus@0/hardware-timestamp@c2b0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gte-aon + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc2b0000 + maximum: 0xc2b0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x226 + maximum: 0x226 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,int-threshold: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#timestamp-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,gpio-controller: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + +examples: + - | + hardware-timestamp@c2b0000 { + compatible = "nvidia,tegra264-gte-aon"; + reg = <0x0 0x0c2b0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + nvidia,gpio-controller = <&gpio_aon>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-lic.yaml b/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-lic.yaml new file mode 100644 index 00000000..593d7e7d --- /dev/null +++ b/Documentation/devicetree/bindings/hte/nvidia,tegra264-gte-lic.yaml @@ -0,0 +1,111 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hardware-timestamp@8380000/nvidia,tegra264-gte-lic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-gte-lic is mentioned in the following drivers + - /kernel/kernel-oot/drivers/hte/hte-tegra194.c + + The following nodes use this compatibility + - /bus@0/hardware-timestamp@8380000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-gte-lic + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8380000 + maximum: 0x8380000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x268 + maximum: 0x268 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,int-threshold: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#timestamp-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + +required: + - compatible + - reg + - interrupts + +examples: + - | + hardware-timestamp@8380000 { + compatible = "nvidia,tegra264-gte-lic"; + reg = <0x0 0x08380000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp451.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp451.yaml new file mode 100644 index 00000000..26451695 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp451.yaml @@ -0,0 +1,107 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/temp-sensor@4c/ti,tmp451.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = ti,tmp451 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/hwmon/lm90.c + + The following nodes use this compatibility + - /bpmp/i2c/temp-sensor@4c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - ti,tmp451 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4c + maximum: 0x4c + + sensor-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tmp451-ext-soc + + + '#thermal-sensor-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4e + maximum: 0x4e + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x9 + + temp-alert-gpio: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x4e + + offset: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xfffff060 + maximum: 0xfffff060 + +required: + - compatible + - reg + - interrupts + +examples: + - | + temp-sensor@4c { + }; diff --git a/Documentation/devicetree/bindings/hwtracing/coresight/arm,embedded-trace-extension.yaml b/Documentation/devicetree/bindings/hwtracing/coresight/arm,embedded-trace-extension.yaml new file mode 100644 index 00000000..81d23970 --- /dev/null +++ b/Documentation/devicetree/bindings/hwtracing/coresight/arm,embedded-trace-extension.yaml @@ -0,0 +1,68 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ete_cpu_0/arm,embedded-trace-extension.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,embedded-trace-extension is mentioned in the following drivers + - /kernel/kernel-oot/drivers/hwtracing/coresight/coresight-etm4x-core.c + + The following nodes use this compatibility + - /ete_cpu_0 + - /ete_cpu_1 + - /ete_cpu_2 + - /ete_cpu_3 + - /ete_cpu_4 + - /ete_cpu_5 + - /ete_cpu_6 + - /ete_cpu_7 + - /ete_cpu_8 + - /ete_cpu_9 + - /ete_cpu_10 + - /ete_cpu_11 + - /ete_cpu_12 + - /ete_cpu_13 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,embedded-trace-extension + + required: + - compatible + +properties: + + cpu: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + +examples: + - | + ete_cpu_0 { + compatible = "arm,embedded-trace-extension"; + status = "disabled"; + cpu = <&cpu_0>; + }; diff --git a/Documentation/devicetree/bindings/hwtracing/coresight/arm,trace-buffer-extension.yaml b/Documentation/devicetree/bindings/hwtracing/coresight/arm,trace-buffer-extension.yaml new file mode 100644 index 00000000..655e4483 --- /dev/null +++ b/Documentation/devicetree/bindings/hwtracing/coresight/arm,trace-buffer-extension.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/trbe/arm,trace-buffer-extension.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,trace-buffer-extension is mentioned in the following drivers + - /kernel/kernel-oot/drivers/hwtracing/coresight/coresight-trbe.c + + The following nodes use this compatibility + - /trbe + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,trace-buffer-extension + + required: + - compatible + +properties: + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6 + maximum: 0x6 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + +required: + - compatible + - interrupts + +examples: + - | + trbe { + compatible = "arm,trace-buffer-extension"; + status = "disabled"; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/i2c/busses/nvidia,tegra264-i2c.yaml b/Documentation/devicetree/bindings/i2c/busses/nvidia,tegra264-i2c.yaml new file mode 100644 index 00000000..54bcf3f5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/busses/nvidia,tegra264-i2c.yaml @@ -0,0 +1,244 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c@c600000/nvidia,tegra264-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-i2c is mentioned in the following drivers + - /kernel/kernel-oot/drivers/i2c/busses/i2c-tegra.c + + The following nodes use this compatibility + - /bus@0/i2c@c600000 + - /bus@0/i2c@c610000 + - /bus@0/i2c@810c410000 + - /bus@0/i2c@810c420000 + - /bus@0/i2c@810c430000 + - /bus@0/i2c@810c630000 + - /bus@0/i2c@810c640000 + - /bus@0/i2c@810c650000 + - /bus@0/i2c@810c670000 + - /bus@0/i2c@810c680000 + - /bus@0/i2c@810c690000 + - /bus@0/i2c@810c6a0000 + - /bus@0/i2c@810c6b0000 + - /bus@0/i2c@810c6c0000 + - /bus@0/i2c@810c6d0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-i2c + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc410000 + maximum: 0xc6d0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7e + maximum: 0x215 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clock-frequency: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x61a80 + maximum: 0x61a80 + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x14 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1f + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x801 + maximum: 0x81f + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tx + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x801 + maximum: 0x81f + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xd + maximum: 0xa0 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - div-clk + - parent + + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xd + maximum: 0x2f + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0xa0 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xb + maximum: 0x3c + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - i2c + + +required: + - compatible + - reg + - interrupts + - iommus + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + i2c@c600000 { + compatible = "nvidia,tegra264-i2c"; + status = "disabled"; + reg = <0x0 0x0c600000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + dmas = <&gpcdma 3 3 TEGRA264_GPCDMA_SID_I2C2>; + dma-names = "tx"; + iommus = <&smmu1_mmu TEGRA264_GPCDMA_SID_I2C2>; + dma-coherent; + clocks = <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names = "div-clk, parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_I2C2>; + reset-names = "i2c"; + }; diff --git a/Documentation/devicetree/bindings/input/keyboard/gpio-keys.yaml b/Documentation/devicetree/bindings/input/keyboard/gpio-keys.yaml new file mode 100644 index 00000000..24288d2b --- /dev/null +++ b/Documentation/devicetree/bindings/input/keyboard/gpio-keys.yaml @@ -0,0 +1,58 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio-keys/gpio-keys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = gpio-keys is mentioned in the following drivers + - /kernel/kernel-oot/drivers/input/keyboard/gpio_keys.c + - /kernel/kernel-oot/drivers/input/keyboard/gpio_keys_polled.c + - /kernel/kernel-oot/drivers/input/misc/soc_button_array.c + - /kernel/kernel-oot/drivers/mfd/ucb1x00-assabet.c + - /kernel/kernel-oot/drivers/mfd/rohm-bd71828.c + - /kernel/kernel-oot/drivers/mfd/rohm-bd718x7.c + - /kernel/kernel-oot/drivers/platform/x86/barco-p50-gpio.c + - /kernel/kernel-oot/drivers/platform/x86/meraki-mx100.c + - /kernel/kernel-oot/drivers/platform/x86/pcengines-apuv2.c + - /kernel/kernel-oot/drivers/platform/x86/x86-android-tablets.c + + The following nodes use this compatibility + - /gpio-keys + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - gpio-keys + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + gpio-keys { + }; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp-hv.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp-hv.yaml new file mode 100644 index 00000000..d7240309 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp-hv.yaml @@ -0,0 +1,141 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-hsp@8800000/nvidia,tegra264-hsp-hv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-hsp-hv is mentioned in the following drivers + - /kernel/kernel-oot/drivers/mailbox/tegra-hsp.c + + The following nodes use this compatibility + - /bus@0/tegra-hsp@8800000 + - /bus@0/tegra-hsp@8c00000 + - /bus@0/tegra-hsp@8d00000 + - /bus@0/tegra-hsp@8189100000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-hsp-hv + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8800000 + maximum: 0x89100000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc0000 + maximum: 0xd0000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x19f + maximum: 0x2a5 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - doorbell + - shared0 + - shared1 + - shared2 + - shared3 + - shared4 + - shared5 + - shared6 + - shared7 + + + '#mbox-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + nvidia,mbox-ie: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + tegra-hsp@8800000 { + compatible = "nvidia,tegra264-hsp", + "nvidia,tegra234-hsp", + "nvidia,tegra186-hsp"; + status = "disabled"; + reg = <0x0 0x08800000 0x0 0xd0000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell, shared0, shared1, shared2", + "shared3", + "shared4, shared5, shared6, shared7"; + #mbox-cells = <2>; + nvidia,mbox-ie; + }; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp.yaml new file mode 100644 index 00000000..29d6e5aa --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra264-hsp.yaml @@ -0,0 +1,142 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-hsp@818c160000/nvidia,tegra264-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-hsp is mentioned in the following drivers + - /kernel/kernel-oot/drivers/mailbox/tegra-hsp.c + + The following nodes use this compatibility + - /bus@0/tegra-hsp@818c160000 + - /bus@0/tegra-hsp@8189200000 + +select: + properties: + compatible: + minItems: 3 + maxItems: 3 + items: + enum: + - nvidia,tegra264-hsp + - nvidia,tegra234-hsp + - nvidia,tegra186-hsp + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x89200000 + maximum: 0x8c160000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x90000 + maximum: 0xc0000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x190 + maximum: 0x1a6 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - shared0 + - shared1 + - shared2 + - shared3 + - shared4 + + + nvidia,num-SM: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + nvidia,num-SS: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,num-SI: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + + nvidia,mbox-ie: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#mbox-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + tegra-hsp@818c160000 { + compatible = "nvidia,tegra264-hsp"; + reg = <0x81 0x8c160000 0x0 0x00090000>; + interrupts = <0 400 0x04>; + interrupt-names = "shared0"; + nvidia,num-SM = <0x8>; + nvidia,num-SS = <0x4>; + nvidia,num-SI = <0x5>; + nvidia,mbox-ie; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/cam_fsync/nvidia,tegra264-cdi-tsc.yaml b/Documentation/devicetree/bindings/media/platform/tegra/cam_fsync/nvidia,tegra264-cdi-tsc.yaml new file mode 100644 index 00000000..97ed2f90 --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/cam_fsync/nvidia,tegra264-cdi-tsc.yaml @@ -0,0 +1,89 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tsc_sig_gen@c230000/nvidia,tegra264-cdi-tsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-cdi-tsc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/cam_fsync/cam_fsync.c + + The following nodes use this compatibility + - /tsc_sig_gen@c230000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-cdi-tsc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc230000 + maximum: 0xc230000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x18 + maximum: 0x18 + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + +required: + - compatible + - reg + +examples: + - | + tsc_sig_gen@c230000 { + compatible = "nvidia,tegra264-cam-cdi-tsc"; + ranges = <0x0 0x0 0xc230000 0x10000>; + reg = <0x0 0xc230000 0x0 0x18>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-isp.yaml b/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-isp.yaml new file mode 100644 index 00000000..b66839b5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-isp.yaml @@ -0,0 +1,67 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-capture-isp/nvidia,tegra-camrtc-capture-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-camrtc-capture-isp is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/camera/fusa-capture/capture-isp.c + + The following nodes use this compatibility + - /tegra-capture-isp + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-camrtc-capture-isp + + required: + - compatible + +properties: + + nvidia,isp-devices: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,isp-max-channels: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20 + maximum: 0x20 + +required: + - compatible + +examples: + - | + tegra-capture-isp { + compatible = "nvidia,tegra-camrtc-capture-isp"; + nvidia,isp-devices = <&isp &isp1>; + nvidia,isp-max-channels = <32>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-vi.yaml b/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-vi.yaml new file mode 100644 index 00000000..1173789c --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/camera/fusa-capture/nvidia,tegra-camrtc-capture-vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-capture-vi/nvidia,tegra-camrtc-capture-vi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-camrtc-capture-vi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/camera/fusa-capture/capture-vi.c + + The following nodes use this compatibility + - /tegra-capture-vi + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-camrtc-capture-vi + + required: + - compatible + +properties: + + nvidia,vi-devices: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,vi-mapping-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6 + maximum: 0x6 + + nvidia,vi-mapping: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x1 + + nvidia,vi-mapping-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - csi-stream-id + - vi-unit-id + + + nvidia,vi-max-channels: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x48 + maximum: 0x48 + +required: + - compatible + +examples: + - | + tegra-capture-vi { + compatible = "nvidia,tegra-camrtc-capture-vi"; + nvidia,vi-devices = <&vi0 &vi1>; + nvidia,vi-mapping-size = <6>; + nvidia,vi-mapping = <0 0>, + <1 0>, + <2 1>, + <3 1>, + <4 0>, + <5 1>; + nvidia,vi-mapping-names = "csi-stream-id, vi-unit-id"; + nvidia,vi-max-channels = <72>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cdi-mgr.yaml b/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cdi-mgr.yaml new file mode 100644 index 00000000..7e1a13da --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cdi-mgr.yaml @@ -0,0 +1,59 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sipl_devblk_7/nvidia,cdi-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,cdi-mgr is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/cdi/cdi_mgr.c + + The following nodes use this compatibility + - /sipl_devblk_7 + - /sipl_devblk_9 + - /sipl_devblk_0 + - /sipl_devblk_12 + - /sipl_devblk_1 + - /sipl_devblk_3 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,cdi-mgr + + required: + - compatible + +properties: + + pwdn-gpios: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5a + +required: + - compatible + +examples: + - | + sipl_devblk_7 { + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cim_ver.yaml b/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cim_ver.yaml new file mode 100644 index 00000000..58b02d8c --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/cdi/nvidia,cim_ver.yaml @@ -0,0 +1,62 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cim_ver/nvidia,cim_ver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,cim_ver is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/cdi/cdi_mgr.c + - /kernel/nvidia-oot/drivers/media/platform/tegra/cdi/cdi_dev.c + + The following nodes use this compatibility + - /cim_ver + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,cim_ver + + required: + - compatible + +properties: + + cim_ver: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - cim_ver_a02 + + + cim_frsync_src: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + +examples: + - | + cim_ver { + }; diff --git a/Documentation/devicetree/bindings/media/platform/tegra/isc/nvidia,isc-mgr.yaml b/Documentation/devicetree/bindings/media/platform/tegra/isc/nvidia,isc-mgr.yaml new file mode 100644 index 00000000..577ad459 --- /dev/null +++ b/Documentation/devicetree/bindings/media/platform/tegra/isc/nvidia,isc-mgr.yaml @@ -0,0 +1,91 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/isc-mgr.0/nvidia,isc-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,isc-mgr is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/media/platform/tegra/isc/isc_mgr.c + + The following nodes use this compatibility + - /isc-mgr.0 + - /isc-mgr.1 + - /isc-mgr.2 + - /isc-mgr.3 + - /isc-mgr.4 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,isc-mgr + + required: + - compatible + +properties: + + i2c-bus: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xc + + csi-port: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x6 + + cphy-map-trio0: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - A_B_C + + + cphy-map-trio1: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - C_A_B + + + cphy-map-trio2: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - A_B_C + + + cphy-map-trio3: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - C_A_B + + +required: + - compatible + +examples: + - | + isc-mgr.0 { + }; diff --git a/Documentation/devicetree/bindings/memory/tegra/nvidia,tegra264-emc.yaml b/Documentation/devicetree/bindings/memory/tegra/nvidia,tegra264-emc.yaml new file mode 100644 index 00000000..c69b310d --- /dev/null +++ b/Documentation/devicetree/bindings/memory/tegra/nvidia,tegra264-emc.yaml @@ -0,0 +1,144 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/external-memory-controller@8108800000/nvidia,tegra264-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-emc is mentioned in the following drivers + - /kernel/kernel-oot/drivers/memory/tegra/tegra186-emc.c + + The following nodes use this compatibility + - /bus@0/memory-controller@8108020000/external-memory-controller@8108800000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-emc + - nvidia,tegra234-emc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8800000 + maximum: 0x8890000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x20000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8d + maximum: 0x8d + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x122 + maximum: 0x122 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - emc + + + '#interconnect-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32" + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + external-memory-controller@8108800000 { + compatible = "nvidia,tegra264-emc", + "nvidia,tegra234-emc"; + status = "disabled"; + reg = <0x81 0x08800000 0x0 0x20000>, + <0x81 0x08890000 0x0 0x20000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_EMC>; + clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; + numa-node-id = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,t264-smmu-hwpm.yaml b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,t264-smmu-hwpm.yaml new file mode 100644 index 00000000..55d20658 --- /dev/null +++ b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,t264-smmu-hwpm.yaml @@ -0,0 +1,80 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/smmu-hwpm@810aa30000/nvidia,t264-smmu-hwpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,t264-smmu-hwpm is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/memory/tegra/private-soc/smmu-hwpm.c + + The following nodes use this compatibility + - /bus@0/smmu-hwpm@810aa30000 + - /bus@0/smmu-hwpm@8105a30000 + - /bus@0/smmu-hwpm@8106a30000 + - /bus@0/smmu-hwpm@8806a30000 + - /bus@0/smmu-hwpm@810ba30000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,t264-smmu-hwpm + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5a30000 + maximum: 0xba30000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + +required: + - compatible + - reg + +examples: + - | + smmu-hwpm@810aa30000 { + compatible = "nvidia,t264-smmu-hwpm"; + reg = <0x81 0x0aa30000 0x0 0x10000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mc-hwpm.yaml b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mc-hwpm.yaml new file mode 100644 index 00000000..35e16588 --- /dev/null +++ b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mc-hwpm.yaml @@ -0,0 +1,92 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controller-hwpm@8108020000/nvidia,tegra-t264-mc-hwpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-t264-mc-hwpm is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c + + The following nodes use this compatibility + - /bus@0/memory-controller-hwpm@8108020000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-t264-mc-hwpm + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8020000 + maximum: 0x8220000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x20000 + +required: + - compatible + - reg + +examples: + - | + memory-controller-hwpm@8108020000 { + compatible = "nvidia,tegra-t264-mc-hwpm"; + reg = <0x81 0x8020000 0x0 0x20000>, + <0x81 0x8040000 0x0 0x20000>, + <0x81 0x8060000 0x0 0x20000>, + <0x81 0x8080000 0x0 0x20000>, + <0x81 0x80a0000 0x0 0x20000>, + <0x81 0x80c0000 0x0 0x20000>, + <0x81 0x80e0000 0x0 0x20000>, + <0x81 0x8100000 0x0 0x20000>, + <0x81 0x8120000 0x0 0x20000>, + <0x81 0x8140000 0x0 0x20000>, + <0x81 0x8160000 0x0 0x20000>, + <0x81 0x8180000 0x0 0x20000>, + <0x81 0x81a0000 0x0 0x20000>, + <0x81 0x81c0000 0x0 0x20000>, + <0x81 0x81e0000 0x0 0x20000>, + <0x81 0x8200000 0x0 0x20000>, + <0x81 0x8220000 0x0 0x20000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mem-qual.yaml b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mem-qual.yaml new file mode 100644 index 00000000..98c73591 --- /dev/null +++ b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t264-mem-qual.yaml @@ -0,0 +1,102 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memqual@f020000/nvidia,tegra-t264-mem-qual.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-t264-mem-qual is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/memory/tegra/private-soc/mem-qual.c + + The following nodes use this compatibility + - /bus@0/memqual@f020000 + - /bus@0/memqual@a808730000 + - /bus@0/memqual@818d020000 + - /bus@0/memqual@a808750000 + - /bus@0/memqual@818d030000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-t264-mem-qual + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8730000 + maximum: 0x8d030000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x3f00 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - iommus + +examples: + - | + memqual@f020000 { + compatible = "nvidia,tegra-t264-mem-qual"; + status = "disabled"; + reg = <0x0 0x0f020000 0x0 0x10000>; + iommus = <&smmu1_mmu TEGRA_SID_MIU0>, + <&smmu1_mmu TEGRA_SID_MIU1>; + dma-coherent; + }; diff --git a/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t26x-mc.yaml b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t26x-mc.yaml new file mode 100644 index 00000000..2d13cedb --- /dev/null +++ b/Documentation/devicetree/bindings/memory/tegra/private-soc/nvidia,tegra-t26x-mc.yaml @@ -0,0 +1,76 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mc_carveout@8108020000/nvidia,tegra-t26x-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-t26x-mc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/memory/tegra/private-soc/mc-t26x.c + + The following nodes use this compatibility + - /bus@0/mc_carveout@8108020000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-t26x-mc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8020000 + maximum: 0x8020000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x20000 + +required: + - compatible + - reg + +examples: + - | + mc_carveout@8108020000 { + compatible = "nvidia,tegra-t26x-mc"; + reg = <0x81 0x08020000 0x0 0x20000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/mfd/cache.yaml b/Documentation/devicetree/bindings/mfd/cache.yaml new file mode 100644 index 00000000..1fb22f2f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/cache.yaml @@ -0,0 +1,260 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/l2-cache-0/cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = cache is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/mfd/nvidia-vrs-pseq.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_xmit_shortcut.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_ap.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_fsm_wnm.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_mlme_ext.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_sec_cam.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_xmit.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_sta_mgt.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_wow.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_recv_shortcut.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_wnm.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_recv.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/rtw_mlme.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/core/mesh/rtw_mesh.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_xmit_shortcut.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_recv.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/drv_types.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/ieee80211.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_mlme_ext.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_wnm.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_mlme.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_sec_cam.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/rtw_xmit.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/include/sta_info.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_rx_agg.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/pltfm_ops_windows.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_types.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_trx_def.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_tx.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_config.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/pltfm_ops_linux.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_rx.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/pltfm_ops_none.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/pltfm_ops_macos.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_api_drv.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/pltfm_ops_uefi.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_init.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/phl_def.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hci/phl_trx_def_pcie.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hci/phl_trx_pcie.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/test/trx_test.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/test/trx_test.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hal_g6/rtl8852c/hal_trx_8852c.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hal_g6/rtl8852c/pci/hal_trx_8852ce.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hal_g6/mac/mac_def.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hal_g6/mac/mac_exp_def.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/phl/hal_g6/mac/mac_ax/wowlan.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/rtw_cfg.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/ioctl_cfg80211.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/rtw_proc.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/rtw_cfgvendor.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/rhashtable.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/os_dep/linux/pci_intf.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/platform/platform_mips_98d_pci.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/platform/platform_ops.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8852ce/platform/platform_linux_pc_pci.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_wlan_util.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_ap.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_mlme_ext.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_pwrctrl.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_sta_mgt.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_debug.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_wnm.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_recv.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/rtw_mlme.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/core/mesh/rtw_mesh.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/hal_com_h2c.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_recv.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/drv_types.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/hal_com.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/ieee80211.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_debug.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_mlme_ext.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_wnm.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_mlme.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_pwrctrl.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/include/rtw_xmit.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/os_dep/linux/rtw_proc.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/os_dep/linux/rtw_cfgvendor.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/os_dep/linux/rhashtable.h + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/os_dep/linux/pci_intf.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/os_dep/linux/os_intfs.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/hal/hal_com.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/hal/hal_halmac.c + - /kernel/nvidia-oot/drivers/net/wireless/realtek/rtl8822ce/hal/rtl8822c/pci/rtl8822ce_xmit.c + - /kernel/nvidia-oot/drivers/net/ethernet/mft/mst_backward_compatibility/mst_pci/mst_pci_bc.c + - /kernel/nvidia-oot/drivers/block/tegra_virt_storage/tegra_hv_vblk.c + - /kernel/nvidia-oot/drivers/block/tegra_virt_storage/tegra_hv_scsi.c + - /kernel/nvidia-oot/drivers/firmware/tegra/ivc_ext.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx274.c + - /kernel/nvidia-oot/drivers/media/i2c/lt6911uxc.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx390_archived.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx318.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx185.c + - /kernel/nvidia-oot/drivers/media/i2c/pca9570.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_hawk_owl.c + - /kernel/nvidia-oot/drivers/media/i2c/max9295.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_ar0234.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx477.c + - /kernel/nvidia-oot/drivers/media/i2c/max929x.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx390.c + - /kernel/nvidia-oot/drivers/media/i2c/max9296.c + - /kernel/nvidia-oot/drivers/media/i2c/max96712.c + - /kernel/nvidia-oot/drivers/media/i2c/nv_imx219.c + - /kernel/nvidia-oot/drivers/media/platform/tegra/camera/fusa-capture/capture-isp.c + - /kernel/nvidia-oot/drivers/media/platform/tegra/camera/fusa-capture/capture-common.c + - /kernel/nvidia-oot/drivers/i2c/busses/i2c-nvvrs11.c + - /kernel/nvidia-oot/drivers/bluetooth/realtek/rtk_misc.c + - /kernel/nvidia-oot/drivers/bluetooth/realtek/rtk_bt.c + - /kernel/nvidia-oot/drivers/bluetooth/realtek/rtk_coex.c + - /kernel/nvidia-oot/drivers/rtc/rtc-max77851.c + - /kernel/nvidia-oot/drivers/virt/tegra/tegra_hv.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/plane.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/nvjpg.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/nvdec.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/nvenc.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/gem.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/drm.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/vic.c + - /kernel/nvidia-oot/drivers/gpu/drm/tegra/include/uapi/drm/tegra_drm_next.h + - /kernel/nvidia-oot/drivers/gpu/host1x/syncpt.c + - /kernel/nvidia-oot/drivers/gpu/host1x/cdma.c + - /kernel/nvidia-oot/drivers/gpu/host1x/bus.c + - /kernel/nvidia-oot/drivers/gpu/host1x/dev.h + - /kernel/nvidia-oot/drivers/gpu/host1x/dev.c + - /kernel/nvidia-oot/drivers/gpu/host1x/include/linux/host1x-next.h + - /kernel/nvidia-oot/drivers/gpu/host1x/hw/syncpt_hw.c + - /kernel/nvidia-oot/drivers/gpu/host1x-emu/syncpt.c + - /kernel/nvidia-oot/drivers/gpu/host1x-emu/hw/syncpt_hw.c + - /kernel/nvidia-oot/drivers/video/tegra/host/nvdla/dla_os_interface.h + - /kernel/nvidia-oot/drivers/video/tegra/host/pva/pva_vpu_exe.c + - /kernel/nvidia-oot/drivers/video/tegra/host/pva/fw_include/pva-task.h + - /kernel/nvidia-oot/drivers/video/tegra/host/pva/fw_include/pva-ucode-header.h + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_fault.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_alloc.h + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_alloc.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_dev_int.h + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_cache.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_ioctl.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_heap.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_handle.h + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_pp.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_dmabuf.c + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_alloc_int.h + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_dev.c + - /kernel/nvidia-oot/drivers/video/tegra/tsec/tsec_boot.c + - /kernel/nvidia-oot/drivers/video/tegra/tsec/tsec_linux.h + - /kernel/nvidia-oot/drivers/video/tegra/tsec/tsec_cmds.h + - /kernel/nvidia-oot/drivers/video/tegra/tsec/tsec_comms/tsec_comms.c + - /kernel/nvidia-oot/drivers/video/tegra/virt/tegra_gr_comm.c + - /kernel/nvidia-oot/drivers/platform/tegra/dce/dce-debug-perf.c + - /kernel/nvidia-oot/drivers/platform/tegra/dce/include/interface/dce-admin-perf-stats.h + - /kernel/nvidia-oot/drivers/platform/tegra/dce/include/interface/dce-interface.h + - /kernel/nvidia-oot/drivers/platform/tegra/uncore_pmu/tegra23x_perf_uncore.c + - /kernel/nvidia-oot/drivers/platform/tegra/aon/tegra-ivc.c + - /kernel/nvidia-oot/drivers/platform/tegra/aon/tegra-aon-mail.c + - /kernel/nvidia-oot/drivers/platform/tegra/mce/mce.c + - /kernel/nvidia-oot/drivers/platform/tegra/mce/tegra23x-mce.c + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/tegra-rtcpu-trace.c + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/camchar.c + - /kernel/nvidia-oot/drivers/platform/tegra/nvadsp/dev-t18x.c + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/stream-extensions.c + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/iova-alloc.h + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/pci-client.c + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/iova-alloc.c + - /kernel/nvidia-oot/drivers/misc/mods/mods_clock.c + - /kernel/nvidia-oot/drivers/misc/mods/mods_krnl.c + - /kernel/nvidia-oot/drivers/misc/mods/mods_internal.h + - /kernel/nvidia-oot/drivers/misc/mods/mods_mem.c + - /kernel/nvidia-oot/drivers/misc/mods/mods_pci.c + + The following nodes use this compatibility + - /cpus/l2-cache-0 + - /cpus/l2-cache-1 + - /cpus/l2-cache-2 + - /cpus/l2-cache-3 + - /cpus/l2-cache-4 + - /cpus/l2-cache-5 + - /cpus/l2-cache-6 + - /cpus/l2-cache-7 + - /cpus/l2-cache-8 + - /cpus/l2-cache-9 + - /cpus/l2-cache-10 + - /cpus/l2-cache-11 + - /cpus/l2-cache-12 + - /cpus/l2-cache-13 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - cache + + required: + - compatible + +properties: + + cache-level: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + cache-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100000 + maximum: 0x100000 + + cache-line-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + + cache-sets: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800 + maximum: 0x800 + + cache-unified: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + +examples: + - | + l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; diff --git a/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml new file mode 100644 index 00000000..34a0f9dc --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml @@ -0,0 +1,101 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vrs@3c/nvidia,vrs-pseq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,vrs-pseq is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/mfd/nvidia-vrs-pseq.c + + The following nodes use this compatibility + - /bpmp/i2c/vrs@3c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,vrs-pseq + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3c + maximum: 0x3c + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - reg + - interrupts + +examples: + - | + vrs@3c { + compatible = "nvidia,vrs-pseq"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/arm,armv8-pmuv3.yaml b/Documentation/devicetree/bindings/misc/arm,armv8-pmuv3.yaml new file mode 100644 index 00000000..764505bf --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,armv8-pmuv3.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmu/arm,armv8-pmuv3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,armv8-pmuv3 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /pmu + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,armv8-pmuv3 + + required: + - compatible + +properties: + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + +required: + - compatible + - interrupts + +examples: + - | + pmu { + compatible = "arm,armv8-pmuv3"; + status = "disabled"; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-funnel.yaml new file mode 100644 index 00000000..a56fdfc3 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-funnel.yaml @@ -0,0 +1,103 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/funnel_major@10080000/arm,coresight-dynamic-funnel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,coresight-dynamic-funnel is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /funnel_major@10080000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,coresight-dynamic-funnel + - arm,primecell + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10080000 + maximum: 0x10080000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xcb + maximum: 0xcb + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - apb_pclk + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + funnel_major@10080000 { + compatible = "arm,coresight-dynamic-funnel, arm,primecell"; + status = "disabled"; + reg = <0x0 0x10080000 0x0 0x1000>; + clocks = <&bpmp TEGRA264_CLK_HCSITE>; + clock-names = "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-replicator.yaml new file mode 100644 index 00000000..85d1d2a6 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,coresight-dynamic-replicator.yaml @@ -0,0 +1,103 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/replicator_soc@10060000/arm,coresight-dynamic-replicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,coresight-dynamic-replicator is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /replicator_soc@10060000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,coresight-dynamic-replicator + - arm,primecell + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10060000 + maximum: 0x10060000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xcb + maximum: 0xcb + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - apb_pclk + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + replicator_soc@10060000 { + compatible = "arm,coresight-dynamic-replicator, arm,primecell"; + status = "disabled"; + reg = <0x0 0x10060000 0x0 0x1000>; + clocks = <&bpmp TEGRA264_CLK_HCSITE>; + clock-names = "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/misc/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/misc/arm,coresight-stm.yaml new file mode 100644 index 00000000..3bc2ce78 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,coresight-stm.yaml @@ -0,0 +1,113 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/stm@10070000/arm,coresight-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,coresight-stm is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /stm@10070000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,coresight-stm + - arm,primecell + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10070000 + maximum: 0x11000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - stm-base + - stm-stimulus-base + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xca + maximum: 0xca + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - apb_pclk + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + stm@10070000 { + compatible = "arm,coresight-stm, arm,primecell"; + status = "disabled"; + reg = <0x0 0x10070000 0x0 0x1000>, + <0x0 0x11000000 0x0 0x1000000>; + reg-names = "stm-base, stm-stimulus-base"; + clocks = <&bpmp TEGRA264_CLK_CSITE>; + clock-names = "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/misc/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/misc/arm,coresight-tmc.yaml new file mode 100644 index 00000000..6d6fc5ae --- /dev/null +++ b/Documentation/devicetree/bindings/misc/arm,coresight-tmc.yaml @@ -0,0 +1,124 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/etf_soc@10040000/arm,coresight-tmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,coresight-tmc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /etf_soc@10040000 + - /etr_soc@10050000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,coresight-tmc + - arm,primecell + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10040000 + maximum: 0x10050000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + coresight-default-sink: + $ref: "/schemas/types.yaml#/definitions/flag" + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xcb + maximum: 0xcb + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - apb_pclk + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x300 + maximum: 0x300 + +required: + - compatible + - reg + - clocks + - clock-names + - iommus + +examples: + - | + etf_soc@10040000 { + compatible = "arm,coresight-tmc, arm,primecell"; + status = "disabled"; + reg = <0x0 0x10040000 0x0 0x1000>; + coresight-default-sink; + clocks = <&bpmp TEGRA264_CLK_HCSITE>; + clock-names = "apb_pclk"; + }; diff --git a/Documentation/devicetree/bindings/misc/mods/nvidia,mods_smmu.yaml b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_smmu.yaml new file mode 100644 index 00000000..9c5da88b --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_smmu.yaml @@ -0,0 +1,187 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mods_pcie0/nvidia,mods_smmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,mods_smmu is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/mods/mods_smmu_drv.c + + The following nodes use this compatibility + - /mods_pcie0 + - /mods_pcie1 + - /mods_pcie2 + - /mods_pcie3 + - /mods_pcie4 + - /mods_pcie5 + - /mods_isp0 + - /mods_isp2 + - /mods_i2c0 + - /mods_i2c1 + - /mods_i2c2 + - /mods_i2c3 + - /mods_i2c7 + - /mods_i2c9 + - /mods_i2c11 + - /mods_i2c12 + - /mods_i2c14 + - /mods_i2c15 + - /mods_i2c16 + - /mods_spi1 + - /mods_spi2 + - /mods_spi3 + - /mods_spi4 + - /mods_spi5 + - /mods_uart4 + - /mods_uart5 + - /mods_uart9 + - /mods_uart10 + - /mods_vi0 + - /mods_vi1 + - /mods_sdmmc1 + - /mods_ufs + - /mods_xhci + - /mods_xusb + - /mods_dma + - /mods_se + - /mods_seu1 + - /mods_seu2 + - /mods_seu3 + - /mods_qspi0_dma + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,mods_smmu + + required: + - compatible + +properties: + + iommu-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x50000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + dev-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - mods_pcie0 + - mods_pcie1 + - mods_pcie2 + - mods_pcie3 + - mods_pcie4 + - mods_pcie5 + - mods_isp0 + - mods_isp2 + - mods_i2c0 + - mods_i2c1 + - mods_i2c2 + - mods_i2c3 + - mods_i2c7 + - mods_i2c9 + - mods_i2c11 + - mods_i2c12 + - mods_i2c14 + - mods_i2c15 + - mods_i2c16 + - mods_spi1 + - mods_spi2 + - mods_spi3 + - mods_spi4 + - mods_spi5 + - mods_uart4 + - mods_uart5 + - mods_uart9 + - mods_uart10 + - mods_vi0 + - mods_vi1 + - mods_sdmmc1 + - mods_ufs + - mods_xhci + - mods_xusb + - mods_dma + - mods_se + - mods_seu1 + - mods_seu2 + - mods_seu3 + - mods_qspi0_dma + + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800 + maximum: 0x50000 + +required: + - compatible + - iommus + +examples: + - | + mods_pcie0 { + compatible = "nvidia,mods_smmu"; + iommu-map = <0x0 &smmu2_mmu 0x10000 0x10000>; + dma-coherent; + dev-names = "mods_pcie0"; + status = "disabled"; + nvidia,bpmp = <&bpmp 0x0>; + }; diff --git a/Documentation/devicetree/bindings/misc/mods/nvidia,mods_tegra_dma.yaml b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_tegra_dma.yaml new file mode 100644 index 00000000..c697b06a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_tegra_dma.yaml @@ -0,0 +1,133 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mods_tegra_dma/nvidia,mods_tegra_dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,mods_tegra_dma is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/mods/mods_dma.c + + The following nodes use this compatibility + - /mods_tegra_dma + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,mods_tegra_dma + + required: + - compatible + +properties: + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x14 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1f + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x801 + maximum: 0x81f + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - i2c0_tx + - i2c1_tx + - i2c2_tx + - i2c3_tx + - i2c7_tx + - i2c9_tx + - i2c11_tx + - i2c12_tx + - i2c14_tx + - i2c15_tx + - i2c16_tx + - spi1_rx + - spi1_tx + - spi2_rx + - spi2_tx + - spi3_rx + - spi3_tx + - spi4_rx + - spi4_tx + - spi5_rx + - spi5_tx + - uart4_rx + - uart4_tx + - uart5_rx + - uart5_tx + - uart9_rx + - uart9_tx + - uart10_rx + - uart10_tx + + +required: + - compatible + +examples: + - | + mods_tegra_dma { + compatible = "nvidia,mods_tegra_dma"; + dmas = <&gpcdma 0 31 TEGRA264_GPCDMA_SID_I2C0>, + < &gpcdma 7 7 TEGRA264_GPCDMA_SID_I2C1>, + < &gpcdma 3 3 TEGRA264_GPCDMA_SID_I2C2>, + < &gpcdma 4 4 TEGRA264_GPCDMA_SID_I2C3>, + < &gpcdma 6 6 TEGRA264_GPCDMA_SID_I2C7>, + < &gpcdma 2 2 TEGRA264_GPCDMA_SID_I2C9>, + < &gpcdma 1 1 TEGRA264_GPCDMA_SID_I2C11>, + < &gpcdma 5 5 TEGRA264_GPCDMA_SID_I2C12>, + < &gpcdma 18 28 TEGRA264_GPCDMA_SID_I2C14>, + < &gpcdma 19 29 TEGRA264_GPCDMA_SID_I2C15>, + < &gpcdma 20 30 TEGRA264_GPCDMA_SID_I2C16>, + < &gpcdma 9 9 TEGRA264_GPCDMA_SID_SPI1>, + < &gpcdma 9 19 TEGRA264_GPCDMA_SID_SPI1>, + < &gpcdma 8 8 TEGRA264_GPCDMA_SID_SPI2>, + < &gpcdma 8 18 TEGRA264_GPCDMA_SID_SPI2>, + < &gpcdma 14 14 TEGRA264_GPCDMA_SID_SPI3>, + < &gpcdma 14 24 TEGRA264_GPCDMA_SID_SPI3>, + < &gpcdma 15 15 TEGRA264_GPCDMA_SID_SPI4>, + < &gpcdma 15 25 TEGRA264_GPCDMA_SID_SPI4>, + < &gpcdma 16 16 TEGRA264_GPCDMA_SID_SPI5>, + < &gpcdma 16 26 TEGRA264_GPCDMA_SID_SPI5>, + < &gpcdma 13 23 TEGRA264_GPCDMA_SID_UART4>, + < &gpcdma 13 13 TEGRA264_GPCDMA_SID_UART4>, + < &gpcdma 11 11 TEGRA264_GPCDMA_SID_UART5>, + < &gpcdma 11 21 TEGRA264_GPCDMA_SID_UART5>, + < &gpcdma 10 10 TEGRA264_GPCDMA_SID_UART9>, + < &gpcdma 10 20 TEGRA264_GPCDMA_SID_UART9>, + < &gpcdma 12 12 TEGRA264_GPCDMA_SID_UART10>, + < &gpcdma 12 22 TEGRA264_GPCDMA_SID_UART10>; + dma-names = "i2c0_tx, i2c1_tx, i2c2_tx, i2c3_tx, i2c7_tx, i2c9_tx, i2c11_tx, i2c12_tx, i2c14_tx, i2c15_tx, i2c16_tx, spi1_rx, spi1_tx, spi2_rx, spi2_tx, spi3_rx, spi3_tx, spi4_rx, spi4_tx, spi5_rx, spi5_tx, uart4_rx, uart4_tx, uart5_rx, uart5_tx, uart9_rx, uart9_tx, uart10_rx, uart10_tx"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/mods/nvidia,mods_test.yaml b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_test.yaml new file mode 100644 index 00000000..304e19fc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mods/nvidia,mods_test.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mods_test/nvidia,mods_test.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,mods_test is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/mods/mods_dmabuf.c + + The following nodes use this compatibility + - /mods_test + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,mods_test + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + mods_test { + compatible = "nvidia,mods_test"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/mods/simple-bus.yaml b/Documentation/devicetree/bindings/misc/mods/simple-bus.yaml new file mode 100644 index 00000000..a5d67268 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mods/simple-bus.yaml @@ -0,0 +1,71 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus@0/simple-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = simple-bus is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/mods/mods_clock.c + + The following nodes use this compatibility + - /bus@0 + - /mods-simple-bus + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - simple-bus + + required: + - compatible + +properties: + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x2 + + device_type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - mods-simple-bus + + +required: + - compatible + +examples: + - | + bus@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,csi-isp-map-config.yaml b/Documentation/devicetree/bindings/misc/nvidia,csi-isp-map-config.yaml new file mode 100644 index 00000000..7b02a5ba --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,csi-isp-map-config.yaml @@ -0,0 +1,70 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-isp-map/nvidia,csi-isp-map-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,csi-isp-map-config is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /tegra-isp-map + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,csi-isp-map-config + + required: + - compatible + +properties: + + nvidia,isp-mapping: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x1 + +required: + - compatible + +examples: + - | + tegra-isp-map { + compatible = "nvidia,csi-isp-map-config"; + nvidia,isp-mapping = <0 0>, + <1 0>, + <2 1>, + <3 1>, + <4 0>, + <5 1>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,dulink-connection.yaml b/Documentation/devicetree/bindings/misc/nvidia,dulink-connection.yaml new file mode 100644 index 00000000..7234cf8c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,dulink-connection.yaml @@ -0,0 +1,125 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bootmgr/nvidia,dulink-connection.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,dulink-connection is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /chosen/driveupdate/bootmgr + - /chosen/driveupdate/bhc + - /chosen/driveupdate/decomp + - /chosen/driveupdate/du-client + - /chosen/driveupdate/content + - /chosen/driveupdate/master + - /chosen/driveupdate/tii + - /chosen/driveupdate/ctx_store + - /chosen/driveupdate/auth + - /chosen/driveupdate/dushell + - /chosen/driveupdate/plugin + - /chosen/driveupdate/ddu + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,dulink-connection + + required: + - compatible + +properties: + + remote-path: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - /bootmgr + - /bhc + - /decomp + - /du-client + - /content + - /master + - /tii + - /ctx_store + - /auth + - /dushell + - /plugin + - /ddu + + + type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - DOWNLINK + + + tr-type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - NVSCI + - TCP + + + tr-params: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvdu_gos_ipc_a_0 + - nvdu_gos_ipc_a_1 + - nvdu_gos_ipc_b_0 + - nvdu_gos_ipc_b_1 + - nvdu_gos_ipc_c_0 + - nvdu_gos_ipc_c_1 + - nvdu_gos_ipc_d_0 + - nvdu_gos_ipc_d_1 + - nvdu_gos_ipc_e_0 + - nvdu_gos_ipc_e_1 + - nvdu_gos_ipc_l_0 + - nvdu_gos_ipc_l_1 + - nvdu_gos_ipc_j_0 + - nvdu_gos_ipc_j_1 + - nvdu_gos_ipc_k_0 + - nvdu_gos_ipc_k_1 + - nvdu_gos_ipc_m_0 + - nvdu_gos_ipc_m_1 + - nvdu_gos_ipc_f_0 + - nvdu_gos_ipc_f_1 + - nvdu_gos_ipc_g_0 + - nvdu_gos_ipc_g_1 + - TCP_SERVER + - 0.0.0.0 + - 4455 + - 0 + + +required: + - compatible + +examples: + - | + bootmgr { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,fsi-carveout.yaml b/Documentation/devicetree/bindings/misc/nvidia,fsi-carveout.yaml new file mode 100644 index 00000000..65d9b251 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,fsi-carveout.yaml @@ -0,0 +1,103 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi-carveout/nvidia,fsi-carveout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,fsi-carveout is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /reserved-memory/fsi-carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,fsi-carveout + + required: + - compatible + +properties: + + size: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000000 + maximum: 0x2000000 + + alignment: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + no-map: + $ref: "/schemas/types.yaml#/definitions/flag" + + alloc-ranges: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + +examples: + - | + fsi-carveout { + compatible = "nvidia,fsi-carveout"; + status = "disabled"; + size = <0 0x2000000>; + alignment = <0 0x1000>; + no-map; + alloc-ranges = <0x0 0x0 0x1 0x0>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,generic_carveout.yaml b/Documentation/devicetree/bindings/misc/nvidia,generic_carveout.yaml new file mode 100644 index 00000000..210d5ace --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,generic_carveout.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/generic_carveout/nvidia,generic_carveout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,generic_carveout is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /reserved-memory/generic_carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,generic_carveout + + required: + - compatible + +properties: + + size: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000000 + maximum: 0x40000000 + + alignment: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x200000 + maximum: 0x200000 + + no-map: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + +examples: + - | + generic_carveout { + compatible = "nvidia,generic_carveout"; + status = "disabled"; + size = <0 0x40000000>; + alignment = <0 0x200000>; + no-map; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,mods-clocks.yaml b/Documentation/devicetree/bindings/misc/nvidia,mods-clocks.yaml new file mode 100644 index 00000000..7c6ed7dc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,mods-clocks.yaml @@ -0,0 +1,1693 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mods-clocks/nvidia,mods-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,mods-clocks is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /mods-simple-bus/mods-clocks + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,mods-clocks + + required: + - compatible + +properties: + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1d3 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - osc + - clk_s + - jtag_reg + - spll + - spll_out0 + - spll_out1 + - spll_out2 + - spll_out3 + - spll_out4 + - spll_out5 + - spll_out6 + - spll_out7 + - aon_i2c + - host1x + - isp + - isp1 + - isp_root + - nafll_pva0_core + - nafll_pva0_vps + - nvcsi + - nvcsilp + - pllp_out0 + - pva0_cpu_axi + - pva0_vps + - pwm10 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm9 + - qspi0 + - qspi0_2x_pm + - rce1_cpu + - rce1_nic + - rce_cpu + - rce_nic + - se + - seu1 + - seu2 + - seu3 + - se_root + - spi1 + - spi2 + - spi3 + - spi4 + - spi5 + - top_i2c + - tsec + - tsec_pka + - uart0 + - uart10 + - uart11 + - uart4 + - uart5 + - uart8 + - uart9 + - vi + - vi1 + - vic + - vi_root + - disppll + - sppll0 + - sppll0_clkout1a + - sppll0_clkout2a + - sppll1 + - vpll0 + - vpll1 + - vpll2 + - vpll3 + - vpll4 + - vpll5 + - vpll6 + - vpll7 + - rg0_div + - rg1_div + - rg2_div + - rg3_div + - rg4_div + - rg5_div + - rg6_div + - rg7_div + - rg0 + - rg1 + - rg2 + - rg3 + - rg4 + - rg5 + - rg6 + - rg7 + - disp + - dsc + - dsc_root + - hub + - vpllx_sor0_muxed + - vpllx_sor1_muxed + - vpllx_sor2_muxed + - vpllx_sor3_muxed + - linka_sym + - linkb_sym + - linkc_sym + - linkd_sym + - pre_sor0 + - pre_sor1 + - pre_sor2 + - pre_sor3 + - sor0_pll_ref + - sor1_pll_ref + - sor2_pll_ref + - sor3_pll_ref + - sor0_pad + - sor1_pad + - sor2_pad + - sor3_pad + - sor0_ref + - sor1_ref + - sor2_ref + - sor3_ref + - sor0_div + - sor1_div + - sor2_div + - sor3_div + - sor0 + - sor1 + - sor2 + - sor3 + - sf0_sor + - sf1_sor + - sf2_sor + - sf3_sor + - sf4_sor + - sf5_sor + - sf6_sor + - sf7_sor + - sf0 + - sf1 + - sf2 + - sf3 + - sf4 + - sf5 + - sf6 + - sf7 + - maud + - aza_2xbit + - dce_cpu + - dce_nic + - pllc4 + - pllc4_out0 + - pllc4_out1 + - pllc4_muxed + - sdmmc1 + - sdmmc_legacy_tm + - pllc0 + - nafll_bpmp + - pllp_out_pdiv + - disp_root + - adsp + - plla + - plla1 + - plla1_out1 + - pllaon + - pllaon_ape + - plla_out0 + - ahub + - ape + - i2s1_sclk_in + - i2s2_sclk_in + - i2s3_sclk_in + - i2s4_sclk_in + - i2s5_sclk_in + - i2s6_sclk_in + - i2s7_sclk_in + - i2s8_sclk_in + - i2s9_sclk_in + - i2s1_audio_sync + - i2s2_audio_sync + - i2s3_audio_sync + - i2s4_audio_sync + - i2s5_audio_sync + - i2s6_audio_sync + - i2s7_audio_sync + - i2s8_audio_sync + - dmic1_audio_sync + - dspk1_audio_sync + - i2s1 + - i2s2 + - i2s3 + - i2s4 + - i2s5 + - i2s6 + - i2s7 + - i2s8 + - i2s9 + - dmic1 + - dmic5 + - dspk1 + - aon_cpu + - aon_nic + - bpmp + - axi_cbb + - fuse + - tsense + - csite + - hcsite + - dbgapb + - la + - pllrefgp + - plle0 + - uphy0_pll0_xdig + - eqos_app + - eqos_mac + - eqos_macsec + - eqos_tx_pcs + - mgbes_ptp_ref + - mgbe0_uphy1_pll_xdig + - mgbe0_tx_pcs + - mgbe0_mac + - mgbe0_macsec + - mgbe0_app + - mgbe1_uphy1_pll_xdig + - mgbe1_tx_pcs + - mgbe1_mac + - mgbe1_macsec + - mgbe1_app + - mgbe2_uphy1_pll_xdig + - mgbe2_tx_pcs + - mgbe2_mac + - mgbe2_macsec + - mgbe2_app + - mgbe3_uphy1_pll_xdig + - mgbe3_tx_pcs + - mgbe3_mac + - mgbe3_macsec + - mgbe3_app + - pllrefufs + - pllrefufs_clkout624 + - pllrefufs_refclkout + - pllrefufs_ufsdev_refclkout + - ufshc_cg_sys + - mphy_l0_rx_ls_bit_div + - mphy_l0_rx_ls_bit + - mphy_l0_rx_ls_symb_div + - mphy_l0_rx_hs_symb_div + - mphy_l0_rx_symb + - mphy_l0_uphy_tx_fifo + - mphy_l0_tx_ls_3xbit_div + - mphy_l0_tx_ls_symb_div + - uphy0_pll4_xdig + - mphy_l0_tx_hs_symb_div + - mphy_l0_tx_symb + - mphy_l0_tx_ls_3xbit + - mphy_l0_rx_ana + - mphy_l1_rx_ana + - mphy_tx_1mhz_ref + - mphy_core_pll_fixed + - mphy_iobist + - ufshc_cg_sys_div + - xusb1_core + - xusb1_falcon + - xusb1_fs + - xusb1_ss + - uphy0_usb_p0_rx_core + - uphy0_usb_p1_rx_core + - uphy0_usb_p2_rx_core + - uphy0_usb_p3_rx_core + - xusb1_clk480m_nvwrap_core + - xusb1_core_host + - xusb1_core_dev + - xusb1_core_superspeed + - xusb1_falcon_host + - xusb1_falcon_superspeed + - xusb1_fs_host + - xusb1_fs_dev + - xusb1_hs_hsicp + - xusb1_ss_dev + - xusb1_ss_superspeed + - aon_touch + - aud_mclk + - extperiph1 + - extperiph2 + - extperiph3 + - extperiph4 + - jtag_reg_ungated + - ist_bus + - ist_bus_rist_mcc + - maths_sec_rist + - nafll_ist + - rist_root + - ist_controller_rist + - mss_encrypt + - emc + - sppll0_clkout100 + - sppll0_clkout270 + - sppll1_clkout100 + - sppll1_clkout270 + - dp_linka_ref + - dp_linkb_ref + - dp_linkc_ref + - dp_linkd_ref + - pllnvcsi + - pllbpmpcam + - utmi_pll1 + - utmi_pll1_clkout48 + - utmi_pll1_clkout60 + - utmi_pll1_clkout480 + - nafll_isp + - nafll_rce + - nafll_rce1 + - nafll_se + - nafll_vi + - nafll_vic + - nafll_dce + - nafll_tsec + - nafll_cpair0 + - nafll_cpair1 + - nafll_cpair2 + - nafll_cpair3 + - nafll_cpair4 + - nafll_cpair5 + - nafll_cpair6 + - nafll_gpu_sys + - nafll_gpu_nvd + - nafll_gpu_uproc + - nafll_gpu_gpc0 + - nafll_gpu_gpc1 + - nafll_gpu_gpc2 + - sor_linka_input + - sor_linkb_input + - sor_linkc_input + - sor_linkd_input + - sor_linka_afifo + - sor_linkb_afifo + - sor_linkc_afifo + - sor_linkd_afifo + - i2s1_pad_m + - i2s2_pad_m + - i2s3_pad_m + - i2s4_pad_m + - i2s5_pad_m + - i2s6_pad_m + - i2s7_pad_m + - i2s8_pad_m + - i2s9_pad_m + - bpmp_nic + - clk1m + - rdet + - adc_soc_ref + - uphy0_pll0_txref + - eqos_tx + - eqos_tx_m + - eqos_rx_pcs_in + - eqos_rx_pcs_m + - eqos_rx_in + - eqos_rx + - eqos_rx_m + - mgbe0_uphy1_pll_txref + - mgbe0_tx + - mgbe0_tx_m + - mgbe0_rx_pcs_in + - mgbe0_rx_pcs_m + - mgbe0_rx_in + - mgbe0_rx_m + - mgbe1_uphy1_pll_txref + - mgbe1_tx + - mgbe1_tx_m + - mgbe1_rx_pcs_in + - mgbe1_rx_pcs_m + - mgbe1_rx_in + - mgbe1_rx_m + - mgbe2_uphy1_pll_txref + - mgbe2_tx + - mgbe2_tx_m + - mgbe2_rx_pcs_in + - mgbe2_rx_pcs_m + - mgbe2_rx_in + - mgbe2_rx_m + - mgbe3_uphy1_pll_txref + - mgbe3_tx + - mgbe3_tx_m + - mgbe3_rx_pcs_in + - mgbe3_rx_pcs_m + - mgbe3_rx_in + - mgbe3_rx_m + - uphy0_usb_p0_tx_core + - uphy0_usb_p1_tx_core + - uphy0_usb_p2_tx_core + - uphy0_usb_p3_tx_core + - uphy0_usb_p0_tx + - uphy0_usb_p1_tx + - uphy0_usb_p2_tx + - uphy0_usb_p3_tx + - uphy0_usb_p0_rx_in + - uphy0_usb_p1_rx_in + - uphy0_usb_p2_rx_in + - uphy0_usb_p3_rx_in + - uphy0_usb_p0_rx_m + - uphy0_usb_p1_rx_m + - uphy0_usb_p2_rx_m + - uphy0_usb_p3_rx_m + - uphy0_lane0_tx_m + - pcie_c1_xclk_nobg_m + - pcie_c2_xclk_nobg_m + - pcie_c3_xclk_nobg_m + - pcie_c4_xclk_nobg_m + - pcie_c5_xclk_nobg_m + - pcie_c1_l0_rx_m + - pcie_c1_l1_rx_m + - pcie_c1_l2_rx_m + - pcie_c1_l3_rx_m + - pcie_c2_l0_rx_m + - pcie_c2_l1_rx_m + - pcie_c2_l2_rx_m + - pcie_c2_l3_rx_m + - pcie_c3_l0_rx_m + - pcie_c3_l1_rx_m + - pcie_c4_l0_rx_m + - pcie_c4_l1_rx_m + - pcie_c4_l2_rx_m + - pcie_c4_l3_rx_m + - pcie_c4_l4_rx_m + - pcie_c4_l5_rx_m + - pcie_c4_l6_rx_m + - pcie_c4_l7_rx_m + - pcie_c5_l0_rx_m + - pcie_c5_l1_rx_m + - pcie_c5_l2_rx_m + - pcie_c5_l3_rx_m + - mphy_l0_rx_pwm_bit_m + - mphy_l1_rx_pwm_bit_m + - dbb_uphy0 + - uphy0_uxl_core + - isc_cpu_root + - isc_nic + - ctc_txclk0_m + - ctc_txclk1_m + - ctc_rxclk0_m + - ctc_rxclk1_m + - pllrefgp_out + - pllrefgp_out1 + - gpu_sys + - gpu_nvd + - gpu_uproc + - gpu_gpc0 + - gpu_gpc1 + - gpu_gpc2 + - pllx + - ape_soundwire_msrc0 + - ape_soundwire_data_en_shaper + - ao_soundwire_msrc0 + - ao_soundwire_data_en_shaper + - dpaux0_clk + + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x53 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - ape_tke + - cec + - adsp_all + - rce_all + - ufshc + - ufshc_axi_m + - ufshc_lp_seq + - dpaux + - eqos + - hwpm + - i2c1 + - i2c2 + - i2c3 + - i2c4 + - i2c6 + - i2c7 + - i2c8 + - i2c9 + - isp + - la + - nvcsi + - eqos_mac + - pwm10 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm9 + - qspi0 + - hda + - hdacodec + - i2c0 + - i2c10 + - sdmmc1 + - mipi_cal + - spi1 + - spi2 + - spi3 + - spi4 + - spi5 + - spi7 + - spi8 + - spi9 + - tach0 + - tsec + - vi + - vi1 + - pva0_all + - vic + - mphy_clk_ctl + - mphy_l0_rx + - mphy_l0_tx + - mphy_l1_rx + - mphy_l1_tx + - isp1 + - i2c11 + - i2c12 + - i2c14 + - i2c15 + - i2c16 + - eqos_macsec + - mgbe0_pcs + - mgbe0_mac + - mgbe0_macsec + - mgbe1_pcs + - mgbe1_mac + - mgbe1_macsec + - mgbe2_pcs + - mgbe2_mac + - mgbe2_macsec + - mgbe3_pcs + - mgbe3_mac + - mgbe3_macsec + - adsp_core0 + - adsp_core1 + - ape + - xusb1_padctl + - aon_cpu_all + - uart4 + - uart5 + - uart9 + - uart10 + + +required: + - compatible + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + mods-clocks { + compatible = "nvidia,mods-clocks"; + status = "disabled"; + clocks = <&bpmp TEGRA264_CLK_OSC >, + <&bpmp TEGRA264_CLK_CLK_S >, + <&bpmp TEGRA264_CLK_JTAG_REG >, + <&bpmp TEGRA264_CLK_SPLL >, + <&bpmp TEGRA264_CLK_SPLL_OUT0 >, + <&bpmp TEGRA264_CLK_SPLL_OUT1 >, + <&bpmp TEGRA264_CLK_SPLL_OUT2 >, + <&bpmp TEGRA264_CLK_SPLL_OUT3 >, + <&bpmp TEGRA264_CLK_SPLL_OUT4 >, + <&bpmp TEGRA264_CLK_SPLL_OUT5 >, + <&bpmp TEGRA264_CLK_SPLL_OUT6 >, + <&bpmp TEGRA264_CLK_SPLL_OUT7 >, + <&bpmp TEGRA264_CLK_AON_I2C >, + <&bpmp TEGRA264_CLK_HOST1X >, + <&bpmp TEGRA264_CLK_ISP >, + <&bpmp TEGRA264_CLK_ISP1 >, + <&bpmp TEGRA264_CLK_ISP_ROOT >, + <&bpmp TEGRA264_CLK_NAFLL_PVA0_CORE >, + <&bpmp TEGRA264_CLK_NAFLL_PVA0_VPS >, + <&bpmp TEGRA264_CLK_NVCSI >, + <&bpmp TEGRA264_CLK_NVCSILP >, + <&bpmp TEGRA264_CLK_PLLP_OUT0 >, + <&bpmp TEGRA264_CLK_PVA0_CPU_AXI >, + <&bpmp TEGRA264_CLK_PVA0_VPS >, + <&bpmp TEGRA264_CLK_PWM10 >, + <&bpmp TEGRA264_CLK_PWM2 >, + <&bpmp TEGRA264_CLK_PWM3 >, + <&bpmp TEGRA264_CLK_PWM4 >, + <&bpmp TEGRA264_CLK_PWM5 >, + <&bpmp TEGRA264_CLK_PWM9 >, + <&bpmp TEGRA264_CLK_QSPI0 >, + <&bpmp TEGRA264_CLK_QSPI0_2X_PM >, + <&bpmp TEGRA264_CLK_RCE1_CPU >, + <&bpmp TEGRA264_CLK_RCE1_NIC >, + <&bpmp TEGRA264_CLK_RCE_CPU >, + <&bpmp TEGRA264_CLK_RCE_NIC >, + <&bpmp TEGRA264_CLK_SE >, + <&bpmp TEGRA264_CLK_SEU1 >, + <&bpmp TEGRA264_CLK_SEU2 >, + <&bpmp TEGRA264_CLK_SEU3 >, + <&bpmp TEGRA264_CLK_SE_ROOT >, + <&bpmp TEGRA264_CLK_SPI1 >, + <&bpmp TEGRA264_CLK_SPI2 >, + <&bpmp TEGRA264_CLK_SPI3 >, + <&bpmp TEGRA264_CLK_SPI4 >, + <&bpmp TEGRA264_CLK_SPI5 >, + <&bpmp TEGRA264_CLK_TOP_I2C >, + <&bpmp TEGRA264_CLK_TSEC >, + <&bpmp TEGRA264_CLK_TSEC_PKA >, + <&bpmp TEGRA264_CLK_UART0 >, + <&bpmp TEGRA264_CLK_UART10 >, + <&bpmp TEGRA264_CLK_UART11 >, + <&bpmp TEGRA264_CLK_UART4 >, + <&bpmp TEGRA264_CLK_UART5 >, + <&bpmp TEGRA264_CLK_UART8 >, + <&bpmp TEGRA264_CLK_UART9 >, + <&bpmp TEGRA264_CLK_VI >, + <&bpmp TEGRA264_CLK_VI1 >, + <&bpmp TEGRA264_CLK_VIC >, + <&bpmp TEGRA264_CLK_VI_ROOT >, + <&bpmp TEGRA264_CLK_DISPPLL >, + <&bpmp TEGRA264_CLK_SPPLL0 >, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT1A >, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT2A >, + <&bpmp TEGRA264_CLK_SPPLL1 >, + <&bpmp TEGRA264_CLK_VPLL0 >, + <&bpmp TEGRA264_CLK_VPLL1 >, + <&bpmp TEGRA264_CLK_VPLL2 >, + <&bpmp TEGRA264_CLK_VPLL3 >, + <&bpmp TEGRA264_CLK_VPLL4 >, + <&bpmp TEGRA264_CLK_VPLL5 >, + <&bpmp TEGRA264_CLK_VPLL6 >, + <&bpmp TEGRA264_CLK_VPLL7 >, + <&bpmp TEGRA264_CLK_RG0_DIV >, + <&bpmp TEGRA264_CLK_RG1_DIV >, + <&bpmp TEGRA264_CLK_RG2_DIV >, + <&bpmp TEGRA264_CLK_RG3_DIV >, + <&bpmp TEGRA264_CLK_RG4_DIV >, + <&bpmp TEGRA264_CLK_RG5_DIV >, + <&bpmp TEGRA264_CLK_RG6_DIV >, + <&bpmp TEGRA264_CLK_RG7_DIV >, + <&bpmp TEGRA264_CLK_RG0 >, + <&bpmp TEGRA264_CLK_RG1 >, + <&bpmp TEGRA264_CLK_RG2 >, + <&bpmp TEGRA264_CLK_RG3 >, + <&bpmp TEGRA264_CLK_RG4 >, + <&bpmp TEGRA264_CLK_RG5 >, + <&bpmp TEGRA264_CLK_RG6 >, + <&bpmp TEGRA264_CLK_RG7 >, + <&bpmp TEGRA264_CLK_DISP >, + <&bpmp TEGRA264_CLK_DSC >, + <&bpmp TEGRA264_CLK_DSC_ROOT >, + <&bpmp TEGRA264_CLK_HUB >, + <&bpmp TEGRA264_CLK_VPLLX_SOR0_MUXED >, + <&bpmp TEGRA264_CLK_VPLLX_SOR1_MUXED >, + <&bpmp TEGRA264_CLK_VPLLX_SOR2_MUXED >, + <&bpmp TEGRA264_CLK_VPLLX_SOR3_MUXED >, + <&bpmp TEGRA264_CLK_LINKA_SYM >, + <&bpmp TEGRA264_CLK_LINKB_SYM >, + <&bpmp TEGRA264_CLK_LINKC_SYM >, + <&bpmp TEGRA264_CLK_LINKD_SYM >, + <&bpmp TEGRA264_CLK_PRE_SOR0 >, + <&bpmp TEGRA264_CLK_PRE_SOR1 >, + <&bpmp TEGRA264_CLK_PRE_SOR2 >, + <&bpmp TEGRA264_CLK_PRE_SOR3 >, + <&bpmp TEGRA264_CLK_SOR0_PLL_REF >, + <&bpmp TEGRA264_CLK_SOR1_PLL_REF >, + <&bpmp TEGRA264_CLK_SOR2_PLL_REF >, + <&bpmp TEGRA264_CLK_SOR3_PLL_REF >, + <&bpmp TEGRA264_CLK_SOR0_PAD >, + <&bpmp TEGRA264_CLK_SOR1_PAD >, + <&bpmp TEGRA264_CLK_SOR2_PAD >, + <&bpmp TEGRA264_CLK_SOR3_PAD >, + <&bpmp TEGRA264_CLK_SOR0_REF >, + <&bpmp TEGRA264_CLK_SOR1_REF >, + <&bpmp TEGRA264_CLK_SOR2_REF >, + <&bpmp TEGRA264_CLK_SOR3_REF >, + <&bpmp TEGRA264_CLK_SOR0_DIV >, + <&bpmp TEGRA264_CLK_SOR1_DIV >, + <&bpmp TEGRA264_CLK_SOR2_DIV >, + <&bpmp TEGRA264_CLK_SOR3_DIV >, + <&bpmp TEGRA264_CLK_SOR0 >, + <&bpmp TEGRA264_CLK_SOR1 >, + <&bpmp TEGRA264_CLK_SOR2 >, + <&bpmp TEGRA264_CLK_SOR3 >, + <&bpmp TEGRA264_CLK_SF0_SOR >, + <&bpmp TEGRA264_CLK_SF1_SOR >, + <&bpmp TEGRA264_CLK_SF2_SOR >, + <&bpmp TEGRA264_CLK_SF3_SOR >, + <&bpmp TEGRA264_CLK_SF4_SOR >, + <&bpmp TEGRA264_CLK_SF5_SOR >, + <&bpmp TEGRA264_CLK_SF6_SOR >, + <&bpmp TEGRA264_CLK_SF7_SOR >, + <&bpmp TEGRA264_CLK_SF0 >, + <&bpmp TEGRA264_CLK_SF1 >, + <&bpmp TEGRA264_CLK_SF2 >, + <&bpmp TEGRA264_CLK_SF3 >, + <&bpmp TEGRA264_CLK_SF4 >, + <&bpmp TEGRA264_CLK_SF5 >, + <&bpmp TEGRA264_CLK_SF6 >, + <&bpmp TEGRA264_CLK_SF7 >, + <&bpmp TEGRA264_CLK_MAUD >, + <&bpmp TEGRA264_CLK_AZA_2XBIT >, + <&bpmp TEGRA264_CLK_DCE_CPU >, + <&bpmp TEGRA264_CLK_DCE_NIC >, + <&bpmp TEGRA264_CLK_PLLC4 >, + <&bpmp TEGRA264_CLK_PLLC4_OUT0 >, + <&bpmp TEGRA264_CLK_PLLC4_OUT1 >, + <&bpmp TEGRA264_CLK_PLLC4_MUXED >, + <&bpmp TEGRA264_CLK_SDMMC1 >, + <&bpmp TEGRA264_CLK_SDMMC_LEGACY_TM >, + <&bpmp TEGRA264_CLK_PLLC0 >, + <&bpmp TEGRA264_CLK_NAFLL_BPMP >, + <&bpmp TEGRA264_CLK_PLLP_OUT_PDIV >, + <&bpmp TEGRA264_CLK_DISP_ROOT >, + <&bpmp TEGRA264_CLK_ADSP >, + <&bpmp TEGRA264_CLK_PLLA >, + <&bpmp TEGRA264_CLK_PLLA1 >, + <&bpmp TEGRA264_CLK_PLLA1_OUT1 >, + <&bpmp TEGRA264_CLK_PLLAON >, + <&bpmp TEGRA264_CLK_PLLAON_APE >, + <&bpmp TEGRA264_CLK_PLLA_OUT0 >, + <&bpmp TEGRA264_CLK_AHUB >, + <&bpmp TEGRA264_CLK_APE >, + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S2_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S9_SCLK_IN >, + <&bpmp TEGRA264_CLK_I2S1_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S2_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S3_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S4_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S5_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S6_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S7_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S8_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_DMIC1_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_DSPK1_AUDIO_SYNC >, + <&bpmp TEGRA264_CLK_I2S1 >, + <&bpmp TEGRA264_CLK_I2S2 >, + <&bpmp TEGRA264_CLK_I2S3 >, + <&bpmp TEGRA264_CLK_I2S4 >, + <&bpmp TEGRA264_CLK_I2S5 >, + <&bpmp TEGRA264_CLK_I2S6 >, + <&bpmp TEGRA264_CLK_I2S7 >, + <&bpmp TEGRA264_CLK_I2S8 >, + <&bpmp TEGRA264_CLK_I2S9 >, + <&bpmp TEGRA264_CLK_DMIC1 >, + <&bpmp TEGRA264_CLK_DMIC5 >, + <&bpmp TEGRA264_CLK_DSPK1 >, + <&bpmp TEGRA264_CLK_AON_CPU >, + <&bpmp TEGRA264_CLK_AON_NIC >, + <&bpmp TEGRA264_CLK_BPMP >, + <&bpmp TEGRA264_CLK_AXI_CBB >, + <&bpmp TEGRA264_CLK_FUSE >, + <&bpmp TEGRA264_CLK_TSENSE >, + <&bpmp TEGRA264_CLK_CSITE >, + <&bpmp TEGRA264_CLK_HCSITE >, + <&bpmp TEGRA264_CLK_DBGAPB >, + <&bpmp TEGRA264_CLK_LA >, + <&bpmp TEGRA264_CLK_PLLREFGP >, + <&bpmp TEGRA264_CLK_PLLE0 >, + <&bpmp TEGRA264_CLK_UPHY0_PLL0_XDIG >, + <&bpmp TEGRA264_CLK_EQOS_APP >, + <&bpmp TEGRA264_CLK_EQOS_MAC >, + <&bpmp TEGRA264_CLK_EQOS_MACSEC >, + <&bpmp TEGRA264_CLK_EQOS_TX_PCS >, + <&bpmp TEGRA264_CLK_MGBES_PTP_REF >, + <&bpmp TEGRA264_CLK_MGBE0_UPHY1_PLL_XDIG >, + <&bpmp TEGRA264_CLK_MGBE0_TX_PCS >, + <&bpmp TEGRA264_CLK_MGBE0_MAC >, + <&bpmp TEGRA264_CLK_MGBE0_MACSEC >, + <&bpmp TEGRA264_CLK_MGBE0_APP >, + <&bpmp TEGRA264_CLK_MGBE1_UPHY1_PLL_XDIG >, + <&bpmp TEGRA264_CLK_MGBE1_TX_PCS >, + <&bpmp TEGRA264_CLK_MGBE1_MAC >, + <&bpmp TEGRA264_CLK_MGBE1_MACSEC >, + <&bpmp TEGRA264_CLK_MGBE1_APP >, + <&bpmp TEGRA264_CLK_MGBE2_UPHY1_PLL_XDIG >, + <&bpmp TEGRA264_CLK_MGBE2_TX_PCS >, + <&bpmp TEGRA264_CLK_MGBE2_MAC >, + <&bpmp TEGRA264_CLK_MGBE2_MACSEC >, + <&bpmp TEGRA264_CLK_MGBE2_APP >, + <&bpmp TEGRA264_CLK_MGBE3_UPHY1_PLL_XDIG >, + <&bpmp TEGRA264_CLK_MGBE3_TX_PCS >, + <&bpmp TEGRA264_CLK_MGBE3_MAC >, + <&bpmp TEGRA264_CLK_MGBE3_MACSEC >, + <&bpmp TEGRA264_CLK_MGBE3_APP >, + <&bpmp TEGRA264_CLK_PLLREFUFS >, + <&bpmp TEGRA264_CLK_PLLREFUFS_CLKOUT624 >, + <&bpmp TEGRA264_CLK_PLLREFUFS_REFCLKOUT >, + <&bpmp TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT >, + <&bpmp TEGRA264_CLK_UFSHC_CG_SYS >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_BIT_DIV >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_BIT >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_SYMB_DIV >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_HS_SYMB_DIV >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_SYMB >, + <&bpmp TEGRA264_CLK_MPHY_L0_UPHY_TX_FIFO >, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT_DIV >, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_SYMB_DIV >, + <&bpmp TEGRA264_CLK_UPHY0_PLL4_XDIG >, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_HS_SYMB_DIV >, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_SYMB >, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_ANA >, + <&bpmp TEGRA264_CLK_MPHY_L1_RX_ANA >, + <&bpmp TEGRA264_CLK_MPHY_TX_1MHZ_REF >, + <&bpmp TEGRA264_CLK_MPHY_CORE_PLL_FIXED >, + <&bpmp TEGRA264_CLK_MPHY_IOBIST >, + <&bpmp TEGRA264_CLK_UFSHC_CG_SYS_DIV >, + <&bpmp TEGRA264_CLK_XUSB1_CORE >, + <&bpmp TEGRA264_CLK_XUSB1_FALCON >, + <&bpmp TEGRA264_CLK_XUSB1_FS >, + <&bpmp TEGRA264_CLK_XUSB1_SS >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P0_RX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P1_RX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P2_RX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P3_RX_CORE >, + <&bpmp TEGRA264_CLK_XUSB1_CLK480M_NVWRAP_CORE >, + <&bpmp TEGRA264_CLK_XUSB1_CORE_HOST >, + <&bpmp TEGRA264_CLK_XUSB1_CORE_DEV >, + <&bpmp TEGRA264_CLK_XUSB1_CORE_SUPERSPEED >, + <&bpmp TEGRA264_CLK_XUSB1_FALCON_HOST >, + <&bpmp TEGRA264_CLK_XUSB1_FALCON_SUPERSPEED >, + <&bpmp TEGRA264_CLK_XUSB1_FS_HOST >, + <&bpmp TEGRA264_CLK_XUSB1_FS_DEV >, + <&bpmp TEGRA264_CLK_XUSB1_HS_HSICP >, + <&bpmp TEGRA264_CLK_XUSB1_SS_DEV >, + <&bpmp TEGRA264_CLK_XUSB1_SS_SUPERSPEED >, + <&bpmp TEGRA264_CLK_AON_TOUCH >, + <&bpmp TEGRA264_CLK_AUD_MCLK >, + <&bpmp TEGRA264_CLK_EXTPERIPH1 >, + <&bpmp TEGRA264_CLK_EXTPERIPH2 >, + <&bpmp TEGRA264_CLK_EXTPERIPH3 >, + <&bpmp TEGRA264_CLK_EXTPERIPH4 >, + <&bpmp TEGRA264_CLK_JTAG_REG_UNGATED >, + <&bpmp TEGRA264_CLK_IST_BUS >, + <&bpmp TEGRA264_CLK_IST_BUS_RIST_MCC >, + <&bpmp TEGRA264_CLK_MATHS_SEC_RIST >, + <&bpmp TEGRA264_CLK_NAFLL_IST >, + <&bpmp TEGRA264_CLK_RIST_ROOT >, + <&bpmp TEGRA264_CLK_IST_CONTROLLER_RIST >, + <&bpmp TEGRA264_CLK_MSS_ENCRYPT >, + <&bpmp TEGRA264_CLK_EMC >, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT100 >, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT270 >, + <&bpmp TEGRA264_CLK_SPPLL1_CLKOUT100 >, + <&bpmp TEGRA264_CLK_SPPLL1_CLKOUT270 >, + <&bpmp TEGRA264_CLK_DP_LINKA_REF >, + <&bpmp TEGRA264_CLK_DP_LINKB_REF >, + <&bpmp TEGRA264_CLK_DP_LINKC_REF >, + <&bpmp TEGRA264_CLK_DP_LINKD_REF >, + <&bpmp TEGRA264_CLK_PLLNVCSI >, + <&bpmp TEGRA264_CLK_PLLBPMPCAM >, + <&bpmp TEGRA264_CLK_UTMI_PLL1 >, + <&bpmp TEGRA264_CLK_UTMI_PLL1_CLKOUT48 >, + <&bpmp TEGRA264_CLK_UTMI_PLL1_CLKOUT60 >, + <&bpmp TEGRA264_CLK_UTMI_PLL1_CLKOUT480 >, + <&bpmp TEGRA264_CLK_NAFLL_ISP >, + <&bpmp TEGRA264_CLK_NAFLL_RCE >, + <&bpmp TEGRA264_CLK_NAFLL_RCE1 >, + <&bpmp TEGRA264_CLK_NAFLL_SE >, + <&bpmp TEGRA264_CLK_NAFLL_VI >, + <&bpmp TEGRA264_CLK_NAFLL_VIC >, + <&bpmp TEGRA264_CLK_NAFLL_DCE >, + <&bpmp TEGRA264_CLK_NAFLL_TSEC >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR0 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR1 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR2 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR3 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR4 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR5 >, + <&bpmp TEGRA264_CLK_NAFLL_CPAIR6 >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_SYS >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_NVD >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_UPROC >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_GPC0 >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_GPC1 >, + <&bpmp TEGRA264_CLK_NAFLL_GPU_GPC2 >, + <&bpmp TEGRA264_CLK_SOR_LINKA_INPUT >, + <&bpmp TEGRA264_CLK_SOR_LINKB_INPUT >, + <&bpmp TEGRA264_CLK_SOR_LINKC_INPUT >, + <&bpmp TEGRA264_CLK_SOR_LINKD_INPUT >, + <&bpmp TEGRA264_CLK_SOR_LINKA_AFIFO >, + <&bpmp TEGRA264_CLK_SOR_LINKB_AFIFO >, + <&bpmp TEGRA264_CLK_SOR_LINKC_AFIFO >, + <&bpmp TEGRA264_CLK_SOR_LINKD_AFIFO >, + <&bpmp TEGRA264_CLK_I2S1_PAD_M >, + <&bpmp TEGRA264_CLK_I2S2_PAD_M >, + <&bpmp TEGRA264_CLK_I2S3_PAD_M >, + <&bpmp TEGRA264_CLK_I2S4_PAD_M >, + <&bpmp TEGRA264_CLK_I2S5_PAD_M >, + <&bpmp TEGRA264_CLK_I2S6_PAD_M >, + <&bpmp TEGRA264_CLK_I2S7_PAD_M >, + <&bpmp TEGRA264_CLK_I2S8_PAD_M >, + <&bpmp TEGRA264_CLK_I2S9_PAD_M >, + <&bpmp TEGRA264_CLK_BPMP_NIC >, + <&bpmp TEGRA264_CLK_CLK1M >, + <&bpmp TEGRA264_CLK_RDET >, + <&bpmp TEGRA264_CLK_ADC_SOC_REF >, + <&bpmp TEGRA264_CLK_UPHY0_PLL0_TXREF >, + <&bpmp TEGRA264_CLK_EQOS_TX >, + <&bpmp TEGRA264_CLK_EQOS_TX_M >, + <&bpmp TEGRA264_CLK_EQOS_RX_PCS_IN >, + <&bpmp TEGRA264_CLK_EQOS_RX_PCS_M >, + <&bpmp TEGRA264_CLK_EQOS_RX_IN >, + <&bpmp TEGRA264_CLK_EQOS_RX >, + <&bpmp TEGRA264_CLK_EQOS_RX_M >, + <&bpmp TEGRA264_CLK_MGBE0_UPHY1_PLL_TXREF >, + <&bpmp TEGRA264_CLK_MGBE0_TX >, + <&bpmp TEGRA264_CLK_MGBE0_TX_M >, + <&bpmp TEGRA264_CLK_MGBE0_RX_PCS_IN >, + <&bpmp TEGRA264_CLK_MGBE0_RX_PCS_M >, + <&bpmp TEGRA264_CLK_MGBE0_RX_IN >, + <&bpmp TEGRA264_CLK_MGBE0_RX_M >, + <&bpmp TEGRA264_CLK_MGBE1_UPHY1_PLL_TXREF >, + <&bpmp TEGRA264_CLK_MGBE1_TX >, + <&bpmp TEGRA264_CLK_MGBE1_TX_M >, + <&bpmp TEGRA264_CLK_MGBE1_RX_PCS_IN >, + <&bpmp TEGRA264_CLK_MGBE1_RX_PCS_M >, + <&bpmp TEGRA264_CLK_MGBE1_RX_IN >, + <&bpmp TEGRA264_CLK_MGBE1_RX_M >, + <&bpmp TEGRA264_CLK_MGBE2_UPHY1_PLL_TXREF >, + <&bpmp TEGRA264_CLK_MGBE2_TX >, + <&bpmp TEGRA264_CLK_MGBE2_TX_M >, + <&bpmp TEGRA264_CLK_MGBE2_RX_PCS_IN >, + <&bpmp TEGRA264_CLK_MGBE2_RX_PCS_M >, + <&bpmp TEGRA264_CLK_MGBE2_RX_IN >, + <&bpmp TEGRA264_CLK_MGBE2_RX_M >, + <&bpmp TEGRA264_CLK_MGBE3_UPHY1_PLL_TXREF >, + <&bpmp TEGRA264_CLK_MGBE3_TX >, + <&bpmp TEGRA264_CLK_MGBE3_TX_M >, + <&bpmp TEGRA264_CLK_MGBE3_RX_PCS_IN >, + <&bpmp TEGRA264_CLK_MGBE3_RX_PCS_M >, + <&bpmp TEGRA264_CLK_MGBE3_RX_IN >, + <&bpmp TEGRA264_CLK_MGBE3_RX_M >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P0_TX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P1_TX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P2_TX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P3_TX_CORE >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P0_TX >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P1_TX >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P2_TX >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P3_TX >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P0_RX_IN >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P1_RX_IN >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P2_RX_IN >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P3_RX_IN >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P0_RX_M >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P1_RX_M >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P2_RX_M >, + <&bpmp TEGRA264_CLK_UPHY0_USB_P3_RX_M >, + <&bpmp TEGRA264_CLK_UPHY0_LANE0_TX_M >, + <&bpmp TEGRA264_CLK_PCIE_C1_XCLK_NOBG_M >, + <&bpmp TEGRA264_CLK_PCIE_C2_XCLK_NOBG_M >, + <&bpmp TEGRA264_CLK_PCIE_C3_XCLK_NOBG_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_XCLK_NOBG_M >, + <&bpmp TEGRA264_CLK_PCIE_C5_XCLK_NOBG_M >, + <&bpmp TEGRA264_CLK_PCIE_C1_L0_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C1_L1_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C1_L2_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C1_L3_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C2_L0_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C2_L1_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C2_L2_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C2_L3_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C3_L0_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C3_L1_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L0_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L1_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L2_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L3_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L4_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L5_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L6_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C4_L7_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C5_L0_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C5_L1_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C5_L2_RX_M >, + <&bpmp TEGRA264_CLK_PCIE_C5_L3_RX_M >, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_PWM_BIT_M >, + <&bpmp TEGRA264_CLK_MPHY_L1_RX_PWM_BIT_M >, + <&bpmp TEGRA264_CLK_DBB_UPHY0 >, + <&bpmp TEGRA264_CLK_UPHY0_UXL_CORE >, + <&bpmp TEGRA264_CLK_ISC_CPU_ROOT >, + <&bpmp TEGRA264_CLK_ISC_NIC >, + <&bpmp TEGRA264_CLK_CTC_TXCLK0_M >, + <&bpmp TEGRA264_CLK_CTC_TXCLK1_M >, + <&bpmp TEGRA264_CLK_CTC_RXCLK0_M >, + <&bpmp TEGRA264_CLK_CTC_RXCLK1_M >, + <&bpmp TEGRA264_CLK_PLLREFGP_OUT >, + <&bpmp TEGRA264_CLK_PLLREFGP_OUT1 >, + <&bpmp TEGRA264_CLK_GPU_SYS >, + <&bpmp TEGRA264_CLK_GPU_NVD >, + <&bpmp TEGRA264_CLK_GPU_UPROC >, + <&bpmp TEGRA264_CLK_GPU_GPC0 >, + <&bpmp TEGRA264_CLK_GPU_GPC1 >, + <&bpmp TEGRA264_CLK_GPU_GPC2 >, + <&bpmp TEGRA264_CLK_PLLX >, + <&bpmp TEGRA264_CLK_APE_SOUNDWIRE_MSRC0 >, + <&bpmp TEGRA264_CLK_APE_SOUNDWIRE_DATA_EN_SHAPER >, + <&bpmp TEGRA264_CLK_AO_SOUNDWIRE_MSRC0 >, + <&bpmp TEGRA264_CLK_AO_SOUNDWIRE_DATA_EN_SHAPER >, + <&bpmp TEGRA264_CLK_DPAUX >; + clock-names = "osc", + "clk_s", + "jtag_reg", + "spll", + "spll_out0", + "spll_out1", + "spll_out2", + "spll_out3", + "spll_out4", + "spll_out5", + "spll_out6", + "spll_out7", + "aon_i2c", + "host1x", + "isp", + "isp1", + "isp_root", + "nafll_pva0_core", + "nafll_pva0_vps", + "nvcsi", + "nvcsilp", + "pllp_out0", + "pva0_cpu_axi", + "pva0_vps", + "pwm10", + "pwm2", + "pwm3", + "pwm4", + "pwm5", + "pwm9", + "qspi0", + "qspi0_2x_pm", + "rce1_cpu", + "rce1_nic", + "rce_cpu", + "rce_nic", + "se", + "seu1", + "seu2", + "seu3", + "se_root", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + "top_i2c", + "tsec", + "tsec_pka", + "uart0", + "uart10", + "uart11", + "uart4", + "uart5", + "uart8", + "uart9", + "vi", + "vi1", + "vic", + "vi_root", + "disppll", + "sppll0", + "sppll0_clkout1a", + "sppll0_clkout2a", + "sppll1", + "vpll0", + "vpll1", + "vpll2", + "vpll3", + "vpll4", + "vpll5", + "vpll6", + "vpll7", + "rg0_div", + "rg1_div", + "rg2_div", + "rg3_div", + "rg4_div", + "rg5_div", + "rg6_div", + "rg7_div", + "rg0", + "rg1", + "rg2", + "rg3", + "rg4", + "rg5", + "rg6", + "rg7", + "disp", + "dsc", + "dsc_root", + "hub", + "vpllx_sor0_muxed", + "vpllx_sor1_muxed", + "vpllx_sor2_muxed", + "vpllx_sor3_muxed", + "linka_sym", + "linkb_sym", + "linkc_sym", + "linkd_sym", + "pre_sor0", + "pre_sor1", + "pre_sor2", + "pre_sor3", + "sor0_pll_ref", + "sor1_pll_ref", + "sor2_pll_ref", + "sor3_pll_ref", + "sor0_pad", + "sor1_pad", + "sor2_pad", + "sor3_pad", + "sor0_ref", + "sor1_ref", + "sor2_ref", + "sor3_ref", + "sor0_div", + "sor1_div", + "sor2_div", + "sor3_div", + "sor0", + "sor1", + "sor2", + "sor3", + "sf0_sor", + "sf1_sor", + "sf2_sor", + "sf3_sor", + "sf4_sor", + "sf5_sor", + "sf6_sor", + "sf7_sor", + "sf0", + "sf1", + "sf2", + "sf3", + "sf4", + "sf5", + "sf6", + "sf7", + "maud", + "aza_2xbit", + "dce_cpu", + "dce_nic", + "pllc4", + "pllc4_out0", + "pllc4_out1", + "pllc4_muxed", + "sdmmc1", + "sdmmc_legacy_tm", + "pllc0", + "nafll_bpmp", + "pllp_out_pdiv", + "disp_root", + "adsp", + "plla", + "plla1", + "plla1_out1", + "pllaon", + "pllaon_ape", + "plla_out0", + "ahub", + "ape", + "i2s1_sclk_in", + "i2s2_sclk_in", + "i2s3_sclk_in", + "i2s4_sclk_in", + "i2s5_sclk_in", + "i2s6_sclk_in", + "i2s7_sclk_in", + "i2s8_sclk_in", + "i2s9_sclk_in", + "i2s1_audio_sync", + "i2s2_audio_sync", + "i2s3_audio_sync", + "i2s4_audio_sync", + "i2s5_audio_sync", + "i2s6_audio_sync", + "i2s7_audio_sync", + "i2s8_audio_sync", + "dmic1_audio_sync", + "dspk1_audio_sync", + "i2s1", + "i2s2", + "i2s3", + "i2s4", + "i2s5", + "i2s6", + "i2s7", + "i2s8", + "i2s9", + "dmic1", + "dmic5", + "dspk1", + "aon_cpu", + "aon_nic", + "bpmp", + "axi_cbb", + "fuse", + "tsense", + "csite", + "hcsite", + "dbgapb", + "la", + "pllrefgp", + "plle0", + "uphy0_pll0_xdig", + "eqos_app", + "eqos_mac", + "eqos_macsec", + "eqos_tx_pcs", + "mgbes_ptp_ref", + "mgbe0_uphy1_pll_xdig", + "mgbe0_tx_pcs", + "mgbe0_mac", + "mgbe0_macsec", + "mgbe0_app", + "mgbe1_uphy1_pll_xdig", + "mgbe1_tx_pcs", + "mgbe1_mac", + "mgbe1_macsec", + "mgbe1_app", + "mgbe2_uphy1_pll_xdig", + "mgbe2_tx_pcs", + "mgbe2_mac", + "mgbe2_macsec", + "mgbe2_app", + "mgbe3_uphy1_pll_xdig", + "mgbe3_tx_pcs", + "mgbe3_mac", + "mgbe3_macsec", + "mgbe3_app", + "pllrefufs", + "pllrefufs_clkout624", + "pllrefufs_refclkout", + "pllrefufs_ufsdev_refclkout", + "ufshc_cg_sys", + "mphy_l0_rx_ls_bit_div", + "mphy_l0_rx_ls_bit", + "mphy_l0_rx_ls_symb_div", + "mphy_l0_rx_hs_symb_div", + "mphy_l0_rx_symb", + "mphy_l0_uphy_tx_fifo", + "mphy_l0_tx_ls_3xbit_div", + "mphy_l0_tx_ls_symb_div", + "uphy0_pll4_xdig", + "mphy_l0_tx_hs_symb_div", + "mphy_l0_tx_symb", + "mphy_l0_tx_ls_3xbit", + "mphy_l0_rx_ana", + "mphy_l1_rx_ana", + "mphy_tx_1mhz_ref", + "mphy_core_pll_fixed", + "mphy_iobist", + "ufshc_cg_sys_div", + "xusb1_core", + "xusb1_falcon", + "xusb1_fs", + "xusb1_ss", + "uphy0_usb_p0_rx_core", + "uphy0_usb_p1_rx_core", + "uphy0_usb_p2_rx_core", + "uphy0_usb_p3_rx_core", + "xusb1_clk480m_nvwrap_core", + "xusb1_core_host", + "xusb1_core_dev", + "xusb1_core_superspeed", + "xusb1_falcon_host", + "xusb1_falcon_superspeed", + "xusb1_fs_host", + "xusb1_fs_dev", + "xusb1_hs_hsicp", + "xusb1_ss_dev", + "xusb1_ss_superspeed", + "aon_touch", + "aud_mclk", + "extperiph1", + "extperiph2", + "extperiph3", + "extperiph4", + "jtag_reg_ungated", + "ist_bus", + "ist_bus_rist_mcc", + "maths_sec_rist", + "nafll_ist", + "rist_root", + "ist_controller_rist", + "mss_encrypt", + "emc", + "sppll0_clkout100", + "sppll0_clkout270", + "sppll1_clkout100", + "sppll1_clkout270", + "dp_linka_ref", + "dp_linkb_ref", + "dp_linkc_ref", + "dp_linkd_ref", + "pllnvcsi", + "pllbpmpcam", + "utmi_pll1", + "utmi_pll1_clkout48", + "utmi_pll1_clkout60", + "utmi_pll1_clkout480", + "nafll_isp", + "nafll_rce", + "nafll_rce1", + "nafll_se", + "nafll_vi", + "nafll_vic", + "nafll_dce", + "nafll_tsec", + "nafll_cpair0", + "nafll_cpair1", + "nafll_cpair2", + "nafll_cpair3", + "nafll_cpair4", + "nafll_cpair5", + "nafll_cpair6", + "nafll_gpu_sys", + "nafll_gpu_nvd", + "nafll_gpu_uproc", + "nafll_gpu_gpc0", + "nafll_gpu_gpc1", + "nafll_gpu_gpc2", + "sor_linka_input", + "sor_linkb_input", + "sor_linkc_input", + "sor_linkd_input", + "sor_linka_afifo", + "sor_linkb_afifo", + "sor_linkc_afifo", + "sor_linkd_afifo", + "i2s1_pad_m", + "i2s2_pad_m", + "i2s3_pad_m", + "i2s4_pad_m", + "i2s5_pad_m", + "i2s6_pad_m", + "i2s7_pad_m", + "i2s8_pad_m", + "i2s9_pad_m", + "bpmp_nic", + "clk1m", + "rdet", + "adc_soc_ref", + "uphy0_pll0_txref", + "eqos_tx", + "eqos_tx_m", + "eqos_rx_pcs_in", + "eqos_rx_pcs_m", + "eqos_rx_in", + "eqos_rx", + "eqos_rx_m", + "mgbe0_uphy1_pll_txref", + "mgbe0_tx", + "mgbe0_tx_m", + "mgbe0_rx_pcs_in", + "mgbe0_rx_pcs_m", + "mgbe0_rx_in", + "mgbe0_rx_m", + "mgbe1_uphy1_pll_txref", + "mgbe1_tx", + "mgbe1_tx_m", + "mgbe1_rx_pcs_in", + "mgbe1_rx_pcs_m", + "mgbe1_rx_in", + "mgbe1_rx_m", + "mgbe2_uphy1_pll_txref", + "mgbe2_tx", + "mgbe2_tx_m", + "mgbe2_rx_pcs_in", + "mgbe2_rx_pcs_m", + "mgbe2_rx_in", + "mgbe2_rx_m", + "mgbe3_uphy1_pll_txref", + "mgbe3_tx", + "mgbe3_tx_m", + "mgbe3_rx_pcs_in", + "mgbe3_rx_pcs_m", + "mgbe3_rx_in", + "mgbe3_rx_m", + "uphy0_usb_p0_tx_core", + "uphy0_usb_p1_tx_core", + "uphy0_usb_p2_tx_core", + "uphy0_usb_p3_tx_core", + "uphy0_usb_p0_tx", + "uphy0_usb_p1_tx", + "uphy0_usb_p2_tx", + "uphy0_usb_p3_tx", + "uphy0_usb_p0_rx_in", + "uphy0_usb_p1_rx_in", + "uphy0_usb_p2_rx_in", + "uphy0_usb_p3_rx_in", + "uphy0_usb_p0_rx_m", + "uphy0_usb_p1_rx_m", + "uphy0_usb_p2_rx_m", + "uphy0_usb_p3_rx_m", + "uphy0_lane0_tx_m", + "pcie_c1_xclk_nobg_m", + "pcie_c2_xclk_nobg_m", + "pcie_c3_xclk_nobg_m", + "pcie_c4_xclk_nobg_m", + "pcie_c5_xclk_nobg_m", + "pcie_c1_l0_rx_m", + "pcie_c1_l1_rx_m", + "pcie_c1_l2_rx_m", + "pcie_c1_l3_rx_m", + "pcie_c2_l0_rx_m", + "pcie_c2_l1_rx_m", + "pcie_c2_l2_rx_m", + "pcie_c2_l3_rx_m", + "pcie_c3_l0_rx_m", + "pcie_c3_l1_rx_m", + "pcie_c4_l0_rx_m", + "pcie_c4_l1_rx_m", + "pcie_c4_l2_rx_m", + "pcie_c4_l3_rx_m", + "pcie_c4_l4_rx_m", + "pcie_c4_l5_rx_m", + "pcie_c4_l6_rx_m", + "pcie_c4_l7_rx_m", + "pcie_c5_l0_rx_m", + "pcie_c5_l1_rx_m", + "pcie_c5_l2_rx_m", + "pcie_c5_l3_rx_m", + "mphy_l0_rx_pwm_bit_m", + "mphy_l1_rx_pwm_bit_m", + "dbb_uphy0", + "uphy0_uxl_core", + "isc_cpu_root", + "isc_nic", + "ctc_txclk0_m", + "ctc_txclk1_m", + "ctc_rxclk0_m", + "ctc_rxclk1_m", + "pllrefgp_out", + "pllrefgp_out1", + "gpu_sys", + "gpu_nvd", + "gpu_uproc", + "gpu_gpc0", + "gpu_gpc1", + "gpu_gpc2", + "pllx", + "ape_soundwire_msrc0", + "ape_soundwire_data_en_shaper", + "ao_soundwire_msrc0", + "ao_soundwire_data_en_shaper", + "dpaux0_clk"; + resets = <&bpmp TEGRA264_RESET_APE_TKE >, + <&bpmp TEGRA264_RESET_CEC >, + <&bpmp TEGRA264_RESET_ADSP_ALL >, + <&bpmp TEGRA264_RESET_RCE_ALL >, + <&bpmp TEGRA264_RESET_UFSHC >, + <&bpmp TEGRA264_RESET_UFSHC_AXI_M >, + <&bpmp TEGRA264_RESET_UFSHC_LP_SEQ >, + <&bpmp TEGRA264_RESET_DPAUX >, + <&bpmp TEGRA264_RESET_EQOS_PCS >, + <&bpmp TEGRA264_RESET_HWPM >, + <&bpmp TEGRA264_RESET_I2C1 >, + <&bpmp TEGRA264_RESET_I2C2 >, + <&bpmp TEGRA264_RESET_I2C3 >, + <&bpmp TEGRA264_RESET_I2C4 >, + <&bpmp TEGRA264_RESET_I2C6 >, + <&bpmp TEGRA264_RESET_I2C7 >, + <&bpmp TEGRA264_RESET_I2C8 >, + <&bpmp TEGRA264_RESET_I2C9 >, + <&bpmp TEGRA264_RESET_ISP >, + <&bpmp TEGRA264_RESET_LA >, + <&bpmp TEGRA264_RESET_NVCSI >, + <&bpmp TEGRA264_RESET_EQOS_MAC >, + <&bpmp TEGRA264_RESET_PWM10 >, + <&bpmp TEGRA264_RESET_PWM2 >, + <&bpmp TEGRA264_RESET_PWM3 >, + <&bpmp TEGRA264_RESET_PWM4 >, + <&bpmp TEGRA264_RESET_PWM5 >, + <&bpmp TEGRA264_RESET_PWM9 >, + <&bpmp TEGRA264_RESET_QSPI0 >, + <&bpmp TEGRA264_RESET_HDA >, + <&bpmp TEGRA264_RESET_HDACODEC >, + <&bpmp TEGRA264_RESET_I2C0 >, + <&bpmp TEGRA264_RESET_I2C10 >, + <&bpmp TEGRA264_RESET_SDMMC1 >, + <&bpmp TEGRA264_RESET_MIPI_CAL >, + <&bpmp TEGRA264_RESET_SPI1 >, + <&bpmp TEGRA264_RESET_SPI2 >, + <&bpmp TEGRA264_RESET_SPI3 >, + <&bpmp TEGRA264_RESET_SPI4 >, + <&bpmp TEGRA264_RESET_SPI5 >, + <&bpmp TEGRA264_RESET_SPI7 >, + <&bpmp TEGRA264_RESET_SPI8 >, + <&bpmp TEGRA264_RESET_SPI9 >, + <&bpmp TEGRA264_RESET_TACH0 >, + <&bpmp TEGRA264_RESET_TSEC >, + <&bpmp TEGRA264_RESET_VI >, + <&bpmp TEGRA264_RESET_VI1 >, + <&bpmp TEGRA264_RESET_PVA0_ALL >, + <&bpmp TEGRA264_RESET_VIC >, + <&bpmp TEGRA264_RESET_MPHY_CLK_CTL >, + <&bpmp TEGRA264_RESET_MPHY_L0_RX >, + <&bpmp TEGRA264_RESET_MPHY_L0_TX >, + <&bpmp TEGRA264_RESET_MPHY_L1_RX >, + <&bpmp TEGRA264_RESET_MPHY_L1_TX >, + <&bpmp TEGRA264_RESET_ISP1 >, + <&bpmp TEGRA264_RESET_I2C11 >, + <&bpmp TEGRA264_RESET_I2C12 >, + <&bpmp TEGRA264_RESET_I2C14 >, + <&bpmp TEGRA264_RESET_I2C15 >, + <&bpmp TEGRA264_RESET_I2C16 >, + <&bpmp TEGRA264_RESET_EQOS_MACSEC >, + <&bpmp TEGRA264_RESET_MGBE0_PCS >, + <&bpmp TEGRA264_RESET_MGBE0_MAC >, + <&bpmp TEGRA264_RESET_MGBE0_MACSEC >, + <&bpmp TEGRA264_RESET_MGBE1_PCS >, + <&bpmp TEGRA264_RESET_MGBE1_MAC >, + <&bpmp TEGRA264_RESET_MGBE1_MACSEC >, + <&bpmp TEGRA264_RESET_MGBE2_PCS >, + <&bpmp TEGRA264_RESET_MGBE2_MAC >, + <&bpmp TEGRA264_RESET_MGBE2_MACSEC >, + <&bpmp TEGRA264_RESET_MGBE3_PCS >, + <&bpmp TEGRA264_RESET_MGBE3_MAC >, + <&bpmp TEGRA264_RESET_MGBE3_MACSEC >, + <&bpmp TEGRA264_RESET_ADSP_CORE0 >, + <&bpmp TEGRA264_RESET_ADSP_CORE1 >, + <&bpmp TEGRA264_RESET_APE >, + <&bpmp TEGRA264_RESET_XUSB1_PADCTL >, + <&bpmp TEGRA264_RESET_AON_CPU_ALL >, + <&bpmp TEGRA264_RESET_UART4 >, + <&bpmp TEGRA264_RESET_UART5 >, + <&bpmp TEGRA264_RESET_UART9 >, + <&bpmp TEGRA264_RESET_UART10 >; + reset-names = "ape_tke", + "cec", + "adsp_all", + "rce_all", + "ufshc", + "ufshc_axi_m", + "ufshc_lp_seq", + "dpaux", + "eqos", + "hwpm", + "i2c1", + "i2c2", + "i2c3", + "i2c4", + "i2c6", + "i2c7", + "i2c8", + "i2c9", + "isp", + "la", + "nvcsi", + "eqos_mac", + "pwm10", + "pwm2", + "pwm3", + "pwm4", + "pwm5", + "pwm9", + "qspi0", + "hda", + "hdacodec", + "i2c0", + "i2c10", + "sdmmc1", + "mipi_cal", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + "spi7", + "spi8", + "spi9", + "tach0", + "tsec", + "vi", + "vi1", + "pva0_all", + "vic", + "mphy_clk_ctl", + "mphy_l0_rx", + "mphy_l0_tx", + "mphy_l1_rx", + "mphy_l1_tx", + "isp1", + "i2c11", + "i2c12", + "i2c14", + "i2c15", + "i2c16", + "eqos_macsec", + "mgbe0_pcs", + "mgbe0_mac", + "mgbe0_macsec", + "mgbe1_pcs", + "mgbe1_mac", + "mgbe1_macsec", + "mgbe2_pcs", + "mgbe2_mac", + "mgbe2_macsec", + "mgbe3_pcs", + "mgbe3_mac", + "mgbe3_macsec", + "adsp_core0", + "adsp_core1", + "ape", + "xusb1_padctl", + "aon_cpu_all", + "uart4", + "uart5", + "uart9", + "uart10"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,smmu_test.yaml b/Documentation/devicetree/bindings/misc/nvidia,smmu_test.yaml new file mode 100644 index 00000000..cf499873 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,smmu_test.yaml @@ -0,0 +1,68 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/smmu_test/nvidia,smmu_test.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,smmu_test is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /smmu_test + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,smmu_test + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - iommus + +examples: + - | + smmu_test { + compatible = "nvidia,smmu_test"; + iommus = <&smmu4_mmu 0x00000000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,t264-soc-hwpm.yaml b/Documentation/devicetree/bindings/misc/nvidia,t264-soc-hwpm.yaml new file mode 100644 index 00000000..51cc22fa --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,t264-soc-hwpm.yaml @@ -0,0 +1,228 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_soc_hwpm@1604000/nvidia,t264-soc-hwpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,t264-soc-hwpm is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/tegra_soc_hwpm@1604000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,t264-soc-hwpm + + required: + - compatible + +properties: + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1600000 + maximum: 0x8160f000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x2000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc + maximum: 0xcd + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - la + - parent + + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0x14 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - la + - hwpm + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xe00 + maximum: 0xe00 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - iommus + +examples: + - | + tegra_soc_hwpm@1604000 { + compatible = "nvidia,t264-soc-hwpm"; + dma-coherent; + reg = <0x00 0x01600000 0x0 0x1000>, + <0x00 0x01604000 0x0 0x1000>, + <0x00 0x14100000 0x0 0x1000>, + <0x00 0x14110000 0x0 0x1000>, + <0x00 0x14120000 0x0 0x1000>, + <0x00 0x14130000 0x0 0x1000>, + <0x00 0x14140000 0x0 0x1000>, + <0x00 0x14150000 0x0 0x1000>, + <0x00 0x14160000 0x0 0x1000>, + <0x00 0x14170000 0x0 0x1000>, + <0x00 0x14180000 0x0 0x1000>, + <0x00 0x14190000 0x0 0x1000>, + <0x00 0x141a0000 0x0 0x1000>, + <0x00 0x141b0000 0x0 0x1000>, + <0x00 0x141c0000 0x0 0x1000>, + <0x00 0x141d0000 0x0 0x1000>, + <0x81 0x01600000 0x0 0x1000>, + <0x81 0x01601000 0x0 0x1000>, + <0x81 0x01602000 0x0 0x1000>, + <0x81 0x01603000 0x0 0x1000>, + <0x81 0x01604000 0x0 0x1000>, + <0x81 0x01605000 0x0 0x1000>, + <0x81 0x01606000 0x0 0x1000>, + <0x81 0x01607000 0x0 0x1000>, + <0x81 0x01608000 0x0 0x1000>, + <0x81 0x01609000 0x0 0x1000>, + <0x81 0x0160a000 0x0 0x1000>, + <0x81 0x0160b000 0x0 0x1000>, + <0x81 0x0160c000 0x0 0x1000>, + <0x81 0x0160d000 0x0 0x1000>, + <0x81 0x0160e000 0x0 0x1000>, + <0x81 0x0160f000 0x0 0x1000>, + <0x81 0x01621000 0x0 0x1000>, + <0x81 0x01622000 0x0 0x1000>, + <0x81 0x01623000 0x0 0x1000>, + <0x81 0x01624000 0x0 0x1000>, + <0x81 0x01625000 0x0 0x1000>, + <0x81 0x01626000 0x0 0x1000>, + <0x81 0x01627000 0x0 0x1000>, + <0x81 0x01628000 0x0 0x1000>, + <0x81 0x01629000 0x0 0x1000>, + <0x81 0x0162a000 0x0 0x1000>, + <0x81 0x0162b000 0x0 0x1000>, + <0x81 0x0162c000 0x0 0x1000>, + <0x81 0x0162d000 0x0 0x1000>, + <0x81 0x0162e000 0x0 0x1000>, + <0x81 0x0162f000 0x0 0x1000>, + <0x81 0x01630000 0x0 0x1000>, + <0x81 0x01631000 0x0 0x1000>, + <0x81 0x01632000 0x0 0x1000>, + <0x81 0x0163e000 0x0 0x1000>, + <0x81 0x0163f000 0x0 0x1000>, + <0x81 0x01642000 0x0 0x1000>, + <0x81 0x01643000 0x0 0x1000>, + <0x81 0x01644000 0x0 0x1000>, + <0x81 0x01645000 0x0 0x1000>, + <0x81 0x01646000 0x0 0x1000>, + <0x81 0x01647000 0x0 0x1000>, + <0x81 0x0164b000 0x0 0x1000>, + <0x81 0x0164f000 0x0 0x1000>, + <0x81 0x01653000 0x0 0x1000>, + <0x81 0x81604000 0x0 0x1000>, + <0x81 0x81605000 0x0 0x1000>, + <0x81 0x81606000 0x0 0x1000>, + <0x81 0x81607000 0x0 0x1000>, + <0x81 0x8160b000 0x0 0x1000>, + <0x81 0x8160c000 0x0 0x1000>, + <0x81 0x8160e000 0x0 0x1000>, + <0x81 0x8160f000 0x0 0x1000>, + <0x88 0x01601000 0x0 0x1000>, + <0x88 0x01602000 0x0 0x1000>, + <0xa8 0x01604000 0x0 0x1000>, + <0xa8 0x01628000 0x0 0x1000>, + <0xa8 0x01629000 0x0 0x1000>, + <0x00 0x01610000 0x0 0x2000>, + <0x00 0x01612000 0x0 0x1000>; + clocks = <&bpmp TEGRA264_CLK_LA>, + <&bpmp TEGRA264_CLK_SPLL_OUT7>; + clock-names = "la, parent"; + resets = <&bpmp TEGRA264_RESET_LA>, + <&bpmp TEGRA264_RESET_HWPM>; + reset-names = "la, hwpm"; + iommus = <&smmu1_mmu TEGRA_SID_PMA0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-SafetyServiceConfig.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-SafetyServiceConfig.yaml new file mode 100644 index 00000000..bab6d6e7 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-SafetyServiceConfig.yaml @@ -0,0 +1,79 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/SS_ErrorReportingConfig/nvidia,tegra-SafetyServiceConfig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-SafetyServiceConfig is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /SS_ErrorReportingConfig + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-SafetyServiceConfig + + required: + - compatible + +properties: + + Sw_Errors_count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + Sw_Errors: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x30 + maximum: 0x8120 + + TSC_MON_Enable: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + TSC_MON_Drift_Threshold: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x64 + maximum: 0x64 + + TSC_MON_Debounce_Delay: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1388 + maximum: 0x1388 + + TSC_MON_Sync_Timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2710 + maximum: 0x2710 + +required: + - compatible + +examples: + - | + SS_ErrorReportingConfig { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-bpmp-dummy.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-bpmp-dummy.yaml new file mode 100644 index 00000000..ad01202d --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-bpmp-dummy.yaml @@ -0,0 +1,64 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bpmp-dummy/nvidia,tegra-bpmp-dummy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-bpmp-dummy is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bpmp-dummy + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-bpmp-dummy + + required: + - compatible + +properties: + + '#clock-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#reset-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#power-domain-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + +required: + - compatible + +examples: + - | + bpmp-dummy { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-CcplexApp.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-CcplexApp.yaml new file mode 100644 index 00000000..88a0ffa1 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-CcplexApp.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/FsiComAppChConfCcplexApp/nvidia,tegra-fsicom-CcplexApp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-fsicom-CcplexApp is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /FsiComAppChConfCcplexApp + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-fsicom-CcplexApp + + required: + - compatible + +properties: + + channelid_list: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x2 + +required: + - compatible + +examples: + - | + FsiComAppChConfCcplexApp { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-EPD.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-EPD.yaml new file mode 100644 index 00000000..e1f6e75e --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-EPD.yaml @@ -0,0 +1,57 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/FsiComClientChConfigEpd/nvidia,tegra-fsicom-EPD.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-fsicom-EPD is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /FsiComClientChConfigEpd + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-fsicom-EPD + + required: + - compatible + +properties: + + channelid_list: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + +examples: + - | + FsiComClientChConfigEpd { + compatible = "nvidia,tegra-fsicom-EPD"; + status = "disabled"; + channelid_list = <0>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-channels.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-channels.yaml new file mode 100644 index 00000000..89fa66d7 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-channels.yaml @@ -0,0 +1,75 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/FsiComIvc/nvidia,tegra-fsicom-channels.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-fsicom-channels is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /FsiComIvc + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-fsicom-channels + + required: + - compatible + +properties: + + nChannel: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9 + maximum: 0x9 + + nvsciipc_endpoint: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvfsicom_EPD + - nvfsicom_CcplexApp + - nvfsicom_CcplexApp_state_change + - nvfsicom_app1 + - nvfsicom_app2 + - nvfsicom_appGR + + +required: + - compatible + +examples: + - | + FsiComIvc { + compatible = "nvidia,tegra-fsicom-channels"; + status = "disabled"; + nChannel = <9>; + nvsciipc_endpoint = "nvfsicom_EPD", + "nvfsicom_CcplexApp", + "nvfsicom_CcplexApp_state_change", + "nvfsicom_app1", + "nvfsicom_app2", + "nvfsicom_appGR"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleApp1.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleApp1.yaml new file mode 100644 index 00000000..eabdab71 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleApp1.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/FsiComAppChConfApp1/nvidia,tegra-fsicom-sampleApp1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-fsicom-sampleApp1 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /FsiComAppChConfApp1 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-fsicom-sampleApp1 + + required: + - compatible + +properties: + + channelid_list: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + +required: + - compatible + +examples: + - | + FsiComAppChConfApp1 { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleAppGR.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleAppGR.yaml new file mode 100644 index 00000000..5c187a92 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra-fsicom-sampleAppGR.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/FsiComQnxAppChConfAppGR/nvidia,tegra-fsicom-sampleAppGR.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-fsicom-sampleAppGR is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /FsiComQnxAppChConfAppGR + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-fsicom-sampleAppGR + + required: + - compatible + +properties: + + channelid_list: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + +required: + - compatible + +examples: + - | + FsiComQnxAppChConfAppGR { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-hsp-mailbox.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-hsp-mailbox.yaml new file mode 100644 index 00000000..bfc2efe4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-hsp-mailbox.yaml @@ -0,0 +1,85 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hsp-mbox/nvidia,tegra186-hsp-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-hsp-mailbox is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/pva0@818c000000/hsp/hsp-mbox + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-hsp-mailbox + + required: + - compatible + +properties: + + nvidia,hsp-shared-mailbox: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x7 + + nvidia,hsp-shared-mailbox-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - command + - addr + - len + - args + - sidechannel-wr + - aisr + - sidechannel-rd + - isr + + +required: + - compatible + +examples: + - | + hsp-mbox { + compatible = "nvidia,tegra186-hsp-mailbox"; + nvidia,hsp-shared-mailbox = <&hsp_pva0 0x0>, + <&hsp_pva0 0x1>, + <&hsp_pva0 0x2>, + <&hsp_pva0 0x3>, + <&hsp_pva0 0x4>, + <&hsp_pva0 0x5>, + <&hsp_pva0 0x6>, + <&hsp_pva0 0x7>; + nvidia,hsp-shared-mailbox-names = "command, addr, len, args, sidechannel-wr, aisr, sidechannel-rd, isr"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra194-pva0-hsp.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra194-pva0-hsp.yaml new file mode 100644 index 00000000..f1d2d20b --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra194-pva0-hsp.yaml @@ -0,0 +1,50 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hsp/nvidia,tegra194-pva0-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra194-pva0-hsp is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/pva0@818c000000/hsp + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra194-pva0-hsp + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + hsp { + compatible = "nvidia,tegra194-pva0-hsp"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-aconnect.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-aconnect.yaml new file mode 100644 index 00000000..681824ff --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-aconnect.yaml @@ -0,0 +1,95 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/aconnect@9000000/nvidia,tegra264-aconnect.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-aconnect is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-aconnect + - nvidia,tegra210-aconnect + + required: + - compatible + +properties: + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9c + maximum: 0xa4 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - ape + - apb2ape + + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + +required: + - compatible + - clocks + - clock-names + +examples: + - | + aconnect@9000000 { + compatible = "nvidia,tegra264-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA264_CLK_APE>, + <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "ape, apb2ape"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-adsp-audio-hv.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-adsp-audio-hv.yaml new file mode 100644 index 00000000..93e8c906 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-adsp-audio-hv.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/adsp_audio/nvidia,tegra264-adsp-audio-hv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-adsp-audio-hv is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000/adsp_audio + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-adsp-audio-hv + + required: + - compatible + +properties: + + nvidia,adma_ch_page: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + nvidia,adma_ch_start: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x31 + maximum: 0x31 + + nvidia,adma_ch_cnt: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + compr-ops: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + num-plugin: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + +required: + - compatible + +examples: + - | + adsp_audio { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-agic.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-agic.yaml new file mode 100644 index 00000000..1603d90d --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-agic.yaml @@ -0,0 +1,140 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller@9960000/nvidia,tegra264-agic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-agic is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000/interrupt-controller@9960000 + - /bus@0/aconnect@9000000/interrupt-controller@9970000 + - /bus@0/aconnect@9000000/interrupt-controller@9980000 + - /bus@0/aconnect@9000000/interrupt-controller@9990000 + - /bus@0/aconnect@9000000/interrupt-controller@99a0000 + - /bus@0/aconnect@9000000/interrupt-controller@99b0000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-agic + - nvidia,tegra210-agic + + required: + - compatible + +properties: + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9961000 + maximum: 0x99b2000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xf04 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xf04 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9c + maximum: 0x9c + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - clk + + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + interrupt-controller@9960000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9961000 0x0 0x1000>, + <0x0 0x9962000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-audio-graph-card.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-audio-graph-card.yaml new file mode 100644 index 00000000..c6313cda --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-audio-graph-card.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra264-audio-graph-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-audio-graph-card is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /sound + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-audio-graph-card + + required: + - compatible + +properties: + + nvidia,ahub-c2c-links: + $ref: "/schemas/types.yaml#/definitions/flag" + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9e + maximum: 0x9f + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pll_a + - plla_out0 + + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9e + maximum: 0x115 + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x9f + +required: + - compatible + - clocks + - clock-names + +examples: + - | + sound { + nvidia,ahub-c2c-links; + compatible = "nvidia,tegra264-audio-graph-card"; + clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + clock-names = "pll_a, plla_out0"; + assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>, + <&bpmp TEGRA264_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-i2c.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-i2c.yaml new file mode 100644 index 00000000..b377772a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-i2c.yaml @@ -0,0 +1,71 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/nvidia,tegra264-bpmp-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-bpmp-i2c is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bpmp/i2c + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-bpmp-i2c + - nvidia,tegra186-bpmp-i2c + + required: + - compatible + +properties: + + nvidia,bpmp-bus-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + +examples: + - | + i2c { + compatible = "nvidia,tegra264-bpmp-i2c", + "nvidia,tegra186-bpmp-i2c"; + status = "disabled"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-shmem.yaml new file mode 100644 index 00000000..3d859f56 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-bpmp-shmem.yaml @@ -0,0 +1,82 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bpmp-shmem@0/nvidia,tegra264-bpmp-shmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-bpmp-shmem is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /reserved-memory/bpmp-shmem@0 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-bpmp-shmem + - nvidia,tegra234-bpmp-shmem + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x86070000 + maximum: 0x86070000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000 + maximum: 0x2000 + + no-map: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + +examples: + - | + bpmp-shmem@0 { + compatible = "nvidia,tegra264-bpmp-shmem", + "nvidia,tegra234-bpmp-shmem"; + status = "disabled"; + reg = <0x0 0x86070000 0x0 0x2000>; + no-map; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-display-niso.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-display-niso.yaml new file mode 100644 index 00000000..3e94376a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-display-niso.yaml @@ -0,0 +1,72 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvdisplay-niso/nvidia,tegra264-display-niso.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-display-niso is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /display@8808c00000/nvdisplay-niso + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-display-niso + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x901 + maximum: 0x901 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - iommus + +examples: + - | + nvdisplay-niso { + compatible = "nvidia,tegra264-display-niso"; + iommus = <&smmu3_mmu 0x901>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-display.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-display.yaml new file mode 100644 index 00000000..48f2aa44 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-display.yaml @@ -0,0 +1,551 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display@8808c00000/nvidia,tegra264-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-display is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /display@8808c00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-display + + required: + - compatible + +properties: + + power-domains: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,num-dpaux-instance: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32" + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvdisplay + - dpaux0 + - hdacodec + - mipical + - vdisp + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8c00000 + maximum: 0x89840000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xfff + maximum: 0x1fffff + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvdisplay + - dpaux0 + - dpaux1 + - dpaux2 + - dpaux3 + - hdacodec + - vdisp + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf7 + maximum: 0x101 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1d3 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvdisplayhub_clk + - nvdisplay_disp_clk + - nvdisplay_p0_clk + - nvdisplay_p1_clk + - nvdisplay_p2_clk + - nvdisplay_p3_clk + - nvdisplay_p4_clk + - nvdisplay_p5_clk + - nvdisplay_p6_clk + - nvdisplay_p7_clk + - fuse_clk + - sppll0_clkouta_clk + - sppll0_clkoutb_clk + - sppll0_clkoutpn_clk + - sppll1_clkoutpn_clk + - sppll0_div27_clk + - sppll1_div27_clk + - vpll0_clk + - vpll1_clk + - vpll2_clk + - vpll3_clk + - vpll4_clk + - vpll5_clk + - vpll6_clk + - vpll7_clk + - rg0_clk + - rg1_clk + - rg2_clk + - rg3_clk + - rg4_clk + - rg5_clk + - rg6_clk + - rg7_clk + - disppll_clk + - pre_sor0_clk + - pre_sor1_clk + - pre_sor2_clk + - pre_sor3_clk + - dp_link_ref_clk + - dp_linkb_ref_clk + - dp_linkc_ref_clk + - dp_linkd_ref_clk + - sor_linka_input_clk + - sor_linkb_input_clk + - sor_linkc_input_clk + - sor_linkd_input_clk + - sor_linka_afifo_clk + - sor_linkb_afifo_clk + - sor_linkc_afifo_clk + - sor_linkd_afifo_clk + - sor0_clk + - sor1_clk + - sor2_clk + - sor3_clk + - sor_pad_input_clk + - sor_padb_input_clk + - sor_padc_input_clk + - sor_padd_input_clk + - sor0_pad_clk + - sor1_pad_clk + - sor2_pad_clk + - sor3_pad_clk + - sf0_clk + - sf1_clk + - sf2_clk + - sf3_clk + - sf4_clk + - sf5_clk + - sf6_clk + - sf7_clk + - sor0_ref_pll_clk + - sor1_ref_pll_clk + - sor2_ref_pll_clk + - sor3_ref_pll_clk + - sor0_ref_clk + - sor1_ref_clk + - sor2_ref_clk + - sor3_ref_clk + - osc_clk + - dsc_clk + - maud_clk + - aza_2xbit_clk + - disp_root + - vpllx_sor0_muxed_clk + - vpllx_sor1_muxed_clk + - vpllx_sor2_muxed_clk + - vpllx_sor3_muxed_clk + - sf0_sor_clk + - sf1_sor_clk + - sf2_sor_clk + - sf3_sor_clk + - sf4_sor_clk + - sf5_sor_clk + - sf6_sor_clk + - sf7_sor_clk + - dpaux0_clk + - emc_clk + + + nvidia,disp-sw-soc-chip-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2650 + maximum: 0x2650 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x1f + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dpaux0_reset + - hdacodec_reset + + + interconnects: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x182 + maximum: 0x182 + - $ref: "/schemas/types.yaml#/definitions/uint32" + + interconnect-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - read-1 + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x900 + maximum: 0x900 + + non-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + single_stage_iso_smmu: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupt-names + - interrupts + - clocks + - clock-names + - resets + - reset-names + - iommus + +examples: + - | + display@8808c00000 { + compatible = "nvidia,tegra264-display"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_DISP>; + nvidia,num-dpaux-instance = <0x00000004>; + nvidia,bpmp = <&bpmp>; + reg-names = "nvdisplay, dpaux0, hdacodec, mipical, vdisp"; + reg = <0x88 0x8c00000 0x00 0x1fffff>, + <0x88 0x9680000 0x00 0x7ffff>, + <0x88 0x9101000 0x00 0xfff>, + <0x81 0x89840000 0x00 0xffff>, + <0x88 0x8d00000 0x00 0x00010000>; + interrupt-names = "nvdisplay, dpaux0, dpaux1, dpaux2, dpaux3, hdacodec, vdisp"; + interrupts = , + , + , + , + , + , + ; + clocks = <&bpmp TEGRA264_CLK_HUB>, + <&bpmp TEGRA264_CLK_DISP>, + <&bpmp TEGRA264_CLK_RG0_DIV>, + <&bpmp TEGRA264_CLK_RG1_DIV>, + <&bpmp TEGRA264_CLK_RG2_DIV>, + <&bpmp TEGRA264_CLK_RG3_DIV>, + <&bpmp TEGRA264_CLK_RG4_DIV>, + <&bpmp TEGRA264_CLK_RG5_DIV>, + <&bpmp TEGRA264_CLK_RG6_DIV>, + <&bpmp TEGRA264_CLK_RG7_DIV>, + <&bpmp TEGRA264_CLK_FUSE>, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT1A>, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT2A>, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT270>, + <&bpmp TEGRA264_CLK_SPPLL1_CLKOUT270>, + <&bpmp TEGRA264_CLK_SPPLL0_CLKOUT100>, + <&bpmp TEGRA264_CLK_SPPLL1_CLKOUT100>, + <&bpmp TEGRA264_CLK_VPLL0>, + <&bpmp TEGRA264_CLK_VPLL1>, + <&bpmp TEGRA264_CLK_VPLL2>, + <&bpmp TEGRA264_CLK_VPLL3>, + <&bpmp TEGRA264_CLK_VPLL4>, + <&bpmp TEGRA264_CLK_VPLL5>, + <&bpmp TEGRA264_CLK_VPLL6>, + <&bpmp TEGRA264_CLK_VPLL7>, + <&bpmp TEGRA264_CLK_RG0>, + <&bpmp TEGRA264_CLK_RG1>, + <&bpmp TEGRA264_CLK_RG2>, + <&bpmp TEGRA264_CLK_RG3>, + <&bpmp TEGRA264_CLK_RG4>, + <&bpmp TEGRA264_CLK_RG5>, + <&bpmp TEGRA264_CLK_RG6>, + <&bpmp TEGRA264_CLK_RG7>, + <&bpmp TEGRA264_CLK_DISPPLL>, + <&bpmp TEGRA264_CLK_PRE_SOR0>, + <&bpmp TEGRA264_CLK_PRE_SOR1>, + <&bpmp TEGRA264_CLK_PRE_SOR2>, + <&bpmp TEGRA264_CLK_PRE_SOR3>, + <&bpmp TEGRA264_CLK_DP_LINKA_REF>, + <&bpmp TEGRA264_CLK_DP_LINKB_REF>, + <&bpmp TEGRA264_CLK_DP_LINKC_REF>, + <&bpmp TEGRA264_CLK_DP_LINKD_REF>, + <&bpmp TEGRA264_CLK_SOR_LINKA_INPUT>, + <&bpmp TEGRA264_CLK_SOR_LINKB_INPUT>, + <&bpmp TEGRA264_CLK_SOR_LINKC_INPUT>, + <&bpmp TEGRA264_CLK_SOR_LINKD_INPUT>, + <&bpmp TEGRA264_CLK_SOR_LINKA_AFIFO>, + <&bpmp TEGRA264_CLK_SOR_LINKB_AFIFO>, + <&bpmp TEGRA264_CLK_SOR_LINKC_AFIFO>, + <&bpmp TEGRA264_CLK_SOR_LINKD_AFIFO>, + <&bpmp TEGRA264_CLK_SOR0>, + <&bpmp TEGRA264_CLK_SOR1>, + <&bpmp TEGRA264_CLK_SOR2>, + <&bpmp TEGRA264_CLK_SOR3>, + <&bpmp TEGRA264_CLK_LINKA_SYM>, + <&bpmp TEGRA264_CLK_LINKB_SYM>, + <&bpmp TEGRA264_CLK_LINKC_SYM>, + <&bpmp TEGRA264_CLK_LINKD_SYM>, + <&bpmp TEGRA264_CLK_SOR0_PAD>, + <&bpmp TEGRA264_CLK_SOR1_PAD>, + <&bpmp TEGRA264_CLK_SOR2_PAD>, + <&bpmp TEGRA264_CLK_SOR3_PAD>, + <&bpmp TEGRA264_CLK_SF0>, + <&bpmp TEGRA264_CLK_SF1>, + <&bpmp TEGRA264_CLK_SF2>, + <&bpmp TEGRA264_CLK_SF3>, + <&bpmp TEGRA264_CLK_SF4>, + <&bpmp TEGRA264_CLK_SF5>, + <&bpmp TEGRA264_CLK_SF6>, + <&bpmp TEGRA264_CLK_SF7>, + <&bpmp TEGRA264_CLK_SOR0_PLL_REF>, + <&bpmp TEGRA264_CLK_SOR1_PLL_REF>, + <&bpmp TEGRA264_CLK_SOR2_PLL_REF>, + <&bpmp TEGRA264_CLK_SOR3_PLL_REF>, + <&bpmp TEGRA264_CLK_SOR0_REF>, + <&bpmp TEGRA264_CLK_SOR1_REF>, + <&bpmp TEGRA264_CLK_SOR2_REF>, + <&bpmp TEGRA264_CLK_SOR3_REF>, + <&bpmp TEGRA264_CLK_OSC>, + <&bpmp TEGRA264_CLK_DSC>, + <&bpmp TEGRA264_CLK_MAUD>, + <&bpmp TEGRA264_CLK_AZA_2XBIT>, + <&bpmp TEGRA264_CLK_DISP_ROOT>, + <&bpmp TEGRA264_CLK_VPLLX_SOR0_MUXED>, + <&bpmp TEGRA264_CLK_VPLLX_SOR1_MUXED>, + <&bpmp TEGRA264_CLK_VPLLX_SOR2_MUXED>, + <&bpmp TEGRA264_CLK_VPLLX_SOR3_MUXED>, + <&bpmp TEGRA264_CLK_SF0_SOR>, + <&bpmp TEGRA264_CLK_SF1_SOR>, + <&bpmp TEGRA264_CLK_SF2_SOR>, + <&bpmp TEGRA264_CLK_SF3_SOR>, + <&bpmp TEGRA264_CLK_SF4_SOR>, + <&bpmp TEGRA264_CLK_SF5_SOR>, + <&bpmp TEGRA264_CLK_SF6_SOR>, + <&bpmp TEGRA264_CLK_SF7_SOR>, + <&bpmp TEGRA264_CLK_DPAUX>, + <&bpmp TEGRA264_CLK_EMC>; + clock-names = "nvdisplayhub_clk", + "nvdisplay_disp_clk", + "nvdisplay_p0_clk", + "nvdisplay_p1_clk", + "nvdisplay_p2_clk", + "nvdisplay_p3_clk", + "nvdisplay_p4_clk", + "nvdisplay_p5_clk", + "nvdisplay_p6_clk", + "nvdisplay_p7_clk", + "fuse_clk", + "sppll0_clkouta_clk", + "sppll0_clkoutb_clk", + "sppll0_clkoutpn_clk", + "sppll1_clkoutpn_clk", + "sppll0_div27_clk", + "sppll1_div27_clk", + "vpll0_clk", + "vpll1_clk", + "vpll2_clk", + "vpll3_clk", + "vpll4_clk", + "vpll5_clk", + "vpll6_clk", + "vpll7_clk", + "rg0_clk", + "rg1_clk", + "rg2_clk", + "rg3_clk", + "rg4_clk", + "rg5_clk", + "rg6_clk", + "rg7_clk", + "disppll_clk", + "pre_sor0_clk", + "pre_sor1_clk", + "pre_sor2_clk", + "pre_sor3_clk", + "dp_link_ref_clk", + "dp_linkb_ref_clk", + "dp_linkc_ref_clk", + "dp_linkd_ref_clk", + "sor_linka_input_clk", + "sor_linkb_input_clk", + "sor_linkc_input_clk", + "sor_linkd_input_clk", + "sor_linka_afifo_clk", + "sor_linkb_afifo_clk", + "sor_linkc_afifo_clk", + "sor_linkd_afifo_clk", + "sor0_clk", + "sor1_clk", + "sor2_clk", + "sor3_clk", + "sor_pad_input_clk", + "sor_padb_input_clk", + "sor_padc_input_clk", + "sor_padd_input_clk", + "sor0_pad_clk", + "sor1_pad_clk", + "sor2_pad_clk", + "sor3_pad_clk", + "sf0_clk", + "sf1_clk", + "sf2_clk", + "sf3_clk", + "sf4_clk", + "sf5_clk", + "sf6_clk", + "sf7_clk", + "sor0_ref_pll_clk", + "sor1_ref_pll_clk", + "sor2_ref_pll_clk", + "sor3_ref_pll_clk", + "sor0_ref_clk", + "sor1_ref_clk", + "sor2_ref_clk", + "sor3_ref_clk", + "osc_clk", + "dsc_clk", + "maud_clk", + "aza_2xbit_clk", + "disp_root", + "vpllx_sor0_muxed_clk", + "vpllx_sor1_muxed_clk", + "vpllx_sor2_muxed_clk", + "vpllx_sor3_muxed_clk", + "sf0_sor_clk", + "sf1_sor_clk", + "sf2_sor_clk", + "sf3_sor_clk", + "sf4_sor_clk", + "sf5_sor_clk", + "sf6_sor_clk", + "sf7_sor_clk", + "dpaux0_clk", + "emc_clk"; + nvidia,disp-sw-soc-chip-id = <0x2650>; + resets = <&bpmp TEGRA264_RESET_DPAUX>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names = "dpaux0_reset, hdacodec_reset"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_DISPR &emc>; + interconnect-names = "read-1"; + status = "disabled"; + iommus = <&smmu3_mmu 0x900>; + non-coherent; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-hda.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-hda.yaml new file mode 100644 index 00000000..c4fc22c0 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-hda.yaml @@ -0,0 +1,165 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hda@88090b0000/nvidia,tegra264-hda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-hda is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/hda@88090b0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-hda + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x90b0000 + maximum: 0x90b0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xfb + maximum: 0xfb + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8f + maximum: 0x8f + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - hda + + + interconnects: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x17c + maximum: 0x17d + - $ref: "/schemas/types.yaml#/definitions/uint32" + + interconnect-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dma-mem + - write + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa00 + maximum: 0xa00 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + +examples: + - | + hda@88090b0000 { + compatible = "nvidia,tegra264-hda"; + reg = <0x88 0x90b0000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names = "hda"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem, write"; + iommus = <&smmu3_mmu TEGRA_SID_HDA>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-isp-thi.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-isp-thi.yaml new file mode 100644 index 00000000..c8a4a8a1 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-isp-thi.yaml @@ -0,0 +1,82 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/isp-thi@8188b00000/nvidia,tegra264-isp-thi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-isp-thi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-isp-thi + + required: + - compatible + +properties: + + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-isp-thi + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x37 + maximum: 0x37 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - isp_thi + - isp1_thi + + +required: + - compatible + - resets + - reset-names + +examples: + - | + isp-thi@8188b00000 { + compatible = "nvidia,tegra264-isp-thi"; + resets = <&bpmp TEGRA264_RESET_ISP1>; + reset-names = "isp_thi"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-mixer-control.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-mixer-control.yaml new file mode 100644 index 00000000..7dea78ac --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-mixer-control.yaml @@ -0,0 +1,52 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mixer-controls/nvidia,tegra264-mixer-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-mixer-control is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /sound/mixer-controls + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-mixer-control + - nvidia,tegra234-mixer-control + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + mixer-controls { + compatible = "nvidia,tegra264-mixer-control", + "nvidia,tegra234-mixer-control"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-rce.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-rce.yaml new file mode 100644 index 00000000..3587789b --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-rce.yaml @@ -0,0 +1,293 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtcpu@81893d0000/nvidia,tegra264-rce.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-rce is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /rtcpu@81893d0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-rce + + required: + - compatible + +properties: + + nvidia,cpu-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rce + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x893d0000 + maximum: 0x893d0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rce-pm + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x23 + maximum: 0x24 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rce-nic + - rce-cpu + + + nvidia,clock-rates: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6ddd000 + maximum: 0x6ddd000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1bc69880 + maximum: 0x1bc69880 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rce-all + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x19e + maximum: 0x19e + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - wdt-remote + + + nvidia,camera-devices: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 5 + maxItems: 5 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,camera-device-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - isp + - vi0 + - vi1 + - nvcsi + - isp1 + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2b01 + maximum: 0x2b01 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,test-bw: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x249f00 + maximum: 0x249f00 + + nvidia,trace: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x70100000 + maximum: 0x70100000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100000 + maximum: 0x100000 + + nvidia,ivc-channels: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x90000000 + maximum: 0x90000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + nvidia,autosuspend-delay-ms: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1388 + maximum: 0x1388 + + nvidia,cmd-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7d0 + maximum: 0x7d0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - iommus + +examples: + - | + rtcpu@81893d0000 { + compatible = "nvidia,tegra264-rce"; + nvidia,cpu-name = "rce"; + reg = <0x81 0x893d0000 0x0 0x10000>; + reg-names = "rce-pm"; + clocks = <&bpmp TEGRA264_CLK_RCE_NIC>, + <&bpmp TEGRA264_CLK_RCE_CPU>; + clock-names = "rce-nic, rce-cpu"; + nvidia,clock-rates = <115200000 466000000>, + <115200000 466000000>; + resets = <&bpmp TEGRA264_RESET_RCE_ALL>; + reset-names = "rce-all"; + interrupts = ; + interrupt-names = "wdt-remote"; + nvidia,camera-devices = <&isp &vi0 &vi1 &nvcsi &isp1>; + nvidia,camera-device-names = "isp, vi0, vi1, nvcsi, isp1"; + iommus = <&smmu4_mmu TEGRA_SID_RCE_VM1>; + memory-region = <&rce_resv>; + dma-coherent; + nvidia,test-bw = <2400000>; + nvidia,trace = <&tegra_rtcpu_trace 4 0x70100000 0x100000>; + nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>; + nvidia,autosuspend-delay-ms = <5000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-rtc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-rtc.yaml new file mode 100644 index 00000000..e68ffb4b --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-rtc.yaml @@ -0,0 +1,130 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc@c2c0000/nvidia,tegra264-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-rtc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/rtc@c2c0000 + +select: + properties: + compatible: + minItems: 3 + maxItems: 3 + items: + enum: + - nvidia,tegra264-rtc + - nvidia,tegra234-rtc + - nvidia,tegra20-rtc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc2c0000 + maximum: 0xc2c0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x41 + maximum: 0x41 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rtc + + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + rtc@c2c0000 { + compatible = "nvidia,tegra264-rtc", + "nvidia,tegra234-rtc", + "nvidia,tegra20-rtc"; + status = "disabled"; + reg = <0x0 0x0c2c0000 0x0 0x10000>; + interrupt-parent = <&pmc>; + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA264_CLK_CLK_S>; + clock-names = "rtc"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-tsec.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-tsec.yaml new file mode 100644 index 00000000..09b401f0 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-tsec.yaml @@ -0,0 +1,167 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tsec@8188150000/nvidia,tegra264-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-tsec is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/tsec@8188150000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-tsec + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88150000 + maximum: 0x88150000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1bf + maximum: 0x1bf + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2d + maximum: 0x2d + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x30 + maximum: 0xc8 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tsec + - efuse + - tsec_pka + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2900 + maximum: 0x2900 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - resets + - clocks + - clock-names + - iommus + +examples: + - | + tsec@8188150000 { + compatible = "nvidia,tegra264-tsec"; + reg = <0x81 0x88150000 0x00 0x40000>; + interrupts = ; + resets = <&bpmp TEGRA264_RESET_TSEC>; + clocks = <&bpmp TEGRA264_CLK_TSEC>, + <&bpmp TEGRA264_CLK_FUSE>, + <&bpmp TEGRA264_CLK_TSEC_PKA>; + clock-names = "tsec, efuse, tsec_pka"; + iommus = <&smmu4_mmu TEGRA_SID_TSEC>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra264-virt-pcm-oot.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra264-virt-pcm-oot.yaml new file mode 100644 index 00000000..6e1ad433 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra264-virt-pcm-oot.yaml @@ -0,0 +1,144 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/virt-alt-pcm-oot/nvidia,tegra264-virt-pcm-oot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-virt-pcm-oot is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /virt-alt-pcm-oot + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-virt-pcm-oot + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + cardname: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tegra-virt-pcm-vm1 + + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x82 + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx1 + - tx1 + - rx2 + - tx2 + - rx3 + - tx3 + - rx4 + - tx4 + - rx5 + - tx5 + - rx6 + - tx6 + - rx7 + - tx7 + - rx8 + - tx8 + - rx9 + - tx9 + - rx10 + - tx10 + - rx11 + - tx11 + - rx12 + - tx12 + - rx13 + - tx13 + - rx14 + - tx14 + - rx15 + - tx15 + - rx16 + - tx16 + - rx17 + - tx17 + - rx18 + - tx18 + - rx19 + - tx19 + - rx20 + - tx20 + - rx21 + - tx21 + - rx22 + - tx22 + - rx23 + - tx23 + - rx24 + - tx24 + + + ivc_queue: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0xa2 + + admaif_ch_num: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x18 + maximum: 0x18 + + admaif_ch_list: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x18 + +required: + - compatible + - iommus + +examples: + - | + virt-alt-pcm-oot { + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra26x-ist.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra26x-ist.yaml new file mode 100644 index 00000000..7bcfd3da --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra26x-ist.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_ist/nvidia,tegra26x-ist.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra26x-ist is mentioned in the following drivers + - /kernel/kernel-oot/drivers/misc/nv_ist.c + + The following nodes use this compatibility + - /tegra_ist + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra26x-ist + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + tegra_ist { + compatible = "nvidia,tegra26x-ist"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epc.yaml b/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epc.yaml new file mode 100644 index 00000000..aabf3182 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epc.yaml @@ -0,0 +1,97 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvscic2c-pcie-s0-c5-epc/nvidia,tegra-nvscic2c-pcie-epc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-nvscic2c-pcie-epc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/dt.c + + The following nodes use this compatibility + - /nvscic2c-pcie-s0-c5-epc + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-nvscic2c-pcie-epc + + required: + - compatible + +properties: + + nvidia,host1x: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x19 + maximum: 0x19 + + nvidia,pcie-edma: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7b + maximum: 0x7b + + nvidia,pci-dev-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x22cc + maximum: 0x22cc + + nvidia,board-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,soc-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,cntrlr-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x5 + + nvidia,endpoint-db: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvscic2c_pcie_s0_c5_1, 16, 00032768, 67108864, 26001 + - nvscic2c_pcie_s0_c5_2, 16, 00032768, 67108864, 26002 + - nvscic2c_pcie_s0_c5_3, 16, 00032768, 67108864, 26003 + - nvscic2c_pcie_s0_c5_4, 16, 00032768, 67108864, 26004 + - nvscic2c_pcie_s0_c5_5, 16, 00032768, 67108864, 26005 + - nvscic2c_pcie_s0_c5_6, 16, 00032768, 67108864, 26006 + - nvscic2c_pcie_s0_c5_7, 16, 00032768, 67108864, 26007 + - nvscic2c_pcie_s0_c5_8, 16, 00032768, 67108864, 26008 + - nvscic2c_pcie_s0_c5_9, 16, 00032768, 67108864, 26009 + - nvscic2c_pcie_s0_c5_10, 16, 00032768, 67108864, 26010 + - nvscic2c_pcie_s0_c5_11, 16, 00032768, 67108864, 26011 + - nvscic2c_pcie_s0_c5_12, 16, 00000064, 0, 26012 + + +required: + - compatible + +examples: + - | + nvscic2c-pcie-s0-c5-epc { + }; diff --git a/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epf.yaml b/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epf.yaml new file mode 100644 index 00000000..91b47157 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvscic2c-pcie/nvidia,tegra-nvscic2c-pcie-epf.yaml @@ -0,0 +1,102 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvscic2c-pcie-s0-c4-epf/nvidia,tegra-nvscic2c-pcie-epf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-nvscic2c-pcie-epf is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/nvscic2c-pcie/dt.c + + The following nodes use this compatibility + - /nvscic2c-pcie-s0-c4-epf + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-nvscic2c-pcie-epf + + required: + - compatible + +properties: + + nvidia,host1x: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x19 + maximum: 0x19 + + nvidia,pcie-edma: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7c + maximum: 0x7c + + nvidia,pci-dev-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x22cc + maximum: 0x22cc + + nvidia,board-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,soc-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,cntrlr-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x5 + + nvidia,bar-win-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000000 + maximum: 0x40000000 + + nvidia,endpoint-db: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvscic2c_pcie_s0_c4_1, 16, 00032768, 67108864, 26101 + - nvscic2c_pcie_s0_c4_2, 16, 00032768, 67108864, 26102 + - nvscic2c_pcie_s0_c4_3, 16, 00032768, 67108864, 26103 + - nvscic2c_pcie_s0_c4_4, 16, 00032768, 67108864, 26104 + - nvscic2c_pcie_s0_c4_5, 16, 00032768, 67108864, 26105 + - nvscic2c_pcie_s0_c4_6, 16, 00032768, 67108864, 26106 + - nvscic2c_pcie_s0_c4_7, 16, 00032768, 67108864, 26107 + - nvscic2c_pcie_s0_c4_8, 16, 00032768, 67108864, 26108 + - nvscic2c_pcie_s0_c4_9, 16, 00032768, 67108864, 26109 + - nvscic2c_pcie_s0_c4_10, 16, 00032768, 67108864, 26110 + - nvscic2c_pcie_s0_c4_11, 16, 00032768, 67108864, 26111 + - nvscic2c_pcie_s0_c4_12, 16, 00000064, 0, 26112 + + +required: + - compatible + +examples: + - | + nvscic2c-pcie-s0-c4-epf { + }; diff --git a/Documentation/devicetree/bindings/misc/sha-carveout.yaml b/Documentation/devicetree/bindings/misc/sha-carveout.yaml new file mode 100644 index 00000000..5a985cab --- /dev/null +++ b/Documentation/devicetree/bindings/misc/sha-carveout.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sha-carveout/sha-carveout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = sha-carveout is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/misc/driver.c + + The following nodes use this compatibility + - /dce@8808000000/sha-carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - sha-carveout + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + sha-carveout { + compatible = "sha-carveout"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/mmc/host/nvidia,tegra264-sdhci.yaml b/Documentation/devicetree/bindings/mmc/host/nvidia,tegra264-sdhci.yaml new file mode 100644 index 00000000..9b8a0a31 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/host/nvidia,tegra264-sdhci.yaml @@ -0,0 +1,309 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sdhci@810c570000/nvidia,tegra264-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-sdhci is mentioned in the following drivers + - /kernel/kernel-oot/drivers/mmc/host/sdhci-tegra.c + + The following nodes use this compatibility + - /bus@0/sdhci@810c570000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-sdhci + - nvidia,tegra194-sdhci + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc570000 + maximum: 0xc570000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa2 + maximum: 0xa2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + sd-uhs-sdr104: + $ref: "/schemas/types.yaml#/definitions/flag" + + sd-uhs-sdr50: + $ref: "/schemas/types.yaml#/definitions/flag" + + sd-uhs-sdr25: + $ref: "/schemas/types.yaml#/definitions/flag" + + sd-uhs-sdr12: + $ref: "/schemas/types.yaml#/definitions/flag" + + mmc-hs200-1_8v: + $ref: "/schemas/types.yaml#/definitions/flag" + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1200 + maximum: 0x1200 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,pad-autocal-pull-up-offset-3v3-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + nvidia,pad-autocal-pull-down-offset-3v3-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + nvidia,pad-autocal-pull-up-offset-1v8-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6 + maximum: 0x6 + + nvidia,pad-autocal-pull-down-offset-1v8-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + nvidia,pad-autocal-pull-up-offset-sdr104: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,pad-autocal-pull-down-offset-sdr104: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + interconnects: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1c2 + maximum: 0x1c3 + - $ref: "/schemas/types.yaml#/definitions/uint32" + + interconnect-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dma-mem + - write + + + pinctrl-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - sdmmc-3v3 + - sdmmc-1v8 + + + pinctrl-0: + $ref: "/schemas/types.yaml#/definitions/uint32" + + pinctrl-1: + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,default-tap: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6 + maximum: 0x6 + + nvidia,default-trim: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x95 + maximum: 0x96 + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x93 + maximum: 0x95 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x22 + maximum: 0x22 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - sdhci + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x96 + maximum: 0x97 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - sdhci + - tmclk + + +required: + - compatible + - reg + - interrupts + - iommus + - resets + - reset-names + - clocks + - clock-names + +examples: + - | + sdhci@810c570000 { + compatible = "nvidia,tegra264-sdhci, nvidia,tegra194-sdhci"; + status = "disabled"; + reg = <0x81 0xc570000 0x00 0x10000>; + interrupts = ; + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + mmc-hs200-1_8v; + iommus = <&smmu2_mmu TEGRA_SID_SDMMC0>; + dma-coherent; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_SDMMC0R &emc>, + <&mc TEGRA264_MEMORY_CLIENT_SDMMC0W &emc>; + interconnect-names = "dma-mem, write"; + pinctrl-names = "sdmmc-3v3, sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + nvidia,default-tap = <6>; + nvidia,default-trim = <0>; + assigned-clocks = <&bpmp TEGRA264_CLK_SDMMC1>, + <&bpmp TEGRA264_CLK_PLLC4_MUXED>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLC4_MUXED>, + <&bpmp TEGRA264_CLK_PLLC4_OUT0>; + resets = <&bpmp TEGRA264_RESET_SDMMC1>; + reset-names = "sdhci"; + clocks = <&bpmp TEGRA264_CLK_SDMMC1>, + <&bpmp TEGRA264_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci, tmclk"; + }; diff --git a/Documentation/devicetree/bindings/mtd/devices/nvidia,tegra-virt-mtd-storage.yaml b/Documentation/devicetree/bindings/mtd/devices/nvidia,tegra-virt-mtd-storage.yaml new file mode 100644 index 00000000..d92a1381 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/devices/nvidia,tegra-virt-mtd-storage.yaml @@ -0,0 +1,86 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_virt_storage83/nvidia,tegra-virt-mtd-storage.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-virt-mtd-storage is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/mtd/devices/tegra_hv_mtd.c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-virt-mtd-storage + + required: + - compatible + +properties: + + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-virt-mtd-storage + + instance: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + ivc: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0x3f + + read-only: + $ref: "/schemas/types.yaml#/definitions/flag" + + mempool: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x17 + maximum: 0x17 + + partition-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - board-info + + +required: + - compatible + +examples: + - | + tegra_virt_storage83 { + compatible = "nvidia,tegra-virt-mtd-storage"; + status = "okay"; + instance = <0x00000000>; + ivc = <0x0000000f>, + <0x0000003f>; + read-only; + mempool = <0x00000017>; + partition-name = "board-info"; + }; diff --git a/Documentation/devicetree/bindings/mtd/spi-nor/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/spi-nor/jedec,spi-nor.yaml new file mode 100644 index 00000000..98b83a78 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spi-nor/jedec,spi-nor.yaml @@ -0,0 +1,80 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/flash@0/jedec,spi-nor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = jedec,spi-nor is mentioned in the following drivers + - /kernel/kernel-oot/drivers/mtd/spi-nor/core.c + - /kernel/kernel-oot/drivers/memory/renesas-rpc-if.c + + The following nodes use this compatibility + - /bus@0/spi@810c5b0000/flash@0 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - jedec,spi-nor + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + spi-max-frequency: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6146580 + maximum: 0x6146580 + + spi-rx-bus-width: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + spi-tx-bus-width: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + +required: + - compatible + - reg + +examples: + - | + flash@0 { + }; diff --git a/Documentation/devicetree/bindings/net/can/mttcan/native/nvidia,tegra264-mttcan.yaml b/Documentation/devicetree/bindings/net/can/mttcan/native/nvidia,tegra264-mttcan.yaml new file mode 100644 index 00000000..dc5459bf --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/mttcan/native/nvidia,tegra264-mttcan.yaml @@ -0,0 +1,186 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mttcan@81102f0000/nvidia,tegra264-mttcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-mttcan is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/net/can/mttcan/native/m_ttcan_linux.c + + The following nodes use this compatibility + - /bus@0/mttcan@81102f0000 + - /bus@0/mttcan@8110300000 + - /bus@0/mttcan@8110330000 + - /bus@0/mttcan@8110340000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-mttcan + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x102f0000 + maximum: 0x10342000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x32 + maximum: 0x1000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - can-regs + - glue-regs + - msg-ram + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x44 + maximum: 0x4a + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + mram-params: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 9 + maxItems: 9 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20 + maximum: 0x20 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + + tx-config: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + + rx-config: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + +required: + - compatible + - reg + - interrupts + +examples: + - | + mttcan@81102f0000 { + compatible = "nvidia,tegra264-mttcan"; + reg = <0x81 0x102f0000 0x00 0x144>, + <0x81 0x102f1000 0x00 0x32>, + <0x81 0x102f2000 0x00 0x1000>; + reg-names = "can-regs, glue-regs, msg-ram"; + interrupts = ; + mram-params = <0 16 16 32 0 0 16 16 16>; + tx-config = <0 16 0 64>; + rx-config = <64 64 64>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/nvmem/nvidia,tegra264-efuse.yaml b/Documentation/devicetree/bindings/nvmem/nvidia,tegra264-efuse.yaml new file mode 100644 index 00000000..7764ec1c --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/nvidia,tegra264-efuse.yaml @@ -0,0 +1,103 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/efuse@1000000/nvidia,tegra264-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-efuse is mentioned in the following drivers + - /kernel/kernel-oot/drivers/nvmem/tegra-efuse.c + + The following nodes use this compatibility + - /bus@0/efuse@1000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-efuse + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000000 + maximum: 0x1000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x20000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc8 + maximum: 0xc8 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - fuse + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + efuse@1000000 { + compatible = "nvidia,tegra264-efuse", + "nvidia,tegra234-efuse"; + status = "disabled"; + reg = <0x0 0x01000000 0x0 0x20000>; + clocks = <&bpmp TEGRA264_CLK_FUSE>; + clock-names = "fuse"; + }; diff --git a/Documentation/devicetree/bindings/nvpmodel/nvidia,nvpmodel.yaml b/Documentation/devicetree/bindings/nvpmodel/nvidia,nvpmodel.yaml new file mode 100644 index 00000000..ed4e02dc --- /dev/null +++ b/Documentation/devicetree/bindings/nvpmodel/nvidia,nvpmodel.yaml @@ -0,0 +1,81 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvpmodel/nvidia,nvpmodel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,nvpmodel is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/nvpmodel/nvpmodel-clk-cap.c + + The following nodes use this compatibility + - /nvpmodel + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,nvpmodel + + required: + - compatible + +properties: + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32" + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x122 + maximum: 0x122 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - emc + + +required: + - compatible + - clocks + - clock-names + +examples: + - | + nvpmodel { + compatible = "nvidia,nvpmodel"; + status = "disabled"; + nvidia,bpmp = <&bpmp>; + clocks = <&bpmp TEGRA264_CLK_EMC>; + clock-names = "emc"; + }; diff --git a/Documentation/devicetree/bindings/nvpps/nvidia,tegra264-nvpps.yaml b/Documentation/devicetree/bindings/nvpps/nvidia,tegra264-nvpps.yaml new file mode 100644 index 00000000..e321cb71 --- /dev/null +++ b/Documentation/devicetree/bindings/nvpps/nvidia,tegra264-nvpps.yaml @@ -0,0 +1,84 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvpps/nvidia,tegra264-nvpps.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-nvpps is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/nvpps/nvpps_main.c + + The following nodes use this compatibility + - /nvpps + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-nvpps + + required: + - compatible + +properties: + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xc230000 + + primary-emac: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x83 + maximum: 0x83 + + sec-emac: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x84 + maximum: 0x84 + +required: + - compatible + - reg + +examples: + - | + nvpps { + }; diff --git a/Documentation/devicetree/bindings/of/ramoops.yaml b/Documentation/devicetree/bindings/of/ramoops.yaml new file mode 100644 index 00000000..ebaa28e0 --- /dev/null +++ b/Documentation/devicetree/bindings/of/ramoops.yaml @@ -0,0 +1,116 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ramoops_carveout/ramoops.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = ramoops is mentioned in the following drivers + - /kernel/kernel-oot/drivers/of/platform.c + - /kernel/kernel-oot/drivers/platform/chrome/chromeos_pstore.c + + The following nodes use this compatibility + - /reserved-memory/ramoops_carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - ramoops + + required: + - compatible + +properties: + + size: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x200000 + maximum: 0x200000 + + record-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + console-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000 + maximum: 0x80000 + + alignment: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + alloc-ranges: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + no-map: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + +examples: + - | + ramoops_carveout { + compatible = "ramoops"; + status = "disabled"; + size = <0x0 0x200000>; + record-size = <0x00010000>; + console-size = <0x00080000>; + alignment = <0x0 0x10000>; + alloc-ranges = <0x0 0x0 0x1 0x0>; + no-map; + }; diff --git a/Documentation/devicetree/bindings/of/shared-dma-pool.yaml b/Documentation/devicetree/bindings/of/shared-dma-pool.yaml new file mode 100644 index 00000000..a66f5fbe --- /dev/null +++ b/Documentation/devicetree/bindings/of/shared-dma-pool.yaml @@ -0,0 +1,87 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/linux,cma/shared-dma-pool.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = shared-dma-pool is mentioned in the following drivers + - /kernel/kernel-oot/drivers/of/of_reserved_mem.c + + The following nodes use this compatibility + - /reserved-memory/linux,cma + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - shared-dma-pool + + required: + - compatible + +properties: + + reusable: + $ref: "/schemas/types.yaml#/definitions/flag" + + size: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4000000 + maximum: 0x4000000 + + alignment: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + linux,cma-default: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + +examples: + - | + linux,cma { + compatible = "shared-dma-pool"; + status = "disabled"; + reusable; + size = <0x0 0x4000000>; + alignment = <0x0 0x10000>; + linux,cma-default; + }; diff --git a/Documentation/devicetree/bindings/pci/controller/arm,gic-v3-its.yaml b/Documentation/devicetree/bindings/pci/controller/arm,gic-v3-its.yaml new file mode 100644 index 00000000..2a5a8404 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/controller/arm,gic-v3-its.yaml @@ -0,0 +1,95 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/its@8146040000/arm,gic-v3-its.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,gic-v3-its is mentioned in the following drivers + - /kernel/kernel-oot/drivers/pci/controller/pcie-iproc.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-platform-msi.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-pci-msi.c + + The following nodes use this compatibility + - /interrupt-controller@8146000000/its@8146040000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,gic-v3-its + + required: + - compatible + +properties: + + msi-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#msi-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x46040000 + maximum: 0x46040000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + +examples: + - | + its@8146040000 { + compatible = "arm,gic-v3-its"; + status = "disabled"; + msi-controller; + reg = <0x81 0x46040000 0x0 0x40000>; + numa-node-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/pci/controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/pci/controller/arm,gic-v3.yaml new file mode 100644 index 00000000..ca10af2d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/controller/arm,gic-v3.yaml @@ -0,0 +1,153 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller@8146000000/arm,gic-v3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,gic-v3 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/pci/controller/pcie-iproc.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-platform-msi.c + - /kernel/kernel-oot/drivers/irqchip/irq-ti-sci-inta.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3-its-pci-msi.c + - /kernel/kernel-oot/drivers/irqchip/irq-gic-v3.c + - /kernel/kernel-oot/drivers/irqchip/irq-ti-sci-intr.c + + The following nodes use this compatibility + - /interrupt-controller@8146000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,gic-v3 + + required: + - compatible + +properties: + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#redistributor-regions': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x46000000 + maximum: 0x46080000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x400000 + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9 + maximum: 0x9 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + redistributor-stride: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + +required: + - compatible + - reg + - interrupts + +examples: + - | + interrupt-controller@8146000000 { + compatible = "arm,gic-v3"; + status = "disabled"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x81 0x46000000 0x0 0x010000>, + <0x81 0x46080000 0x0 0x00400000>; + interrupt-parent = <&gic>; + interrupts = ; + redistributor-stride = <0x00 0x40000>; + ranges; + }; diff --git a/Documentation/devicetree/bindings/pci/controller/pci-host-ecam-generic.yaml b/Documentation/devicetree/bindings/pci/controller/pci-host-ecam-generic.yaml new file mode 100644 index 00000000..13d3461a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/controller/pci-host-ecam-generic.yaml @@ -0,0 +1,207 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pcie@a8b0000000/pci-host-ecam-generic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = pci-host-ecam-generic is mentioned in the following drivers + - /kernel/kernel-oot/drivers/pci/controller/pci-host-generic.c + + The following nodes use this compatibility + - /bus@0/pcie@a8b0000000 + - /bus@0/pcie@b0b0000000 + - /bus@0/pcie@b8b0000000 + - /bus@0/pcie@c0b0000000 + - /bus@0/pcie@c8b0000000 + - /bus@0/pcie@d0b0000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - pci-host-ecam-generic + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xd0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8520000 + maximum: 0xb0000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - ecam + - xdma + + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + device_type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pci + + + linux,pci-domain: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + interrupt-map-mask: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + iommu-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x50000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + msi-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x110000 + maximum: 0x210000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + bus-range: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xff + maximum: 0xff + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + ats-supported: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + +examples: + - | + pcie@a8b0000000 { + status = "disabled"; + compatible = "pci-host-ecam-generic"; + reg = <0xa8 0xb0000000 0x0 0x10000000>; + reg-names = "ecam"; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + linux,pci-domain = <0x1>; + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x38c IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x38d IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x38e IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x38f IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0x0 &smmu1_mmu 0x10000 0x10000>; + dma-coherent; + msi-map = <0x0 &its 0x110000 0x10000>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x00 0x28000000 0x00 0x28000000 0x0 0x080000000xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x7 0xc00000000x81000000 0xa8 0x82000000 0xa8 0x82000000 0x0 0x00200000>; + numa-node-id = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie-ep.yaml new file mode 100644 index 00000000..049c1d5b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie-ep.yaml @@ -0,0 +1,230 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pcie-ep@a808420000/nvidia,tegra264-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pcie-ep is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/pci/controller/private-soc/pcie-tegra264-ep.c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pcie-ep + + required: + - compatible + +properties: + + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pcie-ep + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xc8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8420000 + maximum: 0x80000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x10000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - xal + - xal-ep-dm + - xtl-ep-pri + - xtl-ep-cfg + - xdma + - xpl + - addr_space + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x392 + maximum: 0x3ad + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - intr + + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + pinctrl-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - default + + + pinctrl-0: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1d + maximum: 0x1d + + reset-gpios: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xb + maximum: 0x1b + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x50000 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + msi-parent: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x120000 + maximum: 0x150000 + + linux,pci-domain: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x5 + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x5 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,pex-prsnt-gpios: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1e + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + pcie-ep@a808420000 { + status = "disabled"; + compatible = "nvidia,tegra264-pcie-ep"; + reg = <0xa8 0x08420000 0x0 0x00004000>, + <0xa8 0x08500000 0x0 0x00001000>, + <0xa8 0x08510000 0x0 0x00001000>, + <0xa8 0x08511000 0x0 0x00001000>, + <0xa8 0x08520000 0x0 0x00010000>, + <0xa8 0x08430000 0x0 0x00010000>, + <0xb0 0x80000000 0x8 0x00000000>; + reg-names = "xal, xal-ep-dm, xtl-ep-pri, xtl-ep-cfg, xdma, xpl, addr_space"; + interrupts = ; + interrupt-names = "intr"; + #address-cells = <0x3>; + #size-cells = <0x2>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c2_in_state>; + reset-gpios = <&gpio_uphy TEGRA264_UPHY_GPIO(B3) GPIO_ACTIVE_LOW>; + iommus = <&smmu1_mmu 0x20000>; + dma-coherent; + msi-parent = <&its 0x120000>; + linux,pci-domain = <0x2>; + nvidia,bpmp = <&bpmp 0x2>; + numa-node-id = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie.yaml new file mode 100644 index 00000000..a7c8dd16 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/controller/private-soc/nvidia,tegra264-pcie.yaml @@ -0,0 +1,233 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pcie@810c000000/nvidia,tegra264-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pcie is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/pci/controller/private-soc/pcie-tegra264-ep.c + - /kernel/nvidia-oot/drivers/pci/controller/private-soc/pcie-tegra264.c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pcie + + required: + - compatible + +properties: + + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pcie + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0xd0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8400000 + maximum: 0xb0000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x10000000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - xal + - xtl + - xtl-pri + - ecam + - xpl + - xdma + + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3 + maximum: 0x3 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + device_type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pci + + + linux,pci-domain: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + interrupt-map-mask: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + + iommu-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x50000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + msi-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x110000 + maximum: 0x210000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + bus-range: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xff + maximum: 0xff + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x5 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + ats-supported: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,host1x: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x19 + maximum: 0x19 + +required: + - compatible + - reg + +examples: + - | + pcie@810c000000 { + status = "disabled"; + compatible = "nvidia,tegra264-pcie"; + reg = <0x81 0x0c000000 0x0 0x00004000>, + <0x81 0x0c004000 0x0 0x00001000>, + <0x81 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names = "xal, xtl, xtl-pri, ecam"; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + linux,pci-domain = <0x0>; + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH0x0 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0x0 &smmu2_mmu 0x10000 0x10000>; + dma-coherent; + msi-map = <0x0 &its 0x210000 0x10000>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x0 0x080000000xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x7 0xc00000000x81000000 0xd0 0x82000000 0xd0 0x82000000 0x0 0x00200000>; + nvidia,bpmp = <&bpmp 0x0>; + numa-node-id = <0x0>; + ats-supported; + nvidia,host1x = <&host1x>; + }; diff --git a/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml b/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml new file mode 100644 index 00000000..1f1608f6 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml @@ -0,0 +1,117 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmu_tcu_smmu0@810a000000/arm,smmu-v3-pmcg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,smmu-v3-pmcg is mentioned in the following drivers + - /kernel/kernel-oot/drivers/perf/arm_smmuv3_pmu.c + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,smmu-v3-pmcg + + required: + - compatible + +properties: + + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,smmu-v3-pmcg + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5002000 + maximum: 0xb1b3000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x6 + maximum: 0x341 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + ceid0-override: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x7 + maximum: 0x7 + +required: + - compatible + - reg + - interrupts + +examples: + - | + pmu_tcu_smmu0@810a000000 { + compatible = "arm,smmu-v3-pmcg"; + status = "disabled"; + reg = <0x81 0x0a002000 0x0 0x1000>, + <0x81 0x0a022000 0x0 0x1000>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/perf/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/perf/arm,smmu-v3.yaml new file mode 100644 index 00000000..01e6f25e --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,smmu-v3.yaml @@ -0,0 +1,132 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu@8105000000/arm,smmu-v3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,smmu-v3 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/perf/arm_smmuv3_pmu.c + - /kernel/kernel-oot/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c + + The following nodes use this compatibility + - /bus@0/iommu@8105000000 + - /bus@0/iommu@8106000000 + - /bus@0/iommu@810a000000 + - /bus@0/iommu@810b000000 + - /bus@0/iommu@8806000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,smmu-v3 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5000000 + maximum: 0xb000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x200000 + maximum: 0x200000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0xe2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - eventq + - gerror + + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#iommu-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + iommu@8105000000 { + compatible = "arm,smmu-v3"; + status = "disabled"; + reg = <0x81 0x5000000 0x00 0x200000>; + interrupts = , + ; + interrupt-names = "eventq", + "gerror"; + dma-coherent; + #iommu-cells = <1>; + numa-node-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/perf/arm,statistical-profiling-extension-v1.yaml b/Documentation/devicetree/bindings/perf/arm,statistical-profiling-extension-v1.yaml new file mode 100644 index 00000000..6f48cd37 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,statistical-profiling-extension-v1.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spe-pmu/arm,statistical-profiling-extension-v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,statistical-profiling-extension-v1 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/perf/arm_spe_pmu.c + + The following nodes use this compatibility + - /spe-pmu + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,statistical-profiling-extension-v1 + + required: + - compatible + +properties: + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + +required: + - compatible + - interrupts + +examples: + - | + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/perf/arm_cspmu/arm,coresight-pmu.yaml b/Documentation/devicetree/bindings/perf/arm_cspmu/arm,coresight-pmu.yaml new file mode 100644 index 00000000..62e78e81 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm_cspmu/arm,coresight-pmu.yaml @@ -0,0 +1,120 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ucf_uapmu@140c0000/arm,coresight-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,coresight-pmu is mentioned in the following drivers + - /kernel/kernel-oot/drivers/perf/arm_cspmu/arm_cspmu.c + + The following nodes use this compatibility + - /ucf_uapmu@140c0000 + - /disp_usb_apmu@8808900000 + - /ucf_gpu_apmu@810c248000 + - /uphy_apmu@a808880000 + - /vision_apmu@818a000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,coresight-pmu + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8880000 + maximum: 0x8a000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x1000 + + cpus: + $ref: "/schemas/types.yaml#/definitions/uint32" + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x33 + maximum: 0x342 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + +required: + - compatible + - reg + - interrupts + +examples: + - | + ucf_uapmu@140c0000 { + compatible = "arm,coresight-pmu"; + status = "disabled"; + reg = <0x0 0x140c0000 0x0 0x1000>; + cpus = <&cpu_0>, + < &cpu_1>, + < &cpu_2>, + < &cpu_3>, + <&cpu_4>, + < &cpu_5>, + < &cpu_6>, + < &cpu_7>, + <&cpu_8>, + < &cpu_9>, + < &cpu_10>, + < &cpu_11>, + <&cpu_12>, + < &cpu_13>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb-padctl.yaml new file mode 100644 index 00000000..7923c28f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb-padctl.yaml @@ -0,0 +1,135 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/padctl@a808680000/nvidia,tegra264-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-padctl is mentioned in the following drivers + - /kernel/kernel-oot/drivers/phy/tegra/xusb.c + + The following nodes use this compatibility + - /bus@0/padctl@a808680000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-padctl + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8680000 + maximum: 0x86a0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x20000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - padctl + - ao + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4d + maximum: 0x4d + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - padctl + + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + +examples: + - | + padctl@a808680000 { + compatible = "nvidia,tegra264-xusb-padctl"; + reg = <0xa8 0x8680000 0x00 0x20000>, + <0xa8 0x86a0000 0x00 0x10000>; + reg-names = "padctl, ao"; + interrupts = <2 5 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bpmp TEGRA264_RESET_XUSB1_PADCTL>; + reset-names = "padctl"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb.yaml b/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb.yaml new file mode 100644 index 00000000..285c26b1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/tegra/nvidia,tegra264-xusb.yaml @@ -0,0 +1,240 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80aa10000/nvidia,tegra264-xusb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb is mentioned in the following drivers + - /kernel/kernel-oot/drivers/phy/tegra/xusb.c + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80aa10000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000000 + maximum: 0xaa50000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x40000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - base + - fpci + - bar2 + - rst + - pinmux + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x3b8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - xhci + - mbox + - padctl + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x12d + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - xusb_host + - xusb_falcon_src + - xusb_ss + - xusb_ss_src + - xusb_hs_src + - xusb_fs_src + - pll_u_480m + - clk_m + - pll_e + + + power-domains: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0xc + + power-domain-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - xusb_host + - xusb_ss + + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3200 + maximum: 0x3600 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + phys: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x29 + maximum: 0x2c + + phy-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - usb2-1 + - usb2-2 + - usb2-3 + - usb3-2 + + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - iommus + +examples: + - | + usb@a80aa10000 { + compatible = "nvidia,tegra264-xusb"; + reg = <0xa8 0xaa10000 0x00 0x40000>, + <0xa8 0xaa00000 0x00 0x10000>, + <0xa8 0xaa50000 0x00 0x10000>, + <0xa8 0x2000000 0x00 0x40000>, + <0xa8 0x82e0000 0x00 0x40000>; + reg-names = "base, fpci, bar2, rst, pinmux"; + interrupts = <0 952 IRQ_TYPE_LEVEL_HIGH>, + <2 0 IRQ_TYPE_LEVEL_HIGH>, + <2 5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "xhci, mbox, padctl"; + clocks = <&bpmp TEGRA264_CLK_XUSB1_CORE_HOST>, + <&bpmp TEGRA264_CLK_XUSB1_FALCON>, + <&bpmp TEGRA264_CLK_XUSB1_CORE_SUPERSPEED>, + <&bpmp TEGRA264_CLK_XUSB1_SS>, + <&bpmp TEGRA264_CLK_OSC>, + <&bpmp TEGRA264_CLK_XUSB1_FS>, + <&bpmp TEGRA264_CLK_UTMI_PLL1>, + <&bpmp TEGRA264_CLK_OSC>, + <&bpmp TEGRA264_CLK_PLLE0>; + clock-names = "xusb_host, xusb_falcon_src", + "xusb_ss, xusb_ss_src, xusb_hs_src", + "xusb_fs_src, pll_u_480m, clk_m", + "pll_e"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_XUSB_HOST>, + <&bpmp TEGRA264_POWER_DOMAIN_XUSB_SS>; + power-domain-names = "xusb_host, xusb_ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_PF_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_PF_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_PF_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_PF_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_PF_SS_PORT4>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-misc.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-misc.yaml new file mode 100644 index 00000000..a1c50f17 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-misc.yaml @@ -0,0 +1,77 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc@100000/nvidia,tegra234-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-misc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/pinctrl/pinctrl-tegra234-dpaux.c + + The following nodes use this compatibility + - /bus@0/misc@100000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-misc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100000 + maximum: 0xc140000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf000 + maximum: 0x10000 + +required: + - compatible + - reg + +examples: + - | + misc@100000 { + compatible = "nvidia,tegra234-misc"; + status = "disabled"; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0c140000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-misc-dpaux-padctl.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-misc-dpaux-padctl.yaml new file mode 100644 index 00000000..32cab77e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-misc-dpaux-padctl.yaml @@ -0,0 +1,76 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/miscreg-dpaux@00100000/nvidia,tegra264-misc-dpaux-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-misc-dpaux-padctl is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/pinctrl/pinctrl-tegra234-dpaux.c + + The following nodes use this compatibility + - /bus@0/miscreg-dpaux@00100000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-misc-dpaux-padctl + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100000 + maximum: 0x100000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4010 + maximum: 0x4010 + +required: + - compatible + - reg + +examples: + - | + miscreg-dpaux@00100000 { + compatible = "nvidia,tegra264-misc-dpaux-padctl"; + reg = <0x0 0x00100000 0x0 0x4010>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/tegra/nvidia,tegra264-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/tegra/nvidia,tegra264-pinmux-aon.yaml new file mode 100644 index 00000000..9fd122f9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/tegra/nvidia,tegra264-pinmux-aon.yaml @@ -0,0 +1,77 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinmux@c7a2000/nvidia,tegra264-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pinmux-aon is mentioned in the following drivers + - /kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264-generic.c + - /kernel/kernel-oot/drivers/pinctrl/tegra/pinctrl-tegra264.c + + The following nodes use this compatibility + - /bus@0/pinmux@c7a2000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pinmux-aon + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc7a2000 + maximum: 0xc7a2000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000 + maximum: 0x2000 + +required: + - compatible + - reg + +examples: + - | + pinmux@c7a2000 { + compatible = "nvidia,tegra264-pinmux-aon"; + status = "disabled"; + reg = <0x0 0x0c7a2000 0x0 0x2000>; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/dce/nvidia,tegra264-dce.yaml b/Documentation/devicetree/bindings/platform/tegra/dce/nvidia,tegra264-dce.yaml new file mode 100644 index 00000000..6e3e46be --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/dce/nvidia,tegra264-dce.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dce@8808000000/nvidia,tegra264-dce.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-dce is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/dce/dce-module.c + + The following nodes use this compatibility + - /dce@8808000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-dce + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88 + maximum: 0x88 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000000 + maximum: 0x8000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xee + maximum: 0xee + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupt-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dce-smb-0 + - dce-smb-1 + - dce-smb-2 + - dce-smb-3 + + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x500 + maximum: 0x500 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - iommus + +examples: + - | + dce@8808000000 { + compatible = "nvidia,tegra264-dce"; + reg = <0x00000088 0x08000000 0x00000000 0x00800000>; + interrupts = ; + interrupt-names = "dce-smb-0, dce-smb-1, dce-smb-2, dce-smb-3"; + iommus = <&smmu3_mmu TEGRA_SID_DCE>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc-utils.yaml b/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc-utils.yaml new file mode 100644 index 00000000..12613d84 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc-utils.yaml @@ -0,0 +1,57 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mc-utils/nvidia,tegra264-mc-utils.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-mc-utils is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/mc-utils/mc-utils.c + + The following nodes use this compatibility + - /bus@0/mc-utils + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-mc-utils + + required: + - compatible + +properties: + + dram_channels: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + +required: + - compatible + +examples: + - | + mc-utils { + compatible = "nvidia,tegra264-mc-utils"; + dram_channels = <16>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc.yaml b/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc.yaml new file mode 100644 index 00000000..4f9cb70a --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc.yaml @@ -0,0 +1,203 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controller@8108020000/nvidia,tegra264-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-mc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/mc-utils/mc-utils.c + + The following nodes use this compatibility + - /bus@0/memory-controller@8108020000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-mc + - nvidia,tegra234-mc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8020000 + maximum: 0x8220000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0x20000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8b + maximum: 0x387 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + '#interconnect-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + '#address-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + '#size-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + dma-ranges: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 6 + maxItems: 6 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100 + maximum: 0x100 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + memory-controller@8108020000 { + compatible = "nvidia,tegra264-mc", + "nvidia,tegra234-mc"; + status = "disabled"; + reg = <0x81 0x08020000 0x0 0x20000>, + <0x81 0x08040000 0x0 0x20000>, + <0x81 0x08060000 0x0 0x20000>, + <0x81 0x08080000 0x0 0x20000>, + <0x81 0x080a0000 0x0 0x20000>, + <0x81 0x080c0000 0x0 0x20000>, + <0x81 0x080e0000 0x0 0x20000>, + <0x81 0x08100000 0x0 0x20000>, + <0x81 0x08120000 0x0 0x20000>, + <0x81 0x08140000 0x0 0x20000>, + <0x81 0x08160000 0x0 0x20000>, + <0x81 0x08180000 0x0 0x20000>, + <0x81 0x081a0000 0x0 0x20000>, + <0x81 0x081c0000 0x0 0x20000>, + <0x81 0x081e0000 0x0 0x20000>, + <0x81 0x08200000 0x0 0x20000>, + <0x81 0x08220000 0x0 0x20000>; + reg-names = "broadcast, ch0, ch1, ch2, ch3", + "ch4, ch5, ch6, ch7, ch8, ch9, ch10", + "ch11, ch12, ch13, ch14, ch15"; + interrupts = , + , + , + , + , + , + , + ; + #interconnect-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x81 0x08020000 0x81 0x08020000 0x0 0x20000>, + <0x81 0x08040000 0x81 0x08040000 0x0 0x20000>, + <0x81 0x080c0000 0x81 0x080c0000 0x0 0x20000>; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + numa-node-id = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp.yaml b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp.yaml new file mode 100644 index 00000000..c931d661 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp.yaml @@ -0,0 +1,249 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/adsp@9080000/nvidia,tegra264-adsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-adsp is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/nvadsp/dev.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000/adsp@9080000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-adsp + + required: + - compatible + +properties: + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4a + maximum: 0x4a + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - adsp + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9c + maximum: 0x9c + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - cpu_clock + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9a00000 + maximum: 0x9d60000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x40000 + + nvidia,dram_map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + + nvidia,adsp_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x200000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20 + maximum: 0x52 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x206 + maximum: 0x206 + + nvidia,cluster_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 6 + maxItems: 6 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9080000 + maximum: 0xa080000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000 + maximum: 0x200000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x18000 + maximum: 0x80000 + + nvidia,adsp_os_secload: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - resets + - reset-names + - clocks + - clock-names + - reg + - interrupts + - iommus + +examples: + - | + adsp@9080000 { + compatible = "nvidia,tegra264-adsp"; + interrupt-parent = <&agic_page0>; + resets = <&bpmp TEGRA264_RESET_ADSP_CORE0>; + reset-names = "adsp"; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "cpu_clock"; + reg = <0x0 0x9d60000 0x0 0x10000>, + <0x0 0x9a00000 0x0 0x1000>, + <0x0 0x9a20000 0x0 0x40000>; + nvidia,dram_map = <0x0 0x20000000 0x0 0x20000000>; + nvidia,adsp_mem = <0x0 0x0>, + <0x0 0x0>, + <0x0 0x0>, + <0x0 0x200000>; + interrupts = , + , + , + , + , + ; + iommus = <&smmu1_mmu (TEGRA_SID_APE+0x6)>; + memory-region = <&adsp0_resv>; + nvidia,cluster_mem = <0x0 0x9080000 0x0 0x80000 0x0 0x80000>, + <0x0 0x9e80000 0x0 0x200000 0x0 0x80000>, + <0x0 0xa080000 0x0 0x100000 0x0 0x18000>; + nvidia,adsp_os_secload; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp1.yaml b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp1.yaml new file mode 100644 index 00000000..27f08daf --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-adsp1.yaml @@ -0,0 +1,249 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/adsp1@9180000/nvidia,tegra264-adsp1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-adsp1 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/nvadsp/dev.c + + The following nodes use this compatibility + - /bus@0/aconnect@9000000/adsp1@9180000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-adsp1 + + required: + - compatible + +properties: + + interrupt-parent: + $ref: "/schemas/types.yaml#/definitions/uint32" + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4b + maximum: 0x4b + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - adsp + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9c + maximum: 0x9c + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - cpu_clock + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9a01000 + maximum: 0x9d60000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1000 + maximum: 0x40000 + + nvidia,dram_map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + + nvidia,adsp_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x200000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3a + maximum: 0x8a + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x207 + maximum: 0x207 + + nvidia,cluster_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 6 + maxItems: 6 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x9180000 + maximum: 0xa080000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000 + maximum: 0x200000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x18000 + maximum: 0x80000 + + nvidia,adsp_os_secload: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - resets + - reset-names + - clocks + - clock-names + - reg + - interrupts + - iommus + +examples: + - | + adsp1@9180000 { + compatible = "nvidia,tegra264-adsp1"; + interrupt-parent = <&agic_page0>; + resets = <&bpmp TEGRA264_RESET_ADSP_CORE1>; + reset-names = "adsp"; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "cpu_clock"; + reg = <0x0 0x9d60000 0x0 0x10000>, + <0x0 0x9a01000 0x0 0x1000>, + <0x0 0x9b20000 0x0 0x40000>; + nvidia,dram_map = <0x0 0x20000000 0x0 0x20000000>; + nvidia,adsp_mem = <0x0 0x0>, + <0x0 0x0>, + <0x0 0x0>, + <0x0 0x200000>; + interrupts = , + , + , + , + , + ; + iommus = <&smmu1_mmu (TEGRA_SID_APE+0x7)>; + memory-region = <&adsp1_resv>; + nvidia,cluster_mem = <0x0 0x9180000 0x0 0x80000 0x0 0x80000>, + <0x0 0x9e80000 0x0 0x200000 0x0 0x80000>, + <0x0 0xa080000 0x0 0x100000 0x0 0x18000>; + nvidia,adsp_os_secload; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-aon.yaml b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-aon.yaml new file mode 100644 index 00000000..4693015d --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvadsp/nvidia,tegra264-aon.yaml @@ -0,0 +1,242 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/aon@c040000/nvidia,tegra264-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-aon is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/nvadsp/dev.c + + The following nodes use this compatibility + - /bus@0/aocluster@c000000/aon@c040000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-aon + + required: + - compatible + +properties: + + nvidia,adsp_os_secload: + $ref: "/schemas/types.yaml#/definitions/flag" + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4e + maximum: 0x4e + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - aon_cpu + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc4 + maximum: 0xc4 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - cpu_clock + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc040000 + maximum: 0xc410000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000 + maximum: 0xa0000 + + nvidia,dram_map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20000000 + maximum: 0x20000000 + + nvidia,adsp_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x200000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x229 + maximum: 0x2d8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100 + maximum: 0x100 + + nvidia,cluster_mem: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 6 + maxItems: 6 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc040000 + maximum: 0xce00000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x200000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000 + maximum: 0xa0000 + +required: + - compatible + - resets + - reset-names + - clocks + - clock-names + - reg + - interrupts + - iommus + +examples: + - | + aon@c040000 { + compatible = "nvidia,tegra264-aon"; + nvidia,adsp_os_secload; + resets = <&bpmp TEGRA264_RESET_AON_CPU_ALL>; + reset-names = "aon_cpu"; + clocks = <&bpmp TEGRA264_CLK_AON_CPU>; + clock-names = "cpu_clock"; + reg = <0x0 0xc040000 0x0 0xa0000>, + <0x0 0xc100000 0x0 0x20000>, + <0x0 0xc410000 0x0 0x40000>; + nvidia,dram_map = <0x0 0x20000000 0x0 0x20000000>; + nvidia,adsp_mem = <0x0 0x0>, + <0x0 0x0>, + <0x0 0x0>, + <0x0 0x200000>; + interrupts = , + , + , + ; + iommus = <&smmu1_mmu TEGRA_SID_AON>; + memory-region = <&aon_resv>; + nvidia,cluster_mem = <0x0 0xc040000 0x0 0x40000 0x0 0xa0000>, + <0x0 0xce00000 0x0 0x200000 0x0 0x80000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-epl-client.yaml b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-epl-client.yaml new file mode 100644 index 00000000..a1b3d7ab --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-epl-client.yaml @@ -0,0 +1,148 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/safetyservices_epl_client@110000/nvidia,tegra234-epl-client.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-epl-client is mentioned in the following drivers + - /kernel/kernel-oot/drivers/platform/tegra/tegra-epl.c + + The following nodes use this compatibility + - /safetyservices_epl_client@110000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-epl-client + + required: + - compatible + +properties: + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x101 + maximum: 0x101 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000000 + maximum: 0x80000000 + + mbox-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - epl-tx + + + handshake-retry-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc8 + maximum: 0xc8 + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x110000 + maximum: 0x170038 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + client-misc-sw-generic-err0: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvgpu + + + client-misc-sw-generic-err1: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - gk20b + + + client-misc-sw-generic-err3: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - gk20d + + + client-misc-sw-generic-err4: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - gk20e + + +required: + - compatible + - reg + +examples: + - | + safetyservices_epl_client@110000 { + compatible = "nvidia,tegra234-epl-client"; + mboxes = <&top_hsp3 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(0)>; + mbox-names = "epl-tx"; + handshake-retry-count = < 200 >; + reg = <0x0 0x00110000 0x0 0x4>, + <0x0 0x00110004 0x0 0x4>, + <0x0 0x00120000 0x0 0x4>, + <0x0 0x00120004 0x0 0x4>, + <0x0 0x00130000 0x0 0x4>, + <0x0 0x00130004 0x0 0x4>, + <0x0 0x00140000 0x0 0x4>, + <0x0 0x00140004 0x0 0x4>, + <0x0 0x00150000 0x0 0x4>, + <0x0 0x00150004 0x0 0x4>, + <0x0 0x00170038 0x0 0x4>; + client-misc-sw-generic-err0 = "fsicom_client"; + client-misc-sw-generic-err1 = "gk20b"; + client-misc-sw-generic-err3 = "gk20d"; + client-misc-sw-generic-err4 = "gk20e"; + enable-deinit-notify; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-fsicom-client.yaml b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-fsicom-client.yaml new file mode 100644 index 00000000..a19165b7 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra234-fsicom-client.yaml @@ -0,0 +1,125 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsicom_client/nvidia,tegra234-fsicom-client.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-fsicom-client is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/tegra-fsicom.c + + The following nodes use this compatibility + - /fsicom_client + - /fsicom_client_inst1 + - /fsicom_client_inst2 + - /fsicom_client_inst3 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-fsicom-client + + required: + - compatible + +properties: + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x101 + maximum: 0x101 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x80000005 + + mbox-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - fsi-tx-cpu0 + - fsi-rx-cpu0 + - fsi-tx-cpu1 + - fsi-rx-cpu1 + + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + smmu_inst: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x3 + + max_fsi_core: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + fsi_core_notify: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + fsi_core_polling: + $ref: "/schemas/types.yaml#/definitions/flag" + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - iommus + +examples: + - | + fsicom_client { + compatible = "nvidia,tegra234-fsicom-client"; + mboxes = <&top_hsp2 (TEGRA_HSP_MBOX_TYPE_SM|TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>, + <&top_hsp2 (TEGRA_HSP_MBOX_TYPE_SM|TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>, + <&top_hsp2 (TEGRA_HSP_MBOX_TYPE_SM|TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(5)>, + <&top_hsp2 (TEGRA_HSP_MBOX_TYPE_SM|TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(4)>; + mbox-names = "fsi-tx-cpu0, fsi-rx-cpu0, fsi-tx-cpu1, fsi-rx-cpu1"; + memory-region = <&fsicom_resv>; + dma-coherent; + enable-deinit-notify; + smmu_inst = <0>; + max_fsi_core = <1>; + fsi_core_notify = <0>; + fsi_core_polling = <>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra23x-hsierrrptinj.yaml b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra23x-hsierrrptinj.yaml new file mode 100644 index 00000000..0d0a376b --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra23x-hsierrrptinj.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hsierrrptinj/nvidia,tegra23x-hsierrrptinj.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra23x-hsierrrptinj is mentioned in the following drivers + - /kernel/kernel-oot/drivers/platform/tegra/tegra-hsierrrptinj.c + + The following nodes use this compatibility + - /hsierrrptinj + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra23x-hsierrrptinj + + required: + - compatible + +properties: + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x101 + maximum: 0x101 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000001 + maximum: 0x80000001 + + mbox-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - hsierrrptinj-tx + + +required: + - compatible + +examples: + - | + hsierrrptinj { + compatible = "nvidia,tegra23x-hsierrrptinj"; + mboxes = <&top_hsp0 (TEGRA_HSP_MBOX_TYPE_SM|TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(1)>; + mbox-names = "hsierrrptinj-tx"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra264-cactmon-mc-all.yaml b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra264-cactmon-mc-all.yaml new file mode 100644 index 00000000..c1745a65 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra264-cactmon-mc-all.yaml @@ -0,0 +1,102 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/actmon@d3f0000/nvidia,tegra264-cactmon-mc-all.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-cactmon-mc-all is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/tegra-cactmon-mc-all.c + + The following nodes use this compatibility + - /bus@0/actmon@d3f0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-cactmon-mc-all + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xd3f0000 + maximum: 0xd3f0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - actmon + + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + actmon@d3f0000 { + compatible = "nvidia,tegra264-cactmon-mc-all"; + reg = <0x0 0xd3f0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_OSC>; + clock-names = "actmon"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra_bl_debug.yaml b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra_bl_debug.yaml new file mode 100644 index 00000000..7536c446 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/nvidia,tegra_bl_debug.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_bl_debug/nvidia,tegra_bl_debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra_bl_debug is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/tegra_bootloader_debug.c + + The following nodes use this compatibility + - /tegra_bl_debug + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra_bl_debug + + required: + - compatible + +properties: + + usec_timer_reg_base: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc240000 + maximum: 0xc240000 + +required: + - compatible + +examples: + - | + tegra_bl_debug { + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/psc/nvidia,tegra234-psc.yaml b/Documentation/devicetree/bindings/platform/tegra/psc/nvidia,tegra234-psc.yaml new file mode 100644 index 00000000..4dd00d38 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/psc/nvidia,tegra234-psc.yaml @@ -0,0 +1,201 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/psc@d8e0000/nvidia,tegra234-psc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-psc is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/psc/tegra23x_psc_mailbox.c + + The following nodes use this compatibility + - /bus@0/psc@d8e0000 + - /bus@0/psc@e0e0000 + - /bus@0/psc@e860000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-psc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xd8e0000 + maximum: 0xe860000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80000 + maximum: 0x80000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xd80205c + maximum: 0xe80201c + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x8 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - mbox-regs + - extcfg + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2c3 + maximum: 0x302 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,cpu-name: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - sb + - oesp + - psc + + + '#mbox-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,mailbox-mutex: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,sidconfig: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1c00 + maximum: 0x2400 + + nvidia,sidtable: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + psc@d8e0000 { + compatible = "nvidia,tegra234-psc"; + reg = <0x0 0xd8e0000 0x0 0x80000 0x0 0xd80205c 0x0 0x8>; + reg-names = "mbox-regs, extcfg"; + interrupts = , + , + , + , + , + , + , + ; + nvidia,cpu-name = "sb"; + #mbox-cells = <1>; + mboxes = <&soc_sb_cluster 0>; + nvidia,mailbox-mutex = <1>; + nvidia,sidconfig = <0x0>; + iommus = <&smmu1_mmu 0x2400>; + dma-coherent; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra-camrtc-hsp-vm.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra-camrtc-hsp-vm.yaml new file mode 100644 index 00000000..7d47cf36 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra-camrtc-hsp-vm.yaml @@ -0,0 +1,81 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hsp-vm1/nvidia,tegra-camrtc-hsp-vm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-camrtc-hsp-vm is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/hsp-mailbox-client.c + + The following nodes use this compatibility + - /rtcpu@81893d0000/hsp-vm1 + - /rtcpu@81893d0000/hsp-vm2 + - /rtcpu@81893d0000/hsp-vm3 + - /rtcpu@81893d0000/hsp-vm4 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-camrtc-hsp-vm + + required: + - compatible + +properties: + + mboxes: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 3 + maxItems: 3 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x80000007 + + mbox-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vm-tx + - vm-rx + - vm-ss + + +required: + - compatible + +examples: + - | + hsp-vm1 { + compatible = "nvidia,tegra-camrtc-hsp-vm"; + mboxes = <&rce_hsp0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>, + <&rce_hsp0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>, + <&rce_hsp0 TEGRA_HSP_MBOX_TYPE_SS 0>; + mbox-names = "vm-tx, vm-rx, vm-ss"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-diagnostics.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-diagnostics.yaml new file mode 100644 index 00000000..d7839ad9 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-diagnostics.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/diag@5/nvidia,tegra186-camera-diagnostics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-diagnostics is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/camera-diagnostics.c + + The following nodes use this compatibility + - /camera-ivc-channels/diag@5 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-diagnostics + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - diag + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + +required: + - compatible + +examples: + - | + diag@5 { + compatible = "nvidia,tegra186-camera-diagnostics"; + nvidia,service = "diag"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <1>; + nvidia,frame-size = <64>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture-control.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture-control.yaml new file mode 100644 index 00000000..9dc75cb2 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture-control.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ivccontrol@3/nvidia,tegra186-camera-ivc-protocol-capture-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-ivc-protocol-capture-control is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/capture-ivc.c + + The following nodes use this compatibility + - /camera-ivc-channels/ivccontrol@3 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-ivc-protocol-capture-control + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - capture-control + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x140 + maximum: 0x140 + +required: + - compatible + +examples: + - | + ivccontrol@3 { + compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control"; + nvidia,service = "capture-control"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <64>; + nvidia,frame-size = <320>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture.yaml new file mode 100644 index 00000000..46ec6eb7 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-capture.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ivccapture@4/nvidia,tegra186-camera-ivc-protocol-capture.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-ivc-protocol-capture is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/capture-ivc.c + + The following nodes use this compatibility + - /camera-ivc-channels/ivccapture@4 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-ivc-protocol-capture + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - capture + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x200 + maximum: 0x200 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + +required: + - compatible + +examples: + - | + ivccapture@4 { + compatible = "nvidia,tegra186-camera-ivc-protocol-capture"; + nvidia,service = "capture"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <512>; + nvidia,frame-size = <64>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-dbg.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-dbg.yaml new file mode 100644 index 00000000..95e9cb3e --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-dbg.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dbg@1/nvidia,tegra186-camera-ivc-protocol-dbg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-ivc-protocol-dbg is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/camchar.c + + The following nodes use this compatibility + - /camera-ivc-channels/dbg@1 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-ivc-protocol-dbg + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - debug + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x200 + maximum: 0x200 + +required: + - compatible + +examples: + - | + dbg@1 { + compatible = "nvidia,tegra186-camera-ivc-protocol-dbg"; + nvidia,service = "debug"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <1>; + nvidia,frame-size = <512>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-debug.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-debug.yaml new file mode 100644 index 00000000..5d7fc29b --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-debug.yaml @@ -0,0 +1,114 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dbg@2/nvidia,tegra186-camera-ivc-protocol-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-ivc-protocol-debug is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/rtcpu-debug.c + + The following nodes use this compatibility + - /camera-ivc-channels/dbg@2 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-ivc-protocol-debug + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - debug + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2000 + maximum: 0x2000 + + nvidia,ivc-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x32 + maximum: 0x32 + + nvidia,test-timeout: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1388 + maximum: 0x1388 + + nvidia,mem-map: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 5 + maxItems: 5 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,test-bw: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x249f00 + maximum: 0x249f00 + +required: + - compatible + +examples: + - | + dbg@2 { + compatible = "nvidia,tegra186-camera-ivc-protocol-debug"; + nvidia,service = "debug"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <1>; + nvidia,frame-size = <8192>; + nvidia,ivc-timeout = <50>; + nvidia,test-timeout = <5000>; + nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1 &isp1>; + nvidia,test-bw = <2400000>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-echo.yaml b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-echo.yaml new file mode 100644 index 00000000..17f3c2f0 --- /dev/null +++ b/Documentation/devicetree/bindings/platform/tegra/rtcpu/nvidia,tegra186-camera-ivc-protocol-echo.yaml @@ -0,0 +1,83 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/echo@0/nvidia,tegra186-camera-ivc-protocol-echo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-camera-ivc-protocol-echo is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/platform/tegra/rtcpu/camchar.c + + The following nodes use this compatibility + - /camera-ivc-channels/echo@0 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-camera-ivc-protocol-echo + + required: + - compatible + +properties: + + nvidia,service: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - echo + + + nvidia,version: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,group: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,frame-count: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + + nvidia,frame-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + +required: + - compatible + +examples: + - | + echo@0 { + compatible = "nvidia,tegra186-camera-ivc-protocol-echo"; + nvidia,service = "echo"; + nvidia,version = <0>; + nvidia,group = <1>; + nvidia,frame-count = <16>; + nvidia,frame-size = <64>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/pwm/nvidia,pwm-tegra264-tachometer.yaml b/Documentation/devicetree/bindings/pwm/nvidia,pwm-tegra264-tachometer.yaml new file mode 100644 index 00000000..99e8e5c7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nvidia,pwm-tegra264-tachometer.yaml @@ -0,0 +1,150 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tachometer@810c5c0000/nvidia,pwm-tegra264-tachometer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,pwm-tegra264-tachometer is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/pwm/pwm-tegra-tachometer.c + + The following nodes use this compatibility + - /bus@0/tachometer@810c5c0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,pwm-tegra264-tachometer + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc5c0000 + maximum: 0xc5c0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + + '#pwm-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x158 + maximum: 0x158 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2c + maximum: 0x2c + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tach + + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - tach + + + pulse-per-rev: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + capture-window-length: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + disable-clk-gate: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - clocks + - resets + - clock-names + - reset-names + +examples: + - | + tachometer@810c5c0000 { + compatible = "nvidia,pwm-tegra264-tachometer"; + status = "disabled"; + reg = <0x81 0x0c5c0000 0x0 0x10>; + #pwm-cells = <2>; + clocks = <&bpmp TEGRA264_CLK_CLK1M>; + resets = <&bpmp TEGRA264_RESET_TACH0>; + clock-names = "tach"; + reset-names = "tach"; + pulse-per-rev = <2>; + capture-window-length = <2>; + disable-clk-gate; + }; diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra264-pwm.yaml b/Documentation/devicetree/bindings/pwm/nvidia,tegra264-pwm.yaml new file mode 100644 index 00000000..8db4f94a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra264-pwm.yaml @@ -0,0 +1,146 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm@c6a0000/nvidia,tegra264-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pwm is mentioned in the following drivers + - /kernel/kernel-oot/drivers/pwm/pwm-tegra.c + + The following nodes use this compatibility + - /bus@0/pwm@c6a0000 + - /bus@0/pwm@810c5e0000 + - /bus@0/pwm@810c5f0000 + - /bus@0/pwm@810c600000 + - /bus@0/pwm@810c610000 + - /bus@0/pwm@810c620000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pwm + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc5e0000 + maximum: 0xc6a0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + nvidia,hw-instance-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0xa + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0xa0 + + '#pwm-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x17 + maximum: 0x1c + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pwm + + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pwm + - pll_aon + - parent + + +required: + - compatible + - reg + - clocks + - resets + - reset-names + - clock-names + +examples: + - | + pwm@c6a0000 { + compatible = "nvidia,tegra264-pwm"; + status = "disabled"; + reg = <0x0 0xc6a0000 0x0 0x10000>; + nvidia,hw-instance-id = <0x4>; + clocks = <&bpmp TEGRA264_CLK_PWM4>; + #pwm-cells = <2>; + resets = <&bpmp TEGRA264_RESET_PWM4>; + reset-names = "pwm"; + }; diff --git a/Documentation/devicetree/bindings/ras/arm,armv8.yaml b/Documentation/devicetree/bindings/ras/arm,armv8.yaml new file mode 100644 index 00000000..877e5cfa --- /dev/null +++ b/Documentation/devicetree/bindings/ras/arm,armv8.yaml @@ -0,0 +1,149 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpu@0/arm,armv8.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,armv8 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/ras/arm64-ras.c + + The following nodes use this compatibility + - /cpus/cpu@0 + - /cpus/cpu@1 + - /cpus/cpu@2 + - /cpus/cpu@3 + - /cpus/cpu@4 + - /cpus/cpu@5 + - /cpus/cpu@6 + - /cpus/cpu@7 + - /cpus/cpu@8 + - /cpus/cpu@9 + - /cpus/cpu@10 + - /cpus/cpu@11 + - /cpus/cpu@12 + - /cpus/cpu@13 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - arm,armv8 + + required: + - compatible + +properties: + + device_type: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - cpu + + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0xd0000 + + enable-method: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - psci + + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + cpu-idle-states: + $ref: "/schemas/types.yaml#/definitions/uint32" + + i-cache-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + i-cache-line-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + + i-cache-sets: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100 + maximum: 0x100 + + d-cache-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + d-cache-line-size: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40 + maximum: 0x40 + + d-cache-sets: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100 + maximum: 0x100 + + next-level-cache: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + +examples: + - | + cpu@0 { + compatible = "arm,armv8"; + status = "disabled"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + cpu-idle-states = <&cc7>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_0>; + }; diff --git a/Documentation/devicetree/bindings/scsi/ufs/tegra264,ufs_variant.yaml b/Documentation/devicetree/bindings/scsi/ufs/tegra264,ufs_variant.yaml new file mode 100644 index 00000000..e88d0272 --- /dev/null +++ b/Documentation/devicetree/bindings/scsi/ufs/tegra264,ufs_variant.yaml @@ -0,0 +1,314 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufshci@a80b8d0000/tegra264,ufs_variant.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = tegra264,ufs_variant is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/scsi/ufs/ufs-tegra-common.c + + The following nodes use this compatibility + - /ufshci@a80b8d0000 + - /ufshci@a80b8d0000/ufs_variant + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - tegra264,ufs_variant + - tegra234,ufs_variant + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xb8d0000 + maximum: 0xb920000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3b7 + maximum: 0x3b7 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2a00 + maximum: 0x2a00 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1af + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pllrefe_vcoout + - mphy_core_pll_fixed + - mphy_l0_tx_symb + - mphy_tx_1mhz_ref + - mphy_l0_rx_ana + - mphy_l0_rx_symb + - mphy_l0_tx_ls_3xbit + - mphy_l0_rx_ls_bit + - mphy_l1_rx_ana + - ufshc + - ufshc_div + - ufsdev_ref + - pll_p + - mphy_l0_tx_ls_3xbit_div + - mphy_l0_tx_ls_symb_div + - mphy_l0_rx_ls_bit_div + - mphy_l0_rx_ls_symb_div + - mphy_l0_tx_hs_symb_div + - mphy_l0_rx_hs_symb_div + - osc + - mphy_l0_uphy_tx_fifo + - uphy_pll3 + - isc_cpu + - utmi_pll1 + + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x36 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - mphy-l0-rx-rst + - mphy-l0-tx-rst + - mphy-l1-rx-rst + - mphy-l1-tx-rst + - mphy-clk-ctl-rst + - ufs-rst + - ufs-axi-m-rst + - ufshc-lp-rst + + + nvidia,enable-x2-config: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,enable-auto-hibern8: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,configure-uphy-pll3: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,mask-fast-auto-mode: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,enable-hs-mode: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,max-hs-gear: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,max-pwm-gear: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + vcc-max-microamp: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + vccq-max-microamp: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + vccq2-max-microamp: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,enable-ufs-provisioning: + $ref: "/schemas/types.yaml#/definitions/flag" + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + - iommus + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + ufshci@a80b8d0000 { + compatible = "tegra264,ufs_variant", + "tegra234,ufs_variant"; + status = "disabled"; + reg = <0xa8 0x0b8d0000 0x0 0x10000>, + <0xa8 0x0b8e0000 0x0 0x8000>, + <0xa8 0x0b8e8000 0x0 0x8000>, + <0xa8 0x0b8f0000 0x0 0x10000>, + <0xa8 0x0b910000 0x0 0x10000>, + <0xa8 0x0b920000 0x0 0x10000>; + interrupts = ; + iommus = <&smmu1_mmu TEGRA_SID_UFS>; + dma-coherent; + clocks = <&bpmp TEGRA264_CLK_PLLREFUFS_CLKOUT624>, + <&bpmp TEGRA264_CLK_MPHY_CORE_PLL_FIXED>, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_SYMB>, + <&bpmp TEGRA264_CLK_MPHY_TX_1MHZ_REF>, + < &bpmp TEGRA264_CLK_MPHY_L0_RX_ANA>, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_SYMB>, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT>, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_BIT>, + <&bpmp TEGRA264_CLK_MPHY_L1_RX_ANA>, + <&bpmp TEGRA264_CLK_UFSHC_CG_SYS>, + <&bpmp TEGRA264_CLK_UFSHC_CG_SYS_DIV>, + <&bpmp TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT_DIV>, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_LS_SYMB_DIV>, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_BIT_DIV>, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_LS_SYMB_DIV>, + <&bpmp TEGRA264_CLK_MPHY_L0_TX_HS_SYMB_DIV>, + <&bpmp TEGRA264_CLK_MPHY_L0_RX_HS_SYMB_DIV>, + <&bpmp TEGRA264_CLK_OSC>, + <&bpmp TEGRA264_CLK_MPHY_L0_UPHY_TX_FIFO>, + <&bpmp TEGRA264_CLK_UPHY0_PLL4_XDIG>, + <&bpmp TEGRA264_CLK_ISC_CPU_ROOT>, + <&bpmp TEGRA264_CLK_UTMI_PLL1_CLKOUT480>; + clock-names = "pllrefe_vcoout, mphy_core_pll_fixed, mphy_l0_tx_symb", + "mphy_tx_1mhz_ref, mphy_l0_rx_ana", + "mphy_l0_rx_symb, mphy_l0_tx_ls_3xbit", + "mphy_l0_rx_ls_bit, mphy_l1_rx_ana", + "ufshc, ufshc_div, ufsdev_ref, pll_p", + "mphy_l0_tx_ls_3xbit_div, mphy_l0_tx_ls_symb_div", + "mphy_l0_rx_ls_bit_div, mphy_l0_rx_ls_symb_div", + "mphy_l0_tx_hs_symb_div, mphy_l0_rx_hs_symb_div", + "osc", + "mphy_l0_uphy_tx_fifo", + "uphy_pll3", + "isc_cpu", + "utmi_pll1"; + resets = <&bpmp TEGRA264_RESET_MPHY_L0_RX>, + <&bpmp TEGRA264_RESET_MPHY_L0_TX>, + <&bpmp TEGRA264_RESET_MPHY_L1_RX>, + <&bpmp TEGRA264_RESET_MPHY_L1_TX>, + <&bpmp TEGRA264_RESET_MPHY_CLK_CTL>, + <&bpmp TEGRA264_RESET_UFSHC>, + <&bpmp TEGRA264_RESET_UFSHC_AXI_M>, + <&bpmp TEGRA264_RESET_UFSHC_LP_SEQ>; + reset-names = "mphy-l0-rx-rst, mphy-l0-tx-rst, mphy-l1-rx-rst", + "mphy-l1-tx-rst, mphy-clk-ctl-rst, ufs-rst", + "ufs-axi-m-rst, ufshc-lp-rst"; + nvidia,enable-x2-config; + nvidia,enable-auto-hibern8; + nvidia,configure-uphy-pll3; + nvidia,mask-fast-auto-mode; + nvidia,enable-hs-mode; + nvidia,max-hs-gear = <4>; + nvidia,max-pwm-gear = <0>; + vcc-max-microamp = <0>; + vccq-max-microamp = <0>; + vccq2-max-microamp = <0>; + nvidia,enable-ufs-provisioning; + numa-node-id = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-sys-cbb-fabric.yaml b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-sys-cbb-fabric.yaml new file mode 100644 index 00000000..7e7e3f9b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-sys-cbb-fabric.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sys-cbb-fabric@800000/nvidia,tegra264-sys-cbb-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-sys-cbb-fabric is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/cbb/tegra234-cbb.c + + The following nodes use this compatibility + - /bus@0/sys-cbb-fabric@800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-sys-cbb-fabric + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x245 + maximum: 0x245 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + sys-cbb-fabric@800000 { + compatible = "nvidia,tegra264-sys-cbb-fabric"; + reg = <0x0 0x800000 0x0 0x800000>; + interrupts = ; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-top0-cbb-fabric.yaml b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-top0-cbb-fabric.yaml new file mode 100644 index 00000000..787f38a6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-top0-cbb-fabric.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/top0-cbb-fabric@8100800000/nvidia,tegra264-top0-cbb-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-top0-cbb-fabric is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/cbb/tegra234-cbb.c + + The following nodes use this compatibility + - /bus@0/top0-cbb-fabric@8100800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-top0-cbb-fabric + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x43 + maximum: 0x43 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + top0-cbb-fabric@8100800000 { + compatible = "nvidia,tegra264-top0-cbb-fabric"; + reg = <0x81 0x800000 0x0 0x800000>; + interrupts = ; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-uphy0-cbb-fabric.yaml b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-uphy0-cbb-fabric.yaml new file mode 100644 index 00000000..b7a68d5b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-uphy0-cbb-fabric.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/uphy0-cbb-fabric@a800800000/nvidia,tegra264-uphy0-cbb-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-uphy0-cbb-fabric is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/cbb/tegra234-cbb.c + + The following nodes use this compatibility + - /bus@0/uphy0-cbb-fabric@a800800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-uphy0-cbb-fabric + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x343 + maximum: 0x343 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + uphy0-cbb-fabric@a800800000 { + compatible = "nvidia,tegra264-uphy0-cbb-fabric"; + reg = <0xa8 0x800000 0x0 0x800000>; + interrupts = ; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-vision-cbb-fabric.yaml b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-vision-cbb-fabric.yaml new file mode 100644 index 00000000..f3c15df1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/cbb/nvidia,tegra264-vision-cbb-fabric.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vision-cbb-fabric@8180800000/nvidia,tegra264-vision-cbb-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-vision-cbb-fabric is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/cbb/tegra234-cbb.c + + The following nodes use this compatibility + - /bus@0/vision-cbb-fabric@8180800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-vision-cbb-fabric + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x80800000 + maximum: 0x80800000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800000 + maximum: 0x800000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x144 + maximum: 0x144 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + vision-cbb-fabric@8180800000 { + compatible = "nvidia,tegra264-vision-cbb-fabric"; + reg = <0x81 0x80800000 0x0 0x800000>; + interrupts = ; + numa-node-id = <0x0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/fuse/nvidia,efuse-nvmem-helper.yaml b/Documentation/devicetree/bindings/soc/tegra/fuse/nvidia,efuse-nvmem-helper.yaml new file mode 100644 index 00000000..98d6181e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/fuse/nvidia,efuse-nvmem-helper.yaml @@ -0,0 +1,63 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/efuse-helper/nvidia,efuse-nvmem-helper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,efuse-nvmem-helper is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/fuse/tegra-efuse-nvmem-helper.c + + The following nodes use this compatibility + - /bus@0/efuse-helper + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,efuse-nvmem-helper + + required: + - compatible + +properties: + + nvmem: + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvmem-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - efuse + + +required: + - compatible + +examples: + - | + efuse-helper { + compatible = "nvidia,efuse-nvmem-helper"; + nvmem = <&tegra_efuse0>; + nvmem-names = "efuse"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra264-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra264-pmc.yaml new file mode 100644 index 00000000..a21ca286 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra264-pmc.yaml @@ -0,0 +1,123 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pmc@c800000/nvidia,tegra264-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pmc is mentioned in the following drivers + - /kernel/kernel-oot/drivers/soc/tegra/tegra264-pmc.c + - /kernel/kernel-oot/drivers/gpio/gpio-tegra186.c + + The following nodes use this compatibility + - /bus@0/pmc@c800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-pmc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc800000 + maximum: 0xc9c0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x100000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pmc + - wake + - scratch + - misc + + + '#interrupt-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + + interrupt-controller: + $ref: "/schemas/types.yaml#/definitions/flag" + + '#padcontroller-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + + nvidia,restrict-voltage-switch: + $ref: "/schemas/types.yaml#/definitions/flag" + + pinctrl-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - default + + + pinctrl-0: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + +examples: + - | + pmc@c800000 { + compatible = "nvidia,tegra264-pmc"; + status = "disabled"; + reg = <0x0 0x0c800000 0x0 0x100000>, + <0x0 0x0c990000 0x0 0x10000>, + <0x0 0x0c980000 0x0 0x10000>, + <0x0 0x0c9c0000 0x0 0x40000>; + reg-names = "pmc, wake, scratch, misc"; + #interrupt-cells = <2>; + interrupt-controller; + #padcontroller-cells = <1>; + nvidia,restrict-voltage-switch; + pinctrl-names = "default"; + pinctrl-0 = <&iopad_defaults>; + }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra186-spi-slave.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra186-spi-slave.yaml new file mode 100644 index 00000000..99a5a26b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra186-spi-slave.yaml @@ -0,0 +1,225 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi@810c460000/nvidia,tegra186-spi-slave.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-spi-slave is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/spi/spi-tegra124-slave.c + + The following nodes use this compatibility + - /bus@0/spi@810c460000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-spi-slave + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc460000 + maximum: 0xc460000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa7 + maximum: 0xa7 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx + - tx + + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x10 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10 + maximum: 0x1a + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x810 + maximum: 0x810 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x810 + maximum: 0x810 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x2e + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - spi + + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2e + maximum: 0x2e + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x16 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x28 + maximum: 0x28 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - spi + + +required: + - compatible + - reg + - interrupts + - iommus + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + spi@810c460000 { + compatible = "nvidia,tegra234-spi, nvidia,tegra210-spi"; + status = "disabled"; + reg = <0x81 0x0c460000 0x0 0x10000>; + interrupts = ; + dma-coherent; + dma-names = "rx, tx"; + dmas = <&gpcdma 16 16 TEGRA264_GPCDMA_SID_SPI5>, + <&gpcdma 16 26 TEGRA264_GPCDMA_SID_SPI5>; + iommus = <&smmu1_mmu TEGRA264_GPCDMA_SID_SPI5>; + clocks = <&bpmp TEGRA264_CLK_SPI5>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "spi"; + assigned-clocks = <&bpmp TEGRA264_CLK_SPI5>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_SPI5>; + reset-names = "spi"; + }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra234-qspi.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra234-qspi.yaml new file mode 100644 index 00000000..bc28f421 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra234-qspi.yaml @@ -0,0 +1,235 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi@810c5b0000/nvidia,tegra234-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-qspi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/spi/spi-tegra210-quad.c + + The following nodes use this compatibility + - /bus@0/spi@810c5b0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-qspi + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc5b0000 + maximum: 0xc5b0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa1 + maximum: 0xa1 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2500 + maximum: 0x2500 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx + - tx + + + nvidia,clk-parents: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pllc0 + - pll_p + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x98 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - qspi + - qspi_out + - pllc0 + - pll_p + + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1d + maximum: 0x1d + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x20 + maximum: 0x98 + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x98 + maximum: 0x98 + + assigned-clock-rates: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xbebc1ff + maximum: 0xbebc1ff + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xbebc1ff + maximum: 0xbebc1ff + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - qspi + + +required: + - compatible + - reg + - interrupts + - iommus + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + spi@810c5b0000 { + compatible = "nvidia,tegra234-qspi"; + status = "disabled"; + reg = <0x81 0x0c5b0000 0x0 0x10000>; + interrupts = ; + iommus = <&smmu2_mmu TEGRA_SID_XSPI0>; + dma-coherent; + dma-names = "rx, tx"; + nvidia,clk-parents = "pllc0, pll_p"; + clocks = <&bpmp TEGRA264_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA264_CLK_QSPI0>, + <&bpmp TEGRA264_CLK_PLLC0>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "qspi, qspi_out, pllc0, pll_p"; + resets = <&bpmp TEGRA264_RESET_QSPI0>; + assigned-clocks = <&bpmp TEGRA264_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA264_CLK_PLLC0>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLC0>; + assigned-clock-rates = <199999999 199999999>; + reset-names = "qspi"; + }; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra234-spi.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra234-spi.yaml new file mode 100644 index 00000000..4af7ea0b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra234-spi.yaml @@ -0,0 +1,230 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi@c6c0000/nvidia,tegra234-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-spi is mentioned in the following drivers + - /kernel/kernel-oot/drivers/spi/spi-tegra114.c + + The following nodes use this compatibility + - /bus@0/spi@c6c0000 + - /bus@0/spi@810c590000 + - /bus@0/spi@810c440000 + - /bus@0/spi@810c450000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra234-spi + - nvidia,tegra210-spi + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc440000 + maximum: 0xc6c0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa4 + maximum: 0x216 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx + - tx + + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0xf + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8 + maximum: 0x19 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x808 + maximum: 0x80f + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x808 + maximum: 0x80f + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0xa0 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - spi + + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2a + maximum: 0x2d + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0xa0 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x24 + maximum: 0x27 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - spi + + +required: + - compatible + - reg + - interrupts + - iommus + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + spi@c6c0000 { + compatible = "nvidia,tegra234-spi, nvidia,tegra210-spi"; + status = "disabled"; + reg = <0x0 0x0c6c0000 0x0 0x10000>; + interrupts = ; + dma-coherent; + dma-names = "rx, tx"; + dmas = <&gpcdma 8 8 TEGRA264_GPCDMA_SID_SPI2>, + <&gpcdma 8 18 TEGRA264_GPCDMA_SID_SPI2>; + iommus = <&smmu1_mmu TEGRA264_GPCDMA_SID_SPI2>; + clocks = <&bpmp TEGRA264_CLK_SPI2>, + <&bpmp TEGRA264_CLK_PLLAON>, + <&bpmp TEGRA264_CLK_OSC>; + clock-names = "spi"; + assigned-clocks = <&bpmp TEGRA264_CLK_SPI2>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_SPI2>; + reset-names = "spi"; + }; diff --git a/Documentation/devicetree/bindings/spi/tegra-spidev.yaml b/Documentation/devicetree/bindings/spi/tegra-spidev.yaml new file mode 100644 index 00000000..8a2b597d --- /dev/null +++ b/Documentation/devicetree/bindings/spi/tegra-spidev.yaml @@ -0,0 +1,73 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi@0/tegra-spidev.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = tegra-spidev is mentioned in the following drivers + - /kernel/kernel-oot/drivers/spi/spidev.c + + The following nodes use this compatibility + - /bus@0/spi@c6c0000/spi@0 + - /bus@0/spi@810c590000/spi@0 + - /bus@0/spi@810c440000/spi@0 + - /bus@0/spi@810c450000/spi@0 + - /bus@0/spi@810c460000/spi@0 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - tegra-spidev + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + spi-max-frequency: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2faf080 + maximum: 0x2faf080 + +required: + - compatible + - reg + +examples: + - | + spi@0 { + }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra234-oc-event.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra234-oc-event.yaml new file mode 100644 index 00000000..aaaf1354 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra234-oc-event.yaml @@ -0,0 +1,55 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvtherm-oc-event/nvidia,tegra234-oc-event.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-oc-event is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/thermal/tegra234-oc-event.c + + The following nodes use this compatibility + - /nvtherm-oc-event + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-oc-event + + required: + - compatible + +properties: + + nvidia,bpmp: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + +examples: + - | + nvtherm-oc-event { + compatible = "nvidia,tegra234-oc-event"; + status = "disabled"; + nvidia,bpmp = <&bpmp>; + }; diff --git a/Documentation/devicetree/bindings/thermal/tegra/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/tegra/nvidia,tegra186-bpmp-thermal.yaml new file mode 100644 index 00000000..d5d2364f --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/tegra/nvidia,tegra186-bpmp-thermal.yaml @@ -0,0 +1,57 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra186-bpmp-thermal is mentioned in the following drivers + - /kernel/kernel-oot/drivers/thermal/tegra/tegra-bpmp-thermal.c + + The following nodes use this compatibility + - /bpmp/thermal + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra186-bpmp-thermal + + required: + - compatible + +properties: + + '#thermal-sensor-cells': + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1 + maximum: 0x1 + +required: + - compatible + +examples: + - | + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + status = "disabled"; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/tty/serial/arm,pl011.yaml b/Documentation/devicetree/bindings/tty/serial/arm,pl011.yaml new file mode 100644 index 00000000..e48367fb --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/arm,pl011.yaml @@ -0,0 +1,220 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial@810c500000/arm,pl011.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,pl011 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/tty/serial/amba-pl011.c + + The following nodes use this compatibility + - /bus@0/serial@810c500000 + - /bus@0/serial@810c510000 + - /bus@0/serial@a808800000 + - /bus@0/serial@810c530000 + - /bus@0/serial@810c540000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,pl011 + - arm,primecell + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8800000 + maximum: 0xc540000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xaa + maximum: 0x3b6 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x38 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - uartclk + - apb_pclk + + + assigned-clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x33 + maximum: 0x38 + + assigned-clock-parents: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x16 + maximum: 0x16 + + dmas: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0xd + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0x17 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x800 + maximum: 0x800 + + dma-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx + - tx + + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + arm,primecell-periphid: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x51011 + maximum: 0x51011 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x50 + maximum: 0x54 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - serial + + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + serial@810c500000 { + compatible = "arm,pl011, arm,primecell"; + reg = <0x81 0x0c500000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_UART4>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "uartclk, apb_pclk"; + assigned-clocks = <&bpmp TEGRA264_CLK_UART4>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + dmas = <&gpcdma 13 23 TEGRA_SID_GPCDMA>, + <&gpcdma 13 13 TEGRA_SID_GPCDMA>; + dma-names = "rx, tx"; + dma-coherent; + arm,primecell-periphid = <0x00051011>; + resets = <&bpmp TEGRA264_RESET_UART4>; + reset-names = "serial"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/tty/serial/arm,sbsa-uart.yaml b/Documentation/devicetree/bindings/tty/serial/arm,sbsa-uart.yaml new file mode 100644 index 00000000..1c3f5591 --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/arm,sbsa-uart.yaml @@ -0,0 +1,119 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial@c5f0000/arm,sbsa-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = arm,sbsa-uart is mentioned in the following drivers + - /kernel/kernel-oot/drivers/tty/serial/amba-pl011.c + + The following nodes use this compatibility + - /bus@0/serial@c5f0000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - arm,sbsa-uart + - arm,pl011 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc5f0000 + maximum: 0xc5f0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + reg-io-width: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x202 + maximum: 0x202 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + current-speed: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1c200 + maximum: 0x1c200 + + numa-node-id: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + +required: + - compatible + - reg + - interrupts + +examples: + - | + serial@c5f0000 { + compatible = "arm,sbsa-uart", + "arm,pl011"; + status = "disabled"; + reg = <0x0 0xc5f0000 0x0 0x10000>; + reg-io-width = <0x4>; + interrupts = ; + current-speed = <0x1c200>; + numa-node-id = <0>; + }; diff --git a/Documentation/devicetree/bindings/tty/serial/nvidia,tegra264-utc.yaml b/Documentation/devicetree/bindings/tty/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 00000000..75e3584e --- /dev/null +++ b/Documentation/devicetree/bindings/tty/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,116 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-utc@c4e0000/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-utc is mentioned in the following drivers + - /kernel/kernel-oot/drivers/tty/serial/tegra-utc.c + + The following nodes use this compatibility + - /bus@0/tegra-utc@c4e0000 + - /bus@0/tegra-utc@c5a0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-utc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc4e0000 + maximum: 0xc5a8000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000 + maximum: 0x8000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - rx + - tx + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x203 + maximum: 0x20f + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + current-speed: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1c200 + maximum: 0x1c200 + +required: + - compatible + - reg + - interrupts + +examples: + - | + tegra-utc@c4e0000 { + compatible = "nvidia,tegra264-utc"; + reg = <0x0 0x0c4e8000 0x0 0x8000>, + <0x0 0x0c4e0000 0x0 0x8000>; + reg-names = "rx, tx"; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/gadget/udc/nvidia,tegra264-xudc.yaml b/Documentation/devicetree/bindings/usb/gadget/udc/nvidia,tegra264-xudc.yaml new file mode 100644 index 00000000..5118f7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/gadget/udc/nvidia,tegra264-xudc.yaml @@ -0,0 +1,201 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a808670000/nvidia,tegra264-xudc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xudc is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/gadget/udc/tegra-xudc.c + + The following nodes use this compatibility + - /bus@0/usb@a808670000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xudc + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8670000 + maximum: 0x8678000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000 + maximum: 0x8000 + + reg-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - base + - fpci + + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2 + maximum: 0x2 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x103 + maximum: 0x10c + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dev + - ss + - ss_src + - fs_src + + + power-domains: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa + maximum: 0xb + + power-domain-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - dev + - ss + + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3708 + maximum: 0x3708 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + phys: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x27 + maximum: 0x28 + + phy-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - usb2-0 + - usb3-1 + + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + +examples: + - | + usb@a808670000 { + compatible = "nvidia,tegra264-xudc"; + reg = <0xa8 0x8670000 0x00 0x8000>, + <0xa8 0x8678000 0x00 0x8000>; + reg-names = "base, fpci"; + interrupts = <2 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA264_CLK_XUSB1_CORE_DEV>, + <&bpmp TEGRA264_CLK_XUSB1_CORE_SUPERSPEED>, + <&bpmp TEGRA264_CLK_XUSB1_SS>, + <&bpmp TEGRA264_CLK_XUSB1_FS>; + clock-names = "dev, ss, ss_src, fs_src"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_XUSB_DEV>, + <&bpmp TEGRA264_POWER_DOMAIN_XUSB_SS>; + power-domain-names = "dev, ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_DEV_MODE>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf1.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf1.yaml new file mode 100644 index 00000000..55b6f6fc --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf1.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80aa70000/nvidia,tegra264-xusb-vf1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf1 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80aa70000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf1 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xaa70000 + maximum: 0xaa70000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3b9 + maximum: 0x3b9 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3201 + maximum: 0x3601 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80aa70000 { + compatible = "nvidia,tegra264-xusb-vf1"; + reg = <0xa8 0xaa70000 0x0 0x40000>; + interrupts = <0 953 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF1_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF1_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF1_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF1_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF1_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf2.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf2.yaml new file mode 100644 index 00000000..6952c89f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf2.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80aac0000/nvidia,tegra264-xusb-vf2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf2 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80aac0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf2 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xaac0000 + maximum: 0xaac0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3ba + maximum: 0x3ba + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3202 + maximum: 0x3602 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80aac0000 { + compatible = "nvidia,tegra264-xusb-vf2"; + reg = <0xa8 0xaac0000 0x0 0x40000>; + interrupts = <0 954 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF2_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF2_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF2_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF2_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF2_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf3.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf3.yaml new file mode 100644 index 00000000..b2cf151c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf3.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80ab10000/nvidia,tegra264-xusb-vf3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf3 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80ab10000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf3 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xab10000 + maximum: 0xab10000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3bb + maximum: 0x3bb + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3203 + maximum: 0x3603 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80ab10000 { + compatible = "nvidia,tegra264-xusb-vf3"; + reg = <0xa8 0xab10000 0x0 0x40000>; + interrupts = <0 955 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF3_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF3_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF3_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF3_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF3_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf4.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf4.yaml new file mode 100644 index 00000000..d1489a2f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf4.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80ab60000/nvidia,tegra264-xusb-vf4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf4 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80ab60000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf4 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xab60000 + maximum: 0xab60000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3bc + maximum: 0x3bc + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3204 + maximum: 0x3604 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80ab60000 { + compatible = "nvidia,tegra264-xusb-vf4"; + reg = <0xa8 0xab60000 0x0 0x40000>; + interrupts = <0 956 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF4_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF4_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF4_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF4_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF4_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf5.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf5.yaml new file mode 100644 index 00000000..c71a11d8 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf5.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80abb0000/nvidia,tegra264-xusb-vf5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf5 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80abb0000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf5 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xabb0000 + maximum: 0xabb0000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3bd + maximum: 0x3bd + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3205 + maximum: 0x3605 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80abb0000 { + compatible = "nvidia,tegra264-xusb-vf5"; + reg = <0xa8 0xabb0000 0x0 0x40000>; + interrupts = <0 957 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF5_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF5_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF5_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF5_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF5_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf6.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf6.yaml new file mode 100644 index 00000000..ee1082fb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf6.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80ac00000/nvidia,tegra264-xusb-vf6.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf6 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80ac00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf6 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xac00000 + maximum: 0xac00000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3be + maximum: 0x3be + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3206 + maximum: 0x3606 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80ac00000 { + compatible = "nvidia,tegra264-xusb-vf6"; + reg = <0xa8 0xac00000 0x0 0x40000>; + interrupts = <0 958 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF6_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF6_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF6_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF6_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF6_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf7.yaml b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf7.yaml new file mode 100644 index 00000000..3a486481 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/host/nvidia,tegra264-xusb-vf7.yaml @@ -0,0 +1,128 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb@a80ac50000/nvidia,tegra264-xusb-vf7.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-xusb-vf7 is mentioned in the following drivers + - /kernel/kernel-oot/drivers/usb/host/xhci-tegra.c + + The following nodes use this compatibility + - /bus@0/usb@a80ac50000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-xusb-vf7 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xa8 + maximum: 0xa8 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xac50000 + maximum: 0xac50000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x40000 + maximum: 0x40000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3bf + maximum: 0x3bf + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x3207 + maximum: 0x3607 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,xusb-padctl: + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - reg + - interrupts + - iommus + +examples: + - | + usb@a80ac50000 { + compatible = "nvidia,tegra264-xusb-vf7"; + reg = <0xa8 0xac50000 0x0 0x40000>; + interrupts = <0 959 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&smmu1_mmu TEGRA_SID_XUSB_VF7_HS_PORTS>, + <&smmu1_mmu TEGRA_SID_XUSB_VF7_SS_PORT1>, + <&smmu1_mmu TEGRA_SID_XUSB_VF7_SS_PORT2>, + <&smmu1_mmu TEGRA_SID_XUSB_VF7_SS_PORT3>, + <&smmu1_mmu TEGRA_SID_XUSB_VF7_SS_PORT4>; + dma-coherent; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra234-vi-thi.yaml b/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra234-vi-thi.yaml new file mode 100644 index 00000000..9613fe14 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra234-vi-thi.yaml @@ -0,0 +1,79 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vi0-thi@8188700000/nvidia,tegra234-vi-thi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra234-vi-thi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/capture/capture-support.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/vi0-thi@8188700000 + - /bus@0/host1x@8181200000/vi1-thi@8188f00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra234-vi-thi + + required: + - compatible + +properties: + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x2e + maximum: 0x2f + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - vi_thi + - vi2_thi + + +required: + - compatible + - resets + - reset-names + +examples: + - | + vi0-thi@8188700000 { + compatible = "nvidia,tegra234-vi-thi"; + resets = <&bpmp TEGRA264_RESET_VI>; + reset-names = "vi_thi"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra264-isp-thi.yaml b/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra264-isp-thi.yaml new file mode 100644 index 00000000..7a73a0cf --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/capture/nvidia,tegra264-isp-thi.yaml @@ -0,0 +1,79 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/isp-thi@8188b00000/nvidia,tegra264-isp-thi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-isp-thi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/capture/capture-support-t264.h + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/isp-thi@8188b00000 + - /bus@0/host1x@8181200000/isp1-thi@818ab00000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-isp-thi + + required: + - compatible + +properties: + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x37 + maximum: 0x37 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - isp_thi + - isp1_thi + + +required: + - compatible + - resets + - reset-names + +examples: + - | + isp-thi@8188b00000 { + compatible = "nvidia,tegra264-isp-thi"; + resets = <&bpmp TEGRA264_RESET_ISP1>; + reset-names = "isp_thi"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/isp/nvidia,tegra264-isp.yaml b/Documentation/devicetree/bindings/video/tegra/host/isp/nvidia,tegra264-isp.yaml new file mode 100644 index 00000000..4d5824e7 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/isp/nvidia,tegra264-isp.yaml @@ -0,0 +1,158 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/isp@8188800000/nvidia,tegra264-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-isp is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/isp/isp5.c + - /kernel/nvidia-oot/drivers/video/tegra/host/isp/isp5-t264.h + - /kernel/nvidia-oot/drivers/video/tegra/host/capture/capture-support-t264.h + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/isp@8188800000 + - /bus@0/host1x@8181200000/isp1@818a800000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra264-isp + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x81 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x88800000 + maximum: 0x88800000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x300000 + maximum: 0x300000 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x13 + maximum: 0x37 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - isp + - isp1 + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0x10 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - isp + - isp1 + + + nvidia,isp-falcon-device: + $ref: "/schemas/types.yaml#/definitions/uint32" + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xc01 + maximum: 0xd01 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - resets + - reset-names + - clocks + - clock-names + - iommus + +examples: + - | + isp@8188800000 { + compatible = "nvidia,tegra264-isp"; + reg = <0x81 0x88800000 0x0 0x00300000>; + resets = <&bpmp TEGRA264_RESET_ISP>; + reset-names = "isp"; + clocks = <&bpmp TEGRA264_CLK_ISP>; + clock-names = "isp"; + nvidia,isp-falcon-device = <&isp_thi>; + iommus = <&smmu4_mmu TEGRA_SID_ISP_VM1>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/nvcsi/nvidia,tegra194-nvcsi.yaml b/Documentation/devicetree/bindings/video/tegra/host/nvcsi/nvidia,tegra194-nvcsi.yaml new file mode 100644 index 00000000..32d54ec9 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/nvcsi/nvidia,tegra194-nvcsi.yaml @@ -0,0 +1,103 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvcsi@8188000000/nvidia,tegra194-nvcsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra194-nvcsi is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/nvcsi/nvcsi-t194.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/nvcsi@8188000000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra194-nvcsi + + required: + - compatible + +properties: + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x14 + maximum: 0x14 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvcsi + + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x15 + maximum: 0x15 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - nvcsi + + +required: + - compatible + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + nvcsi@8188000000 { + compatible = "nvidia,tegra194-nvcsi"; + clocks = <&bpmp TEGRA264_CLK_NVCSI>; + clock-names = "nvcsi"; + resets = <&bpmp TEGRA264_RESET_NVCSI>; + reset-names = "nvcsi"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,pva-tegra264-iommu-context.yaml b/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,pva-tegra264-iommu-context.yaml new file mode 100644 index 00000000..84353882 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,pva-tegra264-iommu-context.yaml @@ -0,0 +1,80 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pva0_niso1_ctx0/nvidia,pva-tegra264-iommu-context.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,pva-tegra264-iommu-context is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/pva/pva_iommu_context_dev.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx0 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx1 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx2 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx3 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx4 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx5 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx6 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx7 + - /bus@0/host1x@8181200000/pva0@818c000000/pva0_niso1_ctx8 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,pva-tegra264-iommu-context + + required: + - compatible + +properties: + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1101 + maximum: 0x1109 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - iommus + +examples: + - | + pva0_niso1_ctx0 { + compatible = "nvidia,pva-tegra264-iommu-context"; + iommus = <&smmu4_mmu (TEGRA_SID_PVA+0x2)>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,tegra264-pva.yaml b/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,tegra264-pva.yaml new file mode 100644 index 00000000..cb5cb6c5 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/host/pva/nvidia,tegra264-pva.yaml @@ -0,0 +1,198 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pva0@818c000000/nvidia,tegra264-pva.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra264-pva is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/host/pva/pva.c + + The following nodes use this compatibility + - /bus@0/host1x@8181200000/pva0@818c000000 + +select: + properties: + compatible: + minItems: 2 + maxItems: 2 + items: + enum: + - nvidia,tegra264-pva + - simple-bus + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x81 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10700000 + maximum: 0x8c000000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x100000 + maximum: 0x900000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x195 + maximum: 0x19d + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + resets: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Resets are given by a tuple of 2 values: + - Phandle to the device + - Reset ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x30 + maximum: 0x30 + + reset-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - pva0 + + + clocks: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Clocks are given by a tuple of 2 values: + - Phandle to the device + - Clock ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x13 + maximum: 0x18 + + clock-names: + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + enum: + - axi + - vps0 + - vps1 + + + power-domains: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x15 + maximum: 0x15 + + iommus: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + iommus are given by a tuple of 2 values: + - Phandle to the device + - Device ID + items: + minItems: 2 + maxItems: 2 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x1100 + maximum: 0x1100 + + dma-coherent: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - clocks + - clock-names + - iommus + +examples: + - | + pva0@818c000000 { + compatible = "nvidia,tegra264-pva, simple-bus"; + reg = <0x81 0x8c000000 0x0 0x900000>, + <0x0 0x10700000 0x0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + ; + resets = <&bpmp TEGRA264_RESET_PVA0_ALL>; + reset-names = "pva0"; + clocks = <&bpmp TEGRA264_CLK_PVA0_CPU_AXI>, + <&bpmp TEGRA264_CLK_NAFLL_PVA0_VPS>, + <&bpmp TEGRA264_CLK_PVA0_VPS>; + clock-names = "axi, vps0, vps1"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_PVA0>; + iommus = <&smmu4_mmu TEGRA_SID_PVA>; + dma-coherent; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,carveouts-t19x.yaml b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,carveouts-t19x.yaml new file mode 100644 index 00000000..e2daae5c --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,carveouts-t19x.yaml @@ -0,0 +1,55 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra-carveouts/nvidia,carveouts-t19x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,carveouts-t19x is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_init.c + + The following nodes use this compatibility + - /tegra-carveouts + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,carveouts-t19x + + required: + - compatible + +properties: + + dont-convert-iovmm-to-carveout: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + +examples: + - | + tegra-carveouts { + compatible = "nvidia,carveouts-t19x"; + memory-region = <&vpr &fsi_reserved &vpr1>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr-carveout.yaml b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr-carveout.yaml new file mode 100644 index 00000000..d0f2d372 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr-carveout.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vpr-carveout/nvidia,vpr-carveout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,vpr-carveout is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_init.c + + The following nodes use this compatibility + - /reserved-memory/vpr-carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,vpr-carveout + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + vpr-carveout { + compatible = "nvidia,vpr-carveout"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr1-carveout.yaml b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr1-carveout.yaml new file mode 100644 index 00000000..d3431a06 --- /dev/null +++ b/Documentation/devicetree/bindings/video/tegra/nvmap/nvidia,vpr1-carveout.yaml @@ -0,0 +1,51 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/vpr1-carveout/nvidia,vpr1-carveout.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,vpr1-carveout is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/video/tegra/nvmap/nvmap_init.c + + The following nodes use this compatibility + - /reserved-memory/vpr1-carveout + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,vpr1-carveout + + required: + - compatible + +properties: + +required: + - compatible + +examples: + - | + vpr1-carveout { + compatible = "nvidia,vpr1-carveout"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/virt/tegra/nvidia,tegra-hv-pm-ctl.yaml b/Documentation/devicetree/bindings/virt/tegra/nvidia,tegra-hv-pm-ctl.yaml new file mode 100644 index 00000000..dcc9d8b3 --- /dev/null +++ b/Documentation/devicetree/bindings/virt/tegra/nvidia,tegra-hv-pm-ctl.yaml @@ -0,0 +1,54 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/tegra_hv_pm_ctl/nvidia,tegra-hv-pm-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-hv-pm-ctl is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/virt/tegra/tegra_hv_pm_ctl.c + + The following nodes use this compatibility + - /tegra_hv_pm_ctl + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-hv-pm-ctl + + required: + - compatible + +properties: + + ivc: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0xf + maximum: 0xc8 + +required: + - compatible + +examples: + - | + tegra_hv_pm_ctl { + }; diff --git a/Documentation/devicetree/bindings/watchdog/nvidia,tegra-wdt-t264.yaml b/Documentation/devicetree/bindings/watchdog/nvidia,tegra-wdt-t264.yaml new file mode 100644 index 00000000..0727b387 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nvidia,tegra-wdt-t264.yaml @@ -0,0 +1,146 @@ +# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog@8110000/nvidia,tegra-wdt-t264.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FIXME -- add title + +maintainers: + - FIXME -- add maintainers + +description: | + the compatability = nvidia,tegra-wdt-t264 is mentioned in the following drivers + - /kernel/nvidia-oot/drivers/watchdog/watchdog-tegra-t18x.c + + The following nodes use this compatibility + - /bus@0/watchdog@8110000 + +select: + properties: + compatible: + minItems: 1 + maxItems: 1 + items: + enum: + - nvidia,tegra-wdt-t264 + + required: + - compatible + +properties: + + reg: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Registers are given by a tuple of two values: + - register address: + - register block size. + items: + minItems: 4 + maxItems: 4 + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x8000000 + maximum: 0x8110000 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x10000 + maximum: 0x10000 + + interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Interrupts are give by a tuple of 3 values: + - interrupt specifier (GIC_SPI = 0, GIC_PPI = 1) + definitions in dt-bindings/interrupt-controller/arm-gic.h + - interrupt number + - trigger type (rising edge, falling edge, both, etc) + definitions in dt-bindings/interrupt-controller/irq.h + items: + items: + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x305 + maximum: 0x308 + - $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x4 + maximum: 0x4 + + nvidia,watchdog-index: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,timer-index: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + nvidia,shared-interrupt: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x0 + maximum: 0x0 + + timeout-sec: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x78 + maximum: 0x78 + + nvidia,wdt-error-threshold: + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x5 + maximum: 0x5 + + nvidia,extend-watchdog-suspend: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,disable-debug-reset: + $ref: "/schemas/types.yaml#/definitions/flag" + + nvidia,disable-por-reset: + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + +examples: + - | + watchdog@8110000 { + compatible = "nvidia,tegra-wdt-t264"; + reg = <0x0 0x08110000 0x0 0x10000>, + <0x0 0x08010000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x10000>; + interrupts = , + , + , + ; + nvidia,watchdog-index = <0>; + nvidia,timer-index = <0>; + nvidia,shared-interrupt = <0>; + timeout-sec = <120>; + nvidia,wdt-error-threshold = <5>; + nvidia,extend-watchdog-suspend; + nvidia,disable-debug-reset; + nvidia,disable-por-reset; + status = "disabled"; + };