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tegra_bootloader_debug: Add functions to read from cmd line

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Add functions to tegra_bootloader_debug to read addresses
from kernel command line for 5.15.

Bug 3896536

Change-Id: Ie0f75bab54b9455ce465740a2ab06a54046657fd
Signed-off-by: praagarwal <praagarwal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2908980
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
praagarwal
2023-05-23 07:15:45 +00:00
committed by mobile promotions
parent 9a0d5b4bb1
commit a88e0ab87c
4 changed files with 82 additions and 200 deletions
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1
drivers/platform/tegra/Makefile
View File

@@ -2,7 +2,6 @@
# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
tegra-bootloader-debug-objs := tegra_bootloader_debug.o
tegra-bootloader-debug-objs += tegra_bootloader_debug_init.o
obj-m += tegra-bootloader-debug.o
tegra-cactmon-objs := cactmon.o

83
drivers/platform/tegra/tegra_bootloader_debug.c
View File

@@ -14,7 +14,16 @@
#include <linux/slab.h>
#include <linux/memblock.h>
#include <asm/page.h>
#include "tegra_bootloader_debug.h"
#include <linux/types.h>
static phys_addr_t tegra_bl_debug_data_start;
static phys_addr_t tegra_bl_debug_data_size;
static phys_addr_t tegra_bl_prof_start;
static phys_addr_t tegra_bl_prof_size;
static phys_addr_t tegra_bl_prof_ro_start;
static phys_addr_t tegra_bl_prof_ro_size;
static phys_addr_t tegra_bl_bcp_start;
static phys_addr_t tegra_bl_bcp_size;
static const char *module_name = "tegra_bootloader_debug";
static const char *dir_name = "tegra_bootloader";
@@ -27,6 +36,11 @@ static const char *gr_file_cpu_bl = "gr_cpu_bl";
static const char *boot_cfg = "boot_cfg";
#endif
static char *bl_debug_data = "0@0x0";
static char *bl_prof_dataptr = "0@0x0";
static char *bl_prof_ro_ptr = "0@0x0";
static char *bl_bcp_ptr = "0@0x0";
struct gr_address_value {
unsigned int gr_address;
unsigned int gr_value;
@@ -570,8 +584,70 @@ static int boot_cfg_open(struct inode *inode, struct file *file)
}
#endif /* CONFIG_DEBUG_FS */
static int __init tegra_bl_args(char *options, phys_addr_t *tegra_bl_arg_size,
phys_addr_t *tegra_bl_arg_start)
{
char *p = options;
*tegra_bl_arg_size = memparse(p, &p);
if (!p)
return -EINVAL;
if (*p != '@')
return -EINVAL;
*tegra_bl_arg_start = memparse(p + 1, &p);
if (!(*tegra_bl_arg_size) || !(*tegra_bl_arg_start)) {
*tegra_bl_arg_size = 0;
*tegra_bl_arg_start = 0;
return 0;
}
if (pfn_valid(__phys_to_pfn(*tegra_bl_arg_start))) {
pr_err("pfn_valid is true for %08llx@%08llx\n",
(u64)*tegra_bl_arg_size,
(u64)*tegra_bl_arg_start);
*tegra_bl_arg_size = 0;
*tegra_bl_arg_start = 0;
return -ENXIO;
}
return 0;
}
static int __init tegra_bl_debuginit_module_init(void)
{
int err = 0;
err = tegra_bl_args(bl_prof_dataptr,
&tegra_bl_prof_size,
&tegra_bl_prof_start);
if (err != 0)
return err;
err = tegra_bl_args(bl_prof_ro_ptr,
&tegra_bl_prof_ro_size,
&tegra_bl_prof_ro_start);
if (err != 0)
return err;
err = tegra_bl_args(bl_debug_data,
&tegra_bl_debug_data_size,
&tegra_bl_debug_data_start);
if (err != 0)
return err;
err = tegra_bl_args(bl_bcp_ptr,
&tegra_bl_bcp_size,
&tegra_bl_bcp_start);
if (err != 0)
return err;
return tegra_bootloader_debuginit();
}
@@ -606,6 +682,11 @@ static void __exit tegra_bl_debuginit_module_exit(void)
iounmap(usc);
}
module_param(bl_debug_data, charp, 0400);
module_param(bl_prof_dataptr, charp, 0400);
module_param(bl_prof_ro_ptr, charp, 0400);
module_param(bl_bcp_ptr, charp, 0400);
module_init(tegra_bl_debuginit_module_init);
module_exit(tegra_bl_debuginit_module_exit);

17
drivers/platform/tegra/tegra_bootloader_debug.h
View File

@@ -1,17 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
#ifndef __TEGRA_BOOTLOADER_DEBUG_H
#define __TEGRA_BOOTLOADER_DEBUG_H
extern phys_addr_t tegra_bl_debug_data_start;
extern phys_addr_t tegra_bl_debug_data_size;
extern phys_addr_t tegra_bl_prof_start;
extern phys_addr_t tegra_bl_prof_size;
extern phys_addr_t tegra_bl_prof_ro_start;
extern phys_addr_t tegra_bl_prof_ro_size;
extern phys_addr_t tegra_bl_bcp_start;
extern phys_addr_t tegra_bl_bcp_size;
size_t tegra_bl_add_profiler_entry(const char *buf, size_t len);
#endif

181
drivers/platform/tegra/tegra_bootloader_debug_init.c
View File

@@ -1,181 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
#include <linux/types.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/memblock.h>
#include <asm/page.h>
phys_addr_t tegra_bl_debug_data_start;
EXPORT_SYMBOL(tegra_bl_debug_data_start);
phys_addr_t tegra_bl_debug_data_size;
EXPORT_SYMBOL(tegra_bl_debug_data_size);
phys_addr_t tegra_bl_prof_start;
EXPORT_SYMBOL(tegra_bl_prof_start);
phys_addr_t tegra_bl_prof_size;
EXPORT_SYMBOL(tegra_bl_prof_size);
phys_addr_t tegra_bl_prof_ro_start;
EXPORT_SYMBOL(tegra_bl_prof_ro_start);
phys_addr_t tegra_bl_prof_ro_size;
EXPORT_SYMBOL(tegra_bl_prof_ro_size);
phys_addr_t tegra_bl_bcp_start;
EXPORT_SYMBOL(tegra_bl_bcp_start);
phys_addr_t tegra_bl_bcp_size;
EXPORT_SYMBOL(tegra_bl_bcp_size);
#ifndef MODULE
static int __init tegra_bl_prof_arg(char *option)
{
char *p = option;
tegra_bl_prof_size = memparse(p, &p);
if (!p)
return -EINVAL;
if (*p != '@')
return -EINVAL;
tegra_bl_prof_start = memparse(p + 1, &p);
if (!tegra_bl_prof_size || !tegra_bl_prof_start) {
tegra_bl_prof_size = 0;
tegra_bl_prof_start = 0;
return -ENXIO;
}
if (pfn_valid(__phys_to_pfn(tegra_bl_prof_start))) {
if (memblock_reserve(tegra_bl_prof_start, tegra_bl_prof_size)) {
pr_err("Failed to reserve bl_prof_data %08llx@%08llx\n",
(u64)tegra_bl_prof_size,
(u64)tegra_bl_prof_start);
tegra_bl_prof_size = 0;
tegra_bl_prof_start = 0;
return -ENXIO;
}
}
return 0;
}
early_param("bl_prof_dataptr", tegra_bl_prof_arg);
static int __init tegra_bl_prof_ro_arg(char *option)
{
char *p = option;
tegra_bl_prof_ro_size = memparse(p, &p);
if (!p)
return -EINVAL;
if (*p != '@')
return -EINVAL;
tegra_bl_prof_ro_start = memparse(p + 1, &p);
if (!tegra_bl_prof_ro_size || !tegra_bl_prof_ro_start) {
tegra_bl_prof_ro_size = 0;
tegra_bl_prof_ro_start = 0;
return -ENXIO;
}
if (pfn_valid(__phys_to_pfn(tegra_bl_prof_ro_start))) {
if (memblock_reserve(tegra_bl_prof_ro_start, tegra_bl_prof_ro_size)) {
pr_err("Failed to reserve bl_prof_ro_data %08llx@%08llx\n",
(u64)tegra_bl_prof_ro_size,
(u64)tegra_bl_prof_ro_start);
tegra_bl_prof_ro_size = 0;
tegra_bl_prof_ro_start = 0;
return -ENXIO;
}
}
return 0;
}
early_param("bl_prof_ro_ptr", tegra_bl_prof_ro_arg);
static int __init tegra_bl_debug_data_arg(char *options)
{
char *p = options;
tegra_bl_debug_data_size = memparse(p, &p);
if (!p)
return -EINVAL;
if (*p != '@')
return -EINVAL;
tegra_bl_debug_data_start = memparse(p + 1, &p);
if (!tegra_bl_debug_data_size || !tegra_bl_debug_data_start) {
tegra_bl_debug_data_size = 0;
tegra_bl_debug_data_start = 0;
return -ENXIO;
}
if (pfn_valid(__phys_to_pfn(tegra_bl_debug_data_start))) {
if (memblock_reserve(tegra_bl_debug_data_start,
tegra_bl_debug_data_size)) {
pr_err("Failed to reserve bl_debug_data %08llx@%08llx\n",
(u64)tegra_bl_debug_data_size,
(u64)tegra_bl_debug_data_start);
tegra_bl_debug_data_size = 0;
tegra_bl_debug_data_start = 0;
return -ENXIO;
}
}
return 0;
}
early_param("bl_debug_data", tegra_bl_debug_data_arg);
static int tegra_bl_bcp_arg(char *options)
{
char *p = options;
tegra_bl_bcp_size = memparse(p, &p);
if (!p)
return -EINVAL;
if (*p != '@')
return -EINVAL;
tegra_bl_bcp_start = memparse(p + 1, &p);
if (!tegra_bl_bcp_size || !tegra_bl_bcp_start) {
tegra_bl_bcp_size = 0;
tegra_bl_bcp_start = 0;
return -ENXIO;
}
if (pfn_valid(__phys_to_pfn(tegra_bl_bcp_start))) {
if (memblock_reserve(tegra_bl_bcp_start,
tegra_bl_bcp_size)) {
pr_err("Failed to reserve boot_cfg_data %08llx@%08llx\n",
(u64)tegra_bl_bcp_size,
(u64)tegra_bl_bcp_start);
tegra_bl_bcp_size = 0;
tegra_bl_bcp_start = 0;
return -ENXIO;
}
}
pr_warn("Got boot_cfg_data %08llx@%08llx\n",
(u64)tegra_bl_bcp_size,
(u64)tegra_bl_bcp_start);
return 0;
}
early_param("boot_cfg_dataptr", tegra_bl_bcp_arg);
#else
#endif