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PCI: epf: dma-test: Add negative tests for EP and DMA
Add negative tests for EP API's set_bar and clear_bar. Add negative tests for all DMA API's JIRA NET-2400 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Change-Id: If1b171f67b4c0a372e2a515704893609b7d11b76 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3313976 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Nagarjuna Kristam
committed by
Jon Hunter
Jon Hunter
parent
04ccb5c0c3
commit
ab18e366eb
@@ -148,6 +148,223 @@ static int edmalib_test_ob(struct seq_file *s, void *data)
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return ret;
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}
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static void validate_api_status(char *api, char *cond, tegra_pcie_dma_status_t act,
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tegra_pcie_dma_status_t exp)
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{
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if (act == exp)
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pr_info("%s() condition -%s- Passed with expected val %d\n", api, cond, act);
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else
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pr_err("%s() condition -%s- Failed actual %d expected %d\n", api, cond, act, exp);
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}
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static void sanitize_dma_info(struct tegra_pcie_dma_init_info *info, struct pcie_epf_dma *epfnv)
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{
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info->soc = NVPCIE_DMA_SOC_T264;
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info->tx[0].ch_type = TEGRA_PCIE_DMA_CHAN_XFER_ASYNC;
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info->tx[0].num_descriptors = 4096;
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info->dev = epfnv->cdev;
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info->msi_irq = epfnv->edma.msi_irq;
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}
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static void sanitize_dma_xfer(struct tegra_pcie_dma_xfer_info *xfer,
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struct tegra_pcie_dma_desc *desc)
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{
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xfer->channel_num = 0;
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xfer->complete = edma_complete;
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xfer->nents = 100;
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xfer->desc = desc;
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}
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static int dma_neg_test(struct seq_file *s, void *data)
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{
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struct pcie_epf_dma *epfnv = (struct pcie_epf_dma *)dev_get_drvdata(s->private);
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struct pcie_epf_bar *epf_bar = (struct pcie_epf_bar *)epfnv->bar_virt;
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struct tegra_pcie_dma_init_info info = {};
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tegra_pcie_dma_status_t status;
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struct tegra_pcie_dma_xfer_info xfer = {};
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struct tegra_pcie_dma_desc desc = {};
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void *prv;
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if ((epfnv->chip_id == TEGRA234) || (!epf_bar->rp_phy_addr)) {
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dev_err(epfnv->fdev, "%s: Not supported for T234 or Link is not up\n", __func__);
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return -EOPNOTSUPP;
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}
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sanitize_dma_info(&info, epfnv);
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status = tegra_pcie_dma_initialize(NULL, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "init NULL", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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info.tx[0].num_descriptors = 0;
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "No channel enabled", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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info.tx[0].num_descriptors = 15;
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "Descriptors not power of 2", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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info.tx[0].num_descriptors = 0x80000000;
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "Max num descriptor check", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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status = tegra_pcie_dma_initialize(&info, NULL);
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validate_api_status("tegra_pcie_dma_initialize", "Cookie is NULL", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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info.dev = NULL;
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "dev param is NULL", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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info.soc = 0xFF; /* Invalid SoC type */
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "Invalid SoC type", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_info(&info, epfnv);
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status = tegra_pcie_dma_initialize(&info, &prv);
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validate_api_status("tegra_pcie_dma_initialize", "All valid params", status,
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TEGRA_PCIE_DMA_SUCCESS);
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status = tegra_pcie_dma_set_msi(NULL, 0, 0);
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validate_api_status("tegra_pcie_dma_set_msi", "NULL cookie", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_xfer(&xfer, &desc);
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xfer.channel_num = 1;
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status = tegra_pcie_dma_submit_xfer(prv, &xfer);
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validate_api_status("tegra_pcie_dma_submit_xfer", "Invalid channel", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_xfer(&xfer, &desc);
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xfer.complete = NULL;
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status = tegra_pcie_dma_submit_xfer(prv, &xfer);
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validate_api_status("tegra_pcie_dma_submit_xfer", "NULL complete", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_xfer(&xfer, &desc);
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xfer.nents = 0;
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status = tegra_pcie_dma_submit_xfer(prv, &xfer);
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validate_api_status("tegra_pcie_dma_submit_xfer", "no nents", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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sanitize_dma_xfer(&xfer, &desc);
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status = tegra_pcie_dma_submit_xfer(NULL, &xfer);
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validate_api_status("tegra_pcie_dma_submit_xfer", "NULL cookie", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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status = tegra_pcie_dma_submit_xfer(prv, NULL);
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validate_api_status("tegra_pcie_dma_submit_xfer", "NULL xfer", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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status = tegra_pcie_dma_stop(NULL);
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validate_api_status("tegra_pcie_dma_stop", "NULL cookie", status,
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(tegra_pcie_dma_status_t)false);
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status = tegra_pcie_dma_deinit(NULL);
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validate_api_status("tegra_pcie_dma_deinit", "NULL cookie", status,
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TEGRA_PCIE_DMA_FAIL_INVAL_INPUTS);
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status = tegra_pcie_dma_stop(prv);
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validate_api_status("tegra_pcie_dma_stop", "Valid param", status,
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(tegra_pcie_dma_status_t)true);
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status = tegra_pcie_dma_deinit(&prv);
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validate_api_status("tegra_pcie_dma_deinit", "Valid param", status, TEGRA_PCIE_DMA_SUCCESS);
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return 0;
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}
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static void validate_bar(struct pcie_epf_dma *epfnv, struct pci_epf_bar *bar, char *err_str)
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{
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int ret = lpci_epc_set_bar(epfnv->epc, epfnv->epf->func_no, bar);
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if (ret < 0)
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dev_err(epfnv->fdev, "%s - Passed: %d\n", err_str, ret);
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else
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dev_err(epfnv->fdev, "%s - Failed\n", err_str);
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}
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static void sanitize_bar(struct pci_epf_bar *bar)
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{
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bar->barno = BAR_1;
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bar->size = SZ_64M;
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bar->flags = PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH;
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}
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static int bar_neg_test(struct seq_file *s, void *data)
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{
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struct pcie_epf_dma *epfnv = (struct pcie_epf_dma *)dev_get_drvdata(s->private);
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struct pcie_epf_bar *epf_bar = (struct pcie_epf_bar *)epfnv->bar_virt;
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struct pci_epf_bar bar = {};
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if (epfnv->chip_id == TEGRA234) {
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dev_err(epfnv->fdev, "%s: Not supported for T234 or when Link is already up\n",
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__func__);
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return -EOPNOTSUPP;
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}
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bar.phys_addr = epf_bar->rp_phy_addr;
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if (epf_bar->rp_phy_addr) {
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sanitize_bar(&bar);
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validate_bar(epfnv, &bar, "set_bar post link up");
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return 0;
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}
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sanitize_bar(&bar);
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bar.flags = PCI_BASE_ADDRESS_MEM_TYPE_32 | PCI_BASE_ADDRESS_MEM_PREFETCH;
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validate_bar(epfnv, &bar, "non 64-bit bar check");
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sanitize_bar(&bar);
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bar.size = SZ_32;
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validate_bar(epfnv, &bar, "BAR1 less than 64M size check");
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sanitize_bar(&bar);
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bar.size = SZ_64 - 1;
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validate_bar(epfnv, &bar, "BAR1 non power of 2 check");
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sanitize_bar(&bar);
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bar.barno = BAR_2;
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validate_bar(epfnv, &bar, "BAR2 non 32 MB check");
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sanitize_bar(&bar);
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bar.size = (SZ_32G * 2) + 1;
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validate_bar(epfnv, &bar, "BAR1 64 GB+1 check");
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sanitize_bar(&bar);
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bar.barno = BAR_3;
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validate_bar(epfnv, &bar, "BAR3 non supported check");
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return 0;
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}
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static int clear_bar(struct seq_file *s, void *data)
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{
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struct pcie_epf_dma *epfnv = (struct pcie_epf_dma *)dev_get_drvdata(s->private);
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struct pcie_epf_bar *epf_bar = (struct pcie_epf_bar *)epfnv->bar_virt;
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struct pci_epf_bar *bar = &epfnv->epf->bar[BAR_2];
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if ((epfnv->chip_id == TEGRA234) || (!epf_bar->rp_phy_addr)) {
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dev_err(epfnv->fdev, "%s: Not supported for T234 or when Link is not up\n",
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__func__);
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return -EOPNOTSUPP;
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}
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lpci_epc_clear_bar(epfnv->epc, epfnv->epf->func_no, bar);
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dev_err(epfnv->fdev, "%s: EPF BAR_2 Clear attempted. Check BAR0/1 access\n",
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__func__);
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return 0;
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}
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static void init_debugfs(struct pcie_epf_dma *epfnv)
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{
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debugfs_create_devm_seqfile(epfnv->fdev, "edmalib_test", epfnv->debugfs, edmalib_test);
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@@ -155,6 +372,13 @@ static void init_debugfs(struct pcie_epf_dma *epfnv)
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debugfs_create_devm_seqfile(epfnv->fdev, "edmalib_test_ob", epfnv->debugfs,
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edmalib_test_ob);
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debugfs_create_devm_seqfile(epfnv->fdev, "dma_neg_test", epfnv->debugfs, dma_neg_test);
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debugfs_create_devm_seqfile(epfnv->fdev, "bar_neg_test", epfnv->debugfs, bar_neg_test);
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debugfs_create_devm_seqfile(epfnv->fdev, "clear_bar", epfnv->debugfs, clear_bar);
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debugfs_create_u32("dma_size", 0644, epfnv->debugfs, &epfnv->dma_size);
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epfnv->dma_size = SZ_1M;
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epfnv->edma.st_as_ch = -1;
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