From ac16d3a12bab34dc3fe00d9348827c8628176fdf Mon Sep 17 00:00:00 2001 From: Manish Bhardwaj Date: Thu, 8 Dec 2022 13:59:02 +0000 Subject: [PATCH] nvidia-oot: sync vse driver with nvidia repo Using this patch we are syncing changes of vse driver from nvidia repo to nvidia-oot repo JIRA ESLC-7104 Change-Id: I5d45f4b645ad9c002c8f3b178fc20eb6f7324cd3 Signed-off-by: Manish Bhardwaj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2824196 Reviewed-by: Suresh Venkatachalam Reviewed-by: Sandeep Trasi GVS: Gerrit_Virtual_Submit --- drivers/crypto/tegra-hv-vse-safety.c | 10 +++++-- drivers/crypto/tegra-hv-vse.h | 4 +++ drivers/crypto/tegra-nvvse-cryptodev.c | 35 +++++++++++++++++++++++ include/uapi/misc/tegra-nvvse-cryptodev.h | 16 +++++++++++ 4 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/tegra-hv-vse-safety.c b/drivers/crypto/tegra-hv-vse-safety.c index ce8f3d54..c53103f2 100644 --- a/drivers/crypto/tegra-hv-vse-safety.c +++ b/drivers/crypto/tegra-hv-vse-safety.c @@ -415,8 +415,8 @@ struct tegra_virtual_se_aes_req_context { enum se_engine_id { VIRTUAL_SE_AES0, VIRTUAL_SE_AES1, - VIRTUAL_SE_SHA = 3, - VIRTUAL_MAX_SE_ENGINE_NUM = 5 + VIRTUAL_SE_SHA = 2, + VIRTUAL_MAX_SE_ENGINE_NUM = 7 }; enum tegra_virtual_se_aes_iv_type { @@ -427,6 +427,12 @@ enum tegra_virtual_se_aes_iv_type { static struct tegra_virtual_se_dev *g_virtual_se_dev[VIRTUAL_MAX_SE_ENGINE_NUM]; +struct crypto_dev_to_ivc_map *tegra_hv_vse_get_db(void) +{ + return &g_crypto_to_ivc_map[0]; +} +EXPORT_SYMBOL(tegra_hv_vse_get_db); + static int tegra_hv_vse_safety_send_ivc( struct tegra_virtual_se_dev *se_dev, struct tegra_hv_ivc_cookie *pivck, diff --git a/drivers/crypto/tegra-hv-vse.h b/drivers/crypto/tegra-hv-vse.h index 3eeb9d73..db6c3683 100644 --- a/drivers/crypto/tegra-hv-vse.h +++ b/drivers/crypto/tegra-hv-vse.h @@ -138,4 +138,8 @@ struct tegra_virtual_se_req_context { /*Crypto dev instance*/ uint32_t node_id; }; + +/* API to get ivc db from hv_vse driver */ +struct crypto_dev_to_ivc_map *tegra_hv_vse_get_db(void); + #endif /*__TEGRA_HV_VSE_H*/ diff --git a/drivers/crypto/tegra-nvvse-cryptodev.c b/drivers/crypto/tegra-nvvse-cryptodev.c index ce08d516..8217acdd 100644 --- a/drivers/crypto/tegra-nvvse-cryptodev.c +++ b/drivers/crypto/tegra-nvvse-cryptodev.c @@ -1555,6 +1555,25 @@ out: return ret; } +static int tnvvse_crypto_get_ivc_db(struct tegra_nvvse_get_ivc_db *get_ivc_db) +{ + struct crypto_dev_to_ivc_map *hv_vse_db; + int ret = 0; + int i; + + hv_vse_db = tegra_hv_vse_get_db(); + if (hv_vse_db == NULL) + return -ENOMEM; + + for (i = 0; i < MAX_NUMBER_MISC_DEVICES; i++) { + get_ivc_db->ivc_id[i] = hv_vse_db[i].ivc_id; + get_ivc_db->se_engine[i] = hv_vse_db[i].se_engine; + get_ivc_db->node_id[i] = hv_vse_db[i].node_id; + } + + return ret; +} + static int tnvvse_crypto_dev_open(struct inode *inode, struct file *filp) { struct tnvvse_crypto_ctx *ctx; @@ -1643,6 +1662,7 @@ static long tnvvse_crypto_dev_ioctl(struct file *filp, struct tegra_nvvse_aes_drng_ctl aes_drng_ctl; struct tegra_nvvse_aes_gmac_init_ctl aes_gmac_init_ctl; struct tegra_nvvse_aes_gmac_sign_verify_ctl aes_gmac_sign_verify_ctl; + struct tegra_nvvse_get_ivc_db get_ivc_db; int ret = 0; /* @@ -1799,6 +1819,21 @@ static long tnvvse_crypto_dev_ioctl(struct file *filp, ret = tnvvse_crypto_get_aes_drng(ctx, &aes_drng_ctl); break; + case NVVSE_IOCTL_CMDID_GET_IVC_DB: + ret = tnvvse_crypto_get_ivc_db(&get_ivc_db); + if (ret) { + pr_err("%s(): Failed to get ivc database get_ivc_db:%d\n", __func__, ret); + goto out; + } + + ret = copy_to_user((void __user *)arg, &get_ivc_db, sizeof(get_ivc_db)); + if (ret) { + pr_err("%s(): Failed to copy_to_user get_ivc_db:%d\n", __func__, ret); + goto out; + } + + break; + default: pr_err("%s(): invalid ioctl code(%d[0x%08x])", __func__, ioctl_num, ioctl_num); ret = -EINVAL; diff --git a/include/uapi/misc/tegra-nvvse-cryptodev.h b/include/uapi/misc/tegra-nvvse-cryptodev.h index 71f3c047..985259d0 100644 --- a/include/uapi/misc/tegra-nvvse-cryptodev.h +++ b/include/uapi/misc/tegra-nvvse-cryptodev.h @@ -10,6 +10,7 @@ #include #define TEGRA_NVVSE_IOC_MAGIC 0x98 +#define MAX_NUMBER_MISC_DEVICES 40U /* Command ID for various IO Control */ #define TEGRA_NVVSE_CMDID_AES_SET_KEY 1 @@ -22,6 +23,7 @@ #define TEGRA_NVVSE_CMDID_AES_GMAC_INIT 9 #define TEGRA_NVVSE_CMDID_AES_GMAC_SIGN_VERIFY 10 #define TEGRA_NVVSE_CMDID_AES_CMAC_SIGN_VERIFY 11 +#define TEGRA_NVVSE_CMDID_GET_IVC_DB 12 /** Defines the length of the AES-CBC Initial Vector */ #define TEGRA_NVVSE_AES_IV_LEN 16U @@ -352,6 +354,20 @@ struct tegra_nvvse_aes_cmac_sign_verify_ctl { TEGRA_NVVSE_CMDID_AES_CMAC_SIGN_VERIFY, \ struct tegra_nvvse_aes_cmac_sign_verify_ctl) +/** + * brief Holds IVC databse + */ +struct tegra_nvvse_get_ivc_db { + /** HoldsIVC Queue Id */ + uint32_t ivc_id[MAX_NUMBER_MISC_DEVICES]; + /** Holds SE Engine Type */ + uint32_t se_engine[MAX_NUMBER_MISC_DEVICES]; + /** Holds Crypto Dev Node Id */ + uint32_t node_id[MAX_NUMBER_MISC_DEVICES]; +}; +#define NVVSE_IOCTL_CMDID_GET_IVC_DB _IOW(TEGRA_NVVSE_IOC_MAGIC, TEGRA_NVVSE_CMDID_GET_IVC_DB, \ + struct tegra_nvvse_get_ivc_db) + /** * \brief Holds AES generated RNG IO control params */