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PCI: Add T264 PCIe DMA support in PCIe EPF and client driver
Replace the exisiting T234 DMA APIs with common APIs and also add chip specific changes like BAR. Bug 4549851 Change-Id: I021e1e93a4fa4ff1d4429bd9db852e0e707ba879 Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3116906 Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
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Manikanta Maddireddy
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@@ -9,62 +9,123 @@
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#define TEGRA_PCIE_EDMA_TEST_COMMON_H
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#include <linux/pci-epf.h>
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#include <linux/pcie_dma.h>
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#include <linux/tegra-pcie-edma.h>
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#include <linux/tegra-pcie-dma.h>
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#define DMA_WRITE_DOORBELL_OFF 0x10
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#define DMA_WRITE_DOORBELL_OFF_WR_STOP BIT(31)
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#define DMA_READ_DOORBELL_OFF 0x30
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static inline void dma_common_wr(void __iomem *p, u32 val, u32 offset)
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{
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writel(val, offset + p);
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}
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#define REMOTE_EDMA_TEST_EN (edma->edma_ch & 0x80000000)
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#define EDMA_ABORT_TEST_EN (edma->edma_ch & 0x40000000)
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#define EDMA_STOP_TEST_EN (edma->edma_ch & 0x20000000)
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#define EDMA_CRC_TEST_EN (edma->edma_ch & 0x10000000)
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#define EDMA_READ_TEST_EN (edma->edma_ch & 0x08000000)
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#define EDMA_SANITY_TEST_EN (edma->edma_ch & 0x04000000)
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#define EDMA_UNALIGN_SRC_TEST_EN (edma->edma_ch & 0x02000000)
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#define EDMA_UNALIGN_DST_TEST_EN (edma->edma_ch & 0x01000000)
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#define EDMA_UNALIGN_SRC_DST_TEST_EN (edma->edma_ch & 0x00800000)
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#define IS_EDMA_CH_ENABLED(i) (edma->edma_ch & ((BIT(i) << 4)))
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#define IS_EDMA_CH_ASYNC(i) (edma->edma_ch & BIT(i))
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#define REMOTE_EDMA_TEST_EN (edma->edma_ch & 0x80000000)
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#define EDMA_PERF (edma->tsz / (diff / 1000))
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#define EDMA_CPERF ((edma->tsz * (edma->nents / edma->nents_per_ch)) / (diff / 1000))
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#define NUM_EDMA_DESC 4096
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#define TEGRA234_PCIE_DMA_RD_CHNL_NUM 2
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#define EDMA_PRIV_CH_OFF 32
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#define EDMA_PRIV_LR_OFF (EDMA_PRIV_CH_OFF + 2)
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#define EDMA_PRIV_XF_OFF (EDMA_PRIV_LR_OFF + 1)
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/* Update DMA_DD_BUF_SIZE and DMA_LL_BUF_SIZE when changing BAR0_SIZE */
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#define BAR0_SIZE SZ_256M
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/* Header includes RP/EP DMA addresses, EP MSI, LL, etc. */
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#define BAR0_HEADER_OFFSET 0x0
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#define BAR0_HEADER_SIZE SZ_1M
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#define DMA_LL_DEFAULT_SIZE 8
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#define BAR0_MSI_OFFSET SZ_64K
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/* DMA'able memory range */
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#define BAR0_DMA_BUF_OFFSET SZ_1M
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#define BAR0_DMA_BUF_SIZE (BAR0_SIZE - SZ_1M)
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#define DEFAULT_STRESS_COUNT 10
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#define MAX_DMA_ELE_SIZE SZ_16M
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/* DMA base offset starts at 0x20000 from ATU_DMA base */
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#define DMA_OFFSET 0x20000
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struct sanity_data {
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u32 size;
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u32 src_offset;
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u32 dst_offset;
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u32 crc;
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};
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/* First 1MB of BAR0 is reserved for control data */
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struct pcie_epf_bar {
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/* RP system memory allocated for EP DMA operations */
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u64 rp_phy_addr;
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/* EP system memory allocated as BAR */
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u64 ep_phy_addr;
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/* MSI data for RP -> EP interrupts */
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u32 msi_data[TEGRA_PCIE_DMA_WR_CHNL_NUM + TEGRA_PCIE_DMA_RD_CHNL_NUM];
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struct sanity_data wr_data[TEGRA_PCIE_DMA_WR_CHNL_NUM];
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struct sanity_data rd_data[TEGRA_PCIE_DMA_RD_CHNL_NUM];
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};
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struct edmalib_common {
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struct device *fdev;
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struct device *cdev;
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void (*raise_irq)(void *p);
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void *priv;
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struct pcie_epf_bar0 *epf_bar0;
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struct pcie_epf_bar *epf_bar;
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void *src_virt;
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void __iomem *dma_base;
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void __iomem *dma_virt;
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u32 dma_size;
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dma_addr_t src_dma_addr;
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dma_addr_t dst_dma_addr;
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dma_addr_t bar0_phy;
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dma_addr_t bar_phy;
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u32 stress_count;
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void *cookie;
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struct device_node *of_node;
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wait_queue_head_t wr_wq[DMA_WR_CHNL_NUM];
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wait_queue_head_t rd_wq[DMA_RD_CHNL_NUM];
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wait_queue_head_t wr_wq[TEGRA_PCIE_DMA_WR_CHNL_NUM];
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unsigned long wr_busy;
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unsigned long rd_busy;
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ktime_t edma_start_time[DMA_WR_CHNL_NUM];
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ktime_t edma_start_time[TEGRA_PCIE_DMA_WR_CHNL_NUM];
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u64 tsz;
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u32 edma_ch;
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u32 prev_edma_ch;
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u32 nents;
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struct tegra_pcie_edma_desc *ll_desc;
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u64 priv_iter[DMA_WR_CHNL_NUM];
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struct pcie_tegra_edma_remote_info edma_remote;
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struct tegra_pcie_dma_desc *ll_desc;
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u64 priv_iter[TEGRA_PCIE_DMA_WR_CHNL_NUM];
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struct tegra_pcie_dma_remote_info remote;
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u32 nents_per_ch;
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u32 st_as_ch;
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u32 ls_as_ch;
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u64 msi_addr;
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u32 msi_data;
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u32 msi_irq;
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nvpcie_dma_soc_t chip_id;
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};
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static struct edmalib_common *l_edma;
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static void edma_final_complete(void *priv, edma_xfer_status_t status,
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struct tegra_pcie_edma_desc *desc)
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static void edma_final_complete(void *priv, tegra_pcie_dma_status_t status)
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{
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struct edmalib_common *edma = l_edma;
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u64 cb = *(u64 *)priv;
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u32 ch = (cb >> EDMA_PRIV_CH_OFF) & 0x3;
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edma_xfer_type_t xfer_type = (cb >> EDMA_PRIV_XF_OFF) & 0x1;
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tegra_pcie_dma_xfer_type_t xfer_type = (cb >> EDMA_PRIV_XF_OFF) & 0x1;
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char *xfer_str[2] = {"WR", "RD"};
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u32 l_r = (cb >> EDMA_PRIV_LR_OFF) & 0x1;
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char *l_r_str[2] = {"local", "remote"};
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@@ -72,9 +133,12 @@ static void edma_final_complete(void *priv, edma_xfer_status_t status,
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u64 cdiff = ktime_to_ns(ktime_get()) - ktime_to_ns(edma->edma_start_time[edma->st_as_ch]);
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cb = cb & 0xFFFFFFFF;
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if (EDMA_ABORT_TEST_EN && status == EDMA_XFER_SUCCESS)
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dma_common_wr(edma->dma_base, DMA_WRITE_DOORBELL_OFF_WR_STOP | (ch + 1),
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DMA_WRITE_DOORBELL_OFF);
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/* TODO support abort test case for T264 */
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if (edma->chip_id == NVPCIE_DMA_SOC_T234) {
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if (EDMA_ABORT_TEST_EN && status == TEGRA_PCIE_DMA_SUCCESS)
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dma_common_wr(edma->dma_virt, DMA_WRITE_DOORBELL_OFF_WR_STOP | (ch + 1),
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DMA_WRITE_DOORBELL_OFF);
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}
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dev_info(edma->fdev, "%s: %s-%s-Async complete for chan %d with status %d. Total desc %llu of Sz %d Bytes done in time %llu nsec. Perf is %llu Mbps\n",
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__func__, xfer_str[xfer_type], l_r_str[l_r], ch, status, edma->nents_per_ch*(cb+1),
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@@ -85,7 +149,7 @@ static void edma_final_complete(void *priv, edma_xfer_status_t status,
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__func__, EDMA_CPERF, cdiff);
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}
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static void edma_complete(void *priv, edma_xfer_status_t status, struct tegra_pcie_edma_desc *desc)
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static void edma_complete(void *priv, tegra_pcie_dma_status_t status)
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{
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struct edmalib_common *edma = l_edma;
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u64 cb = *(u64 *)priv;
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@@ -103,24 +167,26 @@ static void edma_complete(void *priv, edma_xfer_status_t status, struct tegra_pc
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/* debugfs to perform eDMA lib transfers and do CRC check */
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static int edmalib_common_test(struct edmalib_common *edma)
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{
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struct tegra_pcie_edma_desc *ll_desc = edma->ll_desc;
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struct tegra_pcie_dma_desc *ll_desc = edma->ll_desc;
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dma_addr_t src_dma_addr = edma->src_dma_addr;
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dma_addr_t dst_dma_addr = edma->dst_dma_addr;
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u32 nents = edma->nents, num_chans = 0, nents_per_ch = 0, nent_id = 0, chan_count;
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u32 i, j, k, max_size, db_off, num_descriptors;
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edma_xfer_status_t ret;
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struct tegra_pcie_edma_init_info info = {};
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struct tegra_pcie_edma_chans_info *chan_info;
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struct tegra_pcie_edma_xfer_info tx_info = {};
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u32 i, j, k, max_size, num_descriptors;
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u32 db_off;
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tegra_pcie_dma_status_t ret;
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struct tegra_pcie_dma_init_info info = {};
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struct tegra_pcie_dma_chans_info *chan_info;
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struct tegra_pcie_dma_xfer_info tx_info = {};
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u64 diff;
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edma_xfer_type_t xfer_type;
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tegra_pcie_dma_xfer_type_t xfer_type;
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char *xfer_str[2] = {"WR", "RD"};
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u32 l_r;
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char *l_r_str[2] = {"local", "remote"};
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struct pcie_epf_bar0 *epf_bar0 = edma->epf_bar0;
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struct pcie_epf_bar *epf_bar = edma->epf_bar;
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u32 crc;
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if (!edma->stress_count) {
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tegra_pcie_edma_deinit(edma->cookie);
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tegra_pcie_dma_deinit(&edma->cookie);
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edma->cookie = NULL;
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return 0;
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}
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@@ -133,52 +199,133 @@ static int edmalib_common_test(struct edmalib_common *edma)
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edma->edma_ch |= 0xF5;
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}
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/* FIXME This is causing crash for remote dma when BAR MMIO virt address is used. */
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#if 0
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epf_bar->wr_data[0].src_offset = 0;
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epf_bar->wr_data[0].dst_offset = 0;
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#endif
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if (EDMA_CRC_TEST_EN) {
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/* 4 channels in sync mode */
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edma->edma_ch = (EDMA_CRC_TEST_EN | 0xF0);
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edma->edma_ch = (0x10000000 | 0xF0);
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/* Single SZ_4K packet on each channel, so total SZ_16K of data */
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edma->stress_count = 1;
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edma->dma_size = SZ_4K;
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edma->nents = nents = 4;
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epf_bar0->wr_data[0].size = edma->dma_size * edma->nents;
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epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
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}
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if (EDMA_UNALIGN_SRC_TEST_EN) {
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/* 4 channels in sync mode */
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edma->edma_ch = (0x02000000 | 0x10000000 | 0x10);
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/* Single SZ_4K packet on each channel, so total SZ_16K of data */
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edma->stress_count = 1;
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edma->dma_size = SZ_4K;
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edma->nents = nents = 4;
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epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
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src_dma_addr += 11;
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epf_bar->wr_data[0].src_offset = 11;
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}
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if (EDMA_UNALIGN_DST_TEST_EN) {
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/* 4 channels in sync mode */
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edma->edma_ch = (0x01000000 | 0x10000000 | 0x10);
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/* Single SZ_4K packet on each channel, so total SZ_16K of data */
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edma->stress_count = 1;
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edma->dma_size = SZ_4K;
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edma->nents = nents = 4;
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epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
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dst_dma_addr += 7;
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epf_bar->wr_data[0].dst_offset = 7;
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}
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if (EDMA_UNALIGN_SRC_DST_TEST_EN) {
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/* 4 channels in sync mode */
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edma->edma_ch = (0x00800000 | 0x10000000 | 0x10);
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/* Single SZ_4K packet on each channel, so total SZ_16K of data */
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edma->stress_count = 1;
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edma->dma_size = SZ_4K;
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edma->nents = nents = 4;
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epf_bar->wr_data[0].size = edma->dma_size * edma->nents;
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src_dma_addr += 7;
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dst_dma_addr += 13;
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epf_bar->wr_data[0].src_offset = 7;
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epf_bar->wr_data[0].dst_offset = 13;
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}
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if (EDMA_SANITY_TEST_EN) {
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edma->dma_size = SZ_1K;
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edma->nents = nents = 128;
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edma->stress_count = 2;
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}
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if (edma->cookie && edma->prev_edma_ch != edma->edma_ch) {
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edma->st_as_ch = -1;
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dev_info(edma->fdev, "edma_ch changed from 0x%x != 0x%x, deinit\n",
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edma->prev_edma_ch, edma->edma_ch);
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tegra_pcie_edma_deinit(edma->cookie);
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edma->prev_edma_ch, edma->edma_ch);
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tegra_pcie_dma_deinit(&edma->cookie);
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edma->cookie = NULL;
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}
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info.np = edma->of_node;
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info.dev = edma->cdev;
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info.soc = edma->chip_id;
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if (REMOTE_EDMA_TEST_EN) {
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num_descriptors = 1024;
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info.rx[0].desc_phy_base = edma->bar0_phy + SZ_512K;
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info.rx[0].desc_iova = 0xf0000000 + SZ_512K;
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info.rx[1].desc_phy_base = edma->bar0_phy + SZ_512K + SZ_256K;
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info.rx[1].desc_iova = 0xf0000000 + SZ_512K + SZ_256K;
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info.edma_remote = &edma->edma_remote;
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chan_count = DMA_RD_CHNL_NUM;
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info.rx[0].desc_phy_base = edma->bar_phy + SZ_128K;
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info.rx[0].desc_iova = epf_bar->ep_phy_addr + SZ_128K;
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info.rx[1].desc_phy_base = edma->bar_phy + SZ_256K;
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info.rx[1].desc_iova = epf_bar->ep_phy_addr + SZ_128K;
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info.rx[2].desc_phy_base = edma->bar_phy + SZ_256K + SZ_128K;
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info.rx[2].desc_iova = epf_bar->ep_phy_addr + SZ_256K + SZ_128K;
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info.rx[3].desc_phy_base = edma->bar_phy + SZ_512K;
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info.rx[3].desc_iova = epf_bar->ep_phy_addr + SZ_512K;
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info.remote = &edma->remote;
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info.msi_irq = edma->msi_irq;
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info.msi_data = edma->msi_data;
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info.msi_addr = edma->msi_addr;
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if (edma->chip_id == NVPCIE_DMA_SOC_T234)
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chan_count = TEGRA234_PCIE_DMA_RD_CHNL_NUM;
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else
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chan_count = TEGRA_PCIE_DMA_RD_CHNL_NUM;
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chan_info = &info.rx[0];
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xfer_type = EDMA_XFER_READ;
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db_off = DMA_WRITE_DOORBELL_OFF;
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xfer_type = TEGRA_PCIE_DMA_READ;
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/* TODO support abort test case for T264 */
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if (edma->chip_id == NVPCIE_DMA_SOC_T234)
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db_off = DMA_WRITE_DOORBELL_OFF;
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l_r = 1;
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} else {
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chan_count = DMA_WR_CHNL_NUM;
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chan_count = TEGRA_PCIE_DMA_WR_CHNL_NUM;
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num_descriptors = 4096;
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chan_info = &info.tx[0];
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xfer_type = EDMA_XFER_WRITE;
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db_off = DMA_READ_DOORBELL_OFF;
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xfer_type = TEGRA_PCIE_DMA_WRITE;
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/* TODO support abort test case for T264 */
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if (edma->chip_id == NVPCIE_DMA_SOC_T234)
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db_off = DMA_READ_DOORBELL_OFF;
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l_r = 0;
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info.msi_irq = edma->msi_irq;
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info.msi_data = edma->msi_data;
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info.msi_addr = edma->msi_addr;
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}
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if (EDMA_READ_TEST_EN) {
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if (edma->chip_id == NVPCIE_DMA_SOC_T234)
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chan_count = TEGRA234_PCIE_DMA_RD_CHNL_NUM;
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else
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chan_count = TEGRA_PCIE_DMA_RD_CHNL_NUM;
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num_descriptors = 4096;
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chan_info = &info.rx[0];
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xfer_type = TEGRA_PCIE_DMA_READ;
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/* TODO support abort test case for T264 */
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if (edma->chip_id == NVPCIE_DMA_SOC_T234)
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db_off = DMA_READ_DOORBELL_OFF;
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l_r = 1;
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}
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for (i = 0; i < chan_count; i++) {
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struct tegra_pcie_edma_chans_info *ch = chan_info + i;
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struct tegra_pcie_dma_chans_info *ch = chan_info + i;
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ch->ch_type = IS_EDMA_CH_ASYNC(i) ? EDMA_CHAN_XFER_ASYNC :
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EDMA_CHAN_XFER_SYNC;
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ch->ch_type = IS_EDMA_CH_ASYNC(i) ? TEGRA_PCIE_DMA_CHAN_XFER_ASYNC :
|
||||
TEGRA_PCIE_DMA_CHAN_XFER_SYNC;
|
||||
if (IS_EDMA_CH_ENABLED(i)) {
|
||||
if (edma->st_as_ch == -1)
|
||||
edma->st_as_ch = i;
|
||||
@@ -200,15 +347,19 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
nents_per_ch = nents / num_chans;
|
||||
|
||||
if (nents_per_ch == 0) {
|
||||
dev_err(edma->fdev, "%s: nents(%d) < enabled chanes(%d)\n",
|
||||
dev_err(edma->fdev, "%s: nents(%d) < enabled channels(%d)\n",
|
||||
__func__, nents, num_chans);
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (j = 0; j < nents; j++) {
|
||||
ll_desc->src = src_dma_addr + (j * edma->dma_size);
|
||||
ll_desc->dst = dst_dma_addr + (j * edma->dma_size);
|
||||
dev_dbg(edma->fdev, "src %llx, dst %llx at %d\n", ll_desc->src, ll_desc->dst, j);
|
||||
if (EDMA_READ_TEST_EN) {
|
||||
ll_desc->dst = src_dma_addr + (j * edma->dma_size);
|
||||
ll_desc->src = dst_dma_addr + (j * edma->dma_size);
|
||||
} else {
|
||||
ll_desc->src = src_dma_addr + (j * edma->dma_size);
|
||||
ll_desc->dst = dst_dma_addr + (j * edma->dma_size);
|
||||
}
|
||||
ll_desc->sz = edma->dma_size;
|
||||
ll_desc++;
|
||||
}
|
||||
@@ -219,14 +370,33 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
if (!edma->cookie || (edma->prev_edma_ch != edma->edma_ch)) {
|
||||
dev_info(edma->fdev, "%s: re-init edma lib prev_ch(%x) != current chans(%x)\n",
|
||||
__func__, edma->prev_edma_ch, edma->edma_ch);
|
||||
edma->cookie = tegra_pcie_edma_initialize(&info);
|
||||
ret = tegra_pcie_dma_initialize(&info, &edma->cookie);
|
||||
if (ret != TEGRA_PCIE_DMA_SUCCESS) {
|
||||
dev_info(edma->fdev, "%s: tegra_pcie_dma_initialize() fail: %d\n",
|
||||
__func__, ret);
|
||||
return -1;
|
||||
}
|
||||
edma->prev_edma_ch = edma->edma_ch;
|
||||
|
||||
if (edma->chip_id == NVPCIE_DMA_SOC_T264) {
|
||||
ret = tegra_pcie_dma_set_msi(edma->cookie, edma->msi_addr, edma->msi_data);
|
||||
if (ret != TEGRA_PCIE_DMA_SUCCESS) {
|
||||
dev_info(edma->fdev, "%s: tegra_pcie_dma_set_msi() fail: %d\n",
|
||||
__func__, ret);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
edma->nents_per_ch = nents_per_ch;
|
||||
|
||||
/* generate random bytes to transfer */
|
||||
get_random_bytes(edma->src_virt, edma->dma_size * nents_per_ch);
|
||||
if (EDMA_SANITY_TEST_EN) {
|
||||
for (j = 0; j < num_descriptors; j++)
|
||||
memset((u8 *)edma->src_virt + (j * SZ_1K), j, SZ_1K);
|
||||
} else {
|
||||
get_random_bytes(edma->src_virt, edma->dma_size * nents_per_ch);
|
||||
}
|
||||
dev_info(edma->fdev, "%s: EDMA LIB %s started for %d chans, size %d Bytes, iterations: %d of descriptors %d\n",
|
||||
__func__, xfer_str[xfer_type], num_chans, edma->dma_size, edma->stress_count,
|
||||
nents_per_ch);
|
||||
@@ -234,7 +404,7 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
/* LL DMA with size epfnv->dma_size per desc */
|
||||
for (i = 0; i < chan_count; i++) {
|
||||
int ch = i;
|
||||
struct tegra_pcie_edma_chans_info *ch_info = chan_info + i;
|
||||
struct tegra_pcie_dma_chans_info *ch_info = chan_info + i;
|
||||
|
||||
if (ch_info->num_descriptors == 0)
|
||||
continue;
|
||||
@@ -245,20 +415,20 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
tx_info.channel_num = ch;
|
||||
tx_info.type = xfer_type;
|
||||
tx_info.nents = nents_per_ch;
|
||||
if (ch_info->ch_type == EDMA_CHAN_XFER_ASYNC) {
|
||||
if (ch_info->ch_type == TEGRA_PCIE_DMA_CHAN_XFER_ASYNC) {
|
||||
if (k == edma->stress_count - 1)
|
||||
tx_info.complete = edma_final_complete;
|
||||
else
|
||||
tx_info.complete = edma_complete;
|
||||
}
|
||||
edma->priv_iter[ch] = k | (((u64)xfer_type) << EDMA_PRIV_XF_OFF) |
|
||||
(((u64)l_r) << EDMA_PRIV_LR_OFF) |
|
||||
(((u64)ch) << EDMA_PRIV_CH_OFF);
|
||||
(((u64)l_r) << EDMA_PRIV_LR_OFF) |
|
||||
(((u64)ch) << EDMA_PRIV_CH_OFF);
|
||||
tx_info.priv = &edma->priv_iter[ch];
|
||||
ret = tegra_pcie_edma_submit_xfer(edma->cookie, &tx_info);
|
||||
if (ret == EDMA_XFER_FAIL_NOMEM) {
|
||||
ret = tegra_pcie_dma_submit_xfer(edma->cookie, &tx_info);
|
||||
if (ret == TEGRA_PCIE_DMA_FAIL_NOMEM) {
|
||||
/** Retry after 20 msec */
|
||||
dev_dbg(edma->fdev, "%s: EDMA_XFER_FAIL_NOMEM stress count %d on channel %d iter %d\n",
|
||||
dev_dbg(edma->fdev, "%s: TEGRA_PCIE_DMA_FAIL_NOMEM stress count %d on channel %d iter %d\n",
|
||||
__func__, edma->stress_count, i, k);
|
||||
ret = wait_event_timeout(edma->wr_wq[i],
|
||||
!(edma->wr_busy & (1 << i)),
|
||||
@@ -272,7 +442,8 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
}
|
||||
k--;
|
||||
continue;
|
||||
} else if ((ret != EDMA_XFER_SUCCESS) && (ret != EDMA_XFER_FAIL_NOMEM)) {
|
||||
} else if ((ret != TEGRA_PCIE_DMA_SUCCESS) &&
|
||||
(ret != TEGRA_PCIE_DMA_FAIL_NOMEM)) {
|
||||
dev_err(edma->fdev, "%s: LL %d, SZ: %u B CH: %d failed. %d at iter %d ret: %d\n",
|
||||
__func__, xfer_type, edma->dma_size, ch, ret, k, ret);
|
||||
if (EDMA_STOP_TEST_EN) {
|
||||
@@ -289,44 +460,48 @@ static int edmalib_common_test(struct edmalib_common *edma)
|
||||
if (i == 0) {
|
||||
if (EDMA_ABORT_TEST_EN) {
|
||||
msleep(edma->stress_count);
|
||||
dma_common_wr(edma->dma_base, DMA_WRITE_DOORBELL_OFF_WR_STOP,
|
||||
db_off);
|
||||
/* TODO support abort test case for T264 */
|
||||
if (edma->chip_id == NVPCIE_DMA_SOC_T234)
|
||||
dma_common_wr(edma->dma_virt,
|
||||
DMA_WRITE_DOORBELL_OFF_WR_STOP, db_off);
|
||||
} else if (EDMA_STOP_TEST_EN) {
|
||||
bool stop_status;
|
||||
|
||||
msleep(edma->stress_count);
|
||||
stop_status = tegra_pcie_edma_stop(edma->cookie);
|
||||
stop_status = tegra_pcie_dma_stop(edma->cookie);
|
||||
dev_info(edma->fdev, "%s: EDMA LIB, status of stop DMA is %d",
|
||||
__func__, stop_status);
|
||||
}
|
||||
}
|
||||
diff = ktime_to_ns(ktime_get()) - ktime_to_ns(edma->edma_start_time[i]);
|
||||
if (ch_info->ch_type == EDMA_CHAN_XFER_SYNC) {
|
||||
if (ret == EDMA_XFER_SUCCESS)
|
||||
if (ch_info->ch_type == TEGRA_PCIE_DMA_CHAN_XFER_SYNC) {
|
||||
if (ret == TEGRA_PCIE_DMA_SUCCESS)
|
||||
dev_info(edma->fdev, "%s: EDMA LIB %s-%s-SYNC done for %d iter on channel %d. Total Size %llu bytes, time %llu nsec. Perf is %llu Mbps\n",
|
||||
__func__, xfer_str[xfer_type], l_r_str[l_r], edma->stress_count, i,
|
||||
edma->tsz, diff, EDMA_PERF);
|
||||
__func__, xfer_str[xfer_type], l_r_str[l_r],
|
||||
edma->stress_count, i, edma->tsz, diff, EDMA_PERF);
|
||||
}
|
||||
}
|
||||
|
||||
if (EDMA_CRC_TEST_EN && !REMOTE_EDMA_TEST_EN) {
|
||||
u32 crc;
|
||||
|
||||
if (EDMA_SANITY_TEST_EN)
|
||||
edma->raise_irq(edma->priv);
|
||||
crc = crc32_le(~0, edma->src_virt, epf_bar0->wr_data[0].size);
|
||||
|
||||
if (EDMA_CRC_TEST_EN && !REMOTE_EDMA_TEST_EN) {
|
||||
edma->raise_irq(edma->priv);
|
||||
crc = crc32_le(~0, edma->src_virt + epf_bar->wr_data[0].src_offset,
|
||||
epf_bar->wr_data[0].size);
|
||||
msleep(100);
|
||||
if (crc != epf_bar0->wr_data[0].crc)
|
||||
if (crc != epf_bar->wr_data[0].crc)
|
||||
dev_err(edma->fdev, "CRC check failed, LCRC: 0x%x RCRC: 0x%x\n",
|
||||
crc, epf_bar0->wr_data[0].crc);
|
||||
crc, epf_bar->wr_data[0].crc);
|
||||
else
|
||||
dev_err(edma->fdev, "CRC check pass\n");
|
||||
}
|
||||
dev_info(edma->fdev, "%s: EDMA LIB submit done\n", __func__);
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
if (ret != EDMA_XFER_DEINIT) {
|
||||
tegra_pcie_edma_deinit(edma->cookie);
|
||||
if (ret != TEGRA_PCIE_DMA_DEINIT) {
|
||||
tegra_pcie_dma_deinit(&edma->cookie);
|
||||
edma->cookie = NULL;
|
||||
}
|
||||
return -1;
|
||||
|
||||
Reference in New Issue
Block a user