diff --git a/include/drivers-private/pinctrl/core.h b/include/drivers-private/pinctrl/core.h deleted file mode 100644 index 840103c4..00000000 --- a/include/drivers-private/pinctrl/core.h +++ /dev/null @@ -1,249 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Core private header for the pin control subsystem - * - * Copyright (C) 2011 ST-Ericsson SA - * Written on behalf of Linaro for ST-Ericsson - * - * Author: Linus Walleij - */ - -#include -#include -#include -#include -#include - -struct pinctrl_gpio_range; - -/** - * struct pinctrl_dev - pin control class device - * @node: node to include this pin controller in the global pin controller list - * @desc: the pin controller descriptor supplied when initializing this pin - * controller - * @pin_desc_tree: each pin descriptor for this pin controller is stored in - * this radix tree - * @pin_group_tree: optionally each pin group can be stored in this radix tree - * @num_groups: optionally number of groups can be kept here - * @pin_function_tree: optionally each function can be stored in this radix tree - * @num_functions: optionally number of functions can be kept here - * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller, - * ranges are added to this list at runtime - * @dev: the device entry for this pin controller - * @owner: module providing the pin controller, used for refcounting - * @driver_data: driver data for drivers registering to the pin controller - * subsystem - * @p: result of pinctrl_get() for this device - * @hog_default: default state for pins hogged by this device - * @hog_sleep: sleep state for pins hogged by this device - * @mutex: mutex taken on each pin controller specific action - * @device_root: debugfs root for this device - */ -struct pinctrl_dev { - struct list_head node; - struct pinctrl_desc *desc; - struct radix_tree_root pin_desc_tree; -#ifdef CONFIG_GENERIC_PINCTRL_GROUPS - struct radix_tree_root pin_group_tree; - unsigned int num_groups; -#endif -#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS - struct radix_tree_root pin_function_tree; - unsigned int num_functions; -#endif - struct list_head gpio_ranges; - struct device *dev; - struct module *owner; - void *driver_data; - struct pinctrl *p; - struct pinctrl_state *hog_default; - struct pinctrl_state *hog_sleep; - struct mutex mutex; -#ifdef CONFIG_DEBUG_FS - struct dentry *device_root; -#endif -}; - -/** - * struct pinctrl - per-device pin control state holder - * @node: global list node - * @dev: the device using this pin control handle - * @states: a list of states for this device - * @state: the current state - * @dt_maps: the mapping table chunks dynamically parsed from device tree for - * this device, if any - * @users: reference count - */ -struct pinctrl { - struct list_head node; - struct device *dev; - struct list_head states; - struct pinctrl_state *state; - struct list_head dt_maps; - struct kref users; -}; - -/** - * struct pinctrl_state - a pinctrl state for a device - * @node: list node for struct pinctrl's @states field - * @name: the name of this state - * @settings: a list of settings for this state - */ -struct pinctrl_state { - struct list_head node; - const char *name; - struct list_head settings; -}; - -/** - * struct pinctrl_setting_mux - setting data for MAP_TYPE_MUX_GROUP - * @group: the group selector to program - * @func: the function selector to program - */ -struct pinctrl_setting_mux { - unsigned group; - unsigned func; -}; - -/** - * struct pinctrl_setting_configs - setting data for MAP_TYPE_CONFIGS_* - * @group_or_pin: the group selector or pin ID to program - * @configs: a pointer to an array of config parameters/values to program into - * hardware. Each individual pin controller defines the format and meaning - * of config parameters. - * @num_configs: the number of entries in array @configs - */ -struct pinctrl_setting_configs { - unsigned group_or_pin; - unsigned long *configs; - unsigned num_configs; -}; - -/** - * struct pinctrl_setting - an individual mux or config setting - * @node: list node for struct pinctrl_settings's @settings field - * @type: the type of setting - * @pctldev: pin control device handling to be programmed. Not used for - * PIN_MAP_TYPE_DUMMY_STATE. - * @dev_name: the name of the device using this state - * @data: Data specific to the setting type - */ -struct pinctrl_setting { - struct list_head node; - enum pinctrl_map_type type; - struct pinctrl_dev *pctldev; - const char *dev_name; - union { - struct pinctrl_setting_mux mux; - struct pinctrl_setting_configs configs; - } data; -}; - -/** - * struct pin_desc - pin descriptor for each physical pin in the arch - * @pctldev: corresponding pin control device - * @name: a name for the pin, e.g. the name of the pin/pad/finger on a - * datasheet or such - * @dynamic_name: if the name of this pin was dynamically allocated - * @drv_data: driver-defined per-pin data. pinctrl core does not touch this - * @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL. - * If non-zero, this pin is claimed by @owner. This field is an integer - * rather than a boolean, since pinctrl_get() might process multiple - * mapping table entries that refer to, and hence claim, the same group - * or pin, and each of these will increment the @usecount. - * @mux_owner: The name of device that called pinctrl_get(). - * @mux_setting: The most recent selected mux setting for this pin, if any. - * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is - * the name of the GPIO that "owns" this pin. - */ -struct pin_desc { - struct pinctrl_dev *pctldev; - const char *name; - bool dynamic_name; - void *drv_data; - /* These fields only added when supporting pinmux drivers */ -#ifdef CONFIG_PINMUX - unsigned mux_usecount; - const char *mux_owner; - const struct pinctrl_setting_mux *mux_setting; - const char *gpio_owner; -#endif -}; - -/** - * struct pinctrl_maps - a list item containing part of the mapping table - * @node: mapping table list node - * @maps: array of mapping table entries - * @num_maps: the number of entries in @maps - */ -struct pinctrl_maps { - struct list_head node; - const struct pinctrl_map *maps; - unsigned num_maps; -}; - -#ifdef CONFIG_GENERIC_PINCTRL_GROUPS - -/** - * struct group_desc - generic pin group descriptor - * @name: name of the pin group - * @pins: array of pins that belong to the group - * @num_pins: number of pins in the group - * @data: pin controller driver specific data - */ -struct group_desc { - const char *name; - int *pins; - int num_pins; - void *data; -}; - -int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev); - -const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group_selector); - -int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group_selector, - const unsigned int **pins, - unsigned int *npins); - -struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev, - unsigned int group_selector); - -int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, - int *gpins, int ngpins, void *data); - -int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev, - unsigned int group_selector); - -#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */ - -struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); -struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np); -int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); -const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin); -int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, - const char *pin_group); - -static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, - unsigned int pin) -{ - return radix_tree_lookup(&pctldev->pin_desc_tree, pin); -} - -extern struct pinctrl_gpio_range * -pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev, - unsigned int pin); - -extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev); -extern int pinctrl_force_default(struct pinctrl_dev *pctldev); - -extern struct mutex pinctrl_maps_mutex; -extern struct list_head pinctrl_maps; - -#define for_each_maps(_maps_node_, _i_, _map_) \ - list_for_each_entry(_maps_node_, &pinctrl_maps, node) \ - for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \ - _i_ < _maps_node_->num_maps; \ - _i_++, _map_ = &_maps_node_->maps[_i_]) diff --git a/include/drivers-private/sound/soc/codecs/rt5640.h b/include/drivers-private/sound/soc/codecs/rt5640.h deleted file mode 100644 index 2c28f83e..00000000 --- a/include/drivers-private/sound/soc/codecs/rt5640.h +++ /dev/null @@ -1,2166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * rt5640.h -- RT5640 ALSA SoC audio driver - * - * Copyright 2011 Realtek Microelectronics - * Author: Johnny Hsu - */ - -#ifndef _RT5640_H -#define _RT5640_H - -#include -#include -#include -#include - -/* Info */ -#define RT5640_RESET 0x00 -#define RT5640_VENDOR_ID 0xfd -#define RT5640_VENDOR_ID1 0xfe -#define RT5640_VENDOR_ID2 0xff -/* I/O - Output */ -#define RT5640_SPK_VOL 0x01 -#define RT5640_HP_VOL 0x02 -#define RT5640_OUTPUT 0x03 -#define RT5640_MONO_OUT 0x04 -/* I/O - Input */ -#define RT5640_IN1_IN2 0x0d -#define RT5640_IN3_IN4 0x0e -#define RT5640_INL_INR_VOL 0x0f -/* I/O - ADC/DAC/DMIC */ -#define RT5640_DAC1_DIG_VOL 0x19 -#define RT5640_DAC2_DIG_VOL 0x1a -#define RT5640_DAC2_CTRL 0x1b -#define RT5640_ADC_DIG_VOL 0x1c -#define RT5640_ADC_DATA 0x1d -#define RT5640_ADC_BST_VOL 0x1e -/* Mixer - D-D */ -#define RT5640_STO_ADC_MIXER 0x27 -#define RT5640_MONO_ADC_MIXER 0x28 -#define RT5640_AD_DA_MIXER 0x29 -#define RT5640_STO_DAC_MIXER 0x2a -#define RT5640_MONO_DAC_MIXER 0x2b -#define RT5640_DIG_MIXER 0x2c -#define RT5640_DSP_PATH1 0x2d -#define RT5640_DSP_PATH2 0x2e -#define RT5640_DIG_INF_DATA 0x2f -/* Mixer - ADC */ -#define RT5640_REC_L1_MIXER 0x3b -#define RT5640_REC_L2_MIXER 0x3c -#define RT5640_REC_R1_MIXER 0x3d -#define RT5640_REC_R2_MIXER 0x3e -/* Mixer - DAC */ -#define RT5640_HPO_MIXER 0x45 -#define RT5640_SPK_L_MIXER 0x46 -#define RT5640_SPK_R_MIXER 0x47 -#define RT5640_SPO_L_MIXER 0x48 -#define RT5640_SPO_R_MIXER 0x49 -#define RT5640_SPO_CLSD_RATIO 0x4a -#define RT5640_MONO_MIXER 0x4c -#define RT5640_OUT_L1_MIXER 0x4d -#define RT5640_OUT_L2_MIXER 0x4e -#define RT5640_OUT_L3_MIXER 0x4f -#define RT5640_OUT_R1_MIXER 0x50 -#define RT5640_OUT_R2_MIXER 0x51 -#define RT5640_OUT_R3_MIXER 0x52 -#define RT5640_LOUT_MIXER 0x53 -/* Power */ -#define RT5640_PWR_DIG1 0x61 -#define RT5640_PWR_DIG2 0x62 -#define RT5640_PWR_ANLG1 0x63 -#define RT5640_PWR_ANLG2 0x64 -#define RT5640_PWR_MIXER 0x65 -#define RT5640_PWR_VOL 0x66 -/* Private Register Control */ -#define RT5640_PRIV_INDEX 0x6a -#define RT5640_PRIV_DATA 0x6c -/* Format - ADC/DAC */ -#define RT5640_I2S1_SDP 0x70 -#define RT5640_I2S2_SDP 0x71 -#define RT5640_ADDA_CLK1 0x73 -#define RT5640_ADDA_CLK2 0x74 -#define RT5640_DMIC 0x75 -/* Function - Analog */ -#define RT5640_GLB_CLK 0x80 -#define RT5640_PLL_CTRL1 0x81 -#define RT5640_PLL_CTRL2 0x82 -#define RT5640_ASRC_1 0x83 -#define RT5640_ASRC_2 0x84 -#define RT5640_ASRC_3 0x85 -#define RT5640_ASRC_4 0x89 -#define RT5640_ASRC_5 0x8a -#define RT5640_HP_OVCD 0x8b -#define RT5640_CLS_D_OVCD 0x8c -#define RT5640_CLS_D_OUT 0x8d -#define RT5640_DEPOP_M1 0x8e -#define RT5640_DEPOP_M2 0x8f -#define RT5640_DEPOP_M3 0x90 -#define RT5640_CHARGE_PUMP 0x91 -#define RT5640_PV_DET_SPK_G 0x92 -#define RT5640_MICBIAS 0x93 -/* Function - Digital */ -#define RT5640_EQ_CTRL1 0xb0 -#define RT5640_EQ_CTRL2 0xb1 -#define RT5640_WIND_FILTER 0xb2 -#define RT5640_DRC_AGC_1 0xb4 -#define RT5640_DRC_AGC_2 0xb5 -#define RT5640_DRC_AGC_3 0xb6 -#define RT5640_SVOL_ZC 0xb7 -#define RT5640_ANC_CTRL1 0xb8 -#define RT5640_ANC_CTRL2 0xb9 -#define RT5640_ANC_CTRL3 0xba -#define RT5640_JD_CTRL 0xbb -#define RT5640_ANC_JD 0xbc -#define RT5640_IRQ_CTRL1 0xbd -#define RT5640_IRQ_CTRL2 0xbe -#define RT5640_INT_IRQ_ST 0xbf -#define RT5640_GPIO_CTRL1 0xc0 -#define RT5640_GPIO_CTRL2 0xc1 -#define RT5640_GPIO_CTRL3 0xc2 -#define RT5640_DSP_CTRL1 0xc4 -#define RT5640_DSP_CTRL2 0xc5 -#define RT5640_DSP_CTRL3 0xc6 -#define RT5640_DSP_CTRL4 0xc7 -#define RT5640_PGM_REG_ARR1 0xc8 -#define RT5640_PGM_REG_ARR2 0xc9 -#define RT5640_PGM_REG_ARR3 0xca -#define RT5640_PGM_REG_ARR4 0xcb -#define RT5640_PGM_REG_ARR5 0xcc -#define RT5640_SCB_FUNC 0xcd -#define RT5640_SCB_CTRL 0xce -#define RT5640_BASE_BACK 0xcf -#define RT5640_MP3_PLUS1 0xd0 -#define RT5640_MP3_PLUS2 0xd1 -#define RT5640_3D_HP 0xd2 -#define RT5640_ADJ_HPF 0xd3 -#define RT5640_HP_CALIB_AMP_DET 0xd6 -#define RT5640_HP_CALIB2 0xd7 -#define RT5640_SV_ZCD1 0xd9 -#define RT5640_SV_ZCD2 0xda -/* Dummy Register */ -#define RT5640_DUMMY1 0xfa -#define RT5640_DUMMY2 0xfb -#define RT5640_DUMMY3 0xfc - - -/* Index of Codec Private Register definition */ -#define RT5640_BIAS_CUR4 0x15 -#define RT5640_CHPUMP_INT_REG1 0x24 -#define RT5640_MAMP_INT_REG2 0x37 -#define RT5640_3D_SPK 0x63 -#define RT5640_WND_1 0x6c -#define RT5640_WND_2 0x6d -#define RT5640_WND_3 0x6e -#define RT5640_WND_4 0x6f -#define RT5640_WND_5 0x70 -#define RT5640_WND_8 0x73 -#define RT5640_DIP_SPK_INF 0x75 -#define RT5640_HP_DCC_INT1 0x77 -#define RT5640_EQ_BW_LOP 0xa0 -#define RT5640_EQ_GN_LOP 0xa1 -#define RT5640_EQ_FC_BP1 0xa2 -#define RT5640_EQ_BW_BP1 0xa3 -#define RT5640_EQ_GN_BP1 0xa4 -#define RT5640_EQ_FC_BP2 0xa5 -#define RT5640_EQ_BW_BP2 0xa6 -#define RT5640_EQ_GN_BP2 0xa7 -#define RT5640_EQ_FC_BP3 0xa8 -#define RT5640_EQ_BW_BP3 0xa9 -#define RT5640_EQ_GN_BP3 0xaa -#define RT5640_EQ_FC_BP4 0xab -#define RT5640_EQ_BW_BP4 0xac -#define RT5640_EQ_GN_BP4 0xad -#define RT5640_EQ_FC_HIP1 0xae -#define RT5640_EQ_GN_HIP1 0xaf -#define RT5640_EQ_FC_HIP2 0xb0 -#define RT5640_EQ_BW_HIP2 0xb1 -#define RT5640_EQ_GN_HIP2 0xb2 -#define RT5640_EQ_PRE_VOL 0xb3 -#define RT5640_EQ_PST_VOL 0xb4 - -/* global definition */ -#define RT5640_L_MUTE (0x1 << 15) -#define RT5640_L_MUTE_SFT 15 -#define RT5640_VOL_L_MUTE (0x1 << 14) -#define RT5640_VOL_L_SFT 14 -#define RT5640_R_MUTE (0x1 << 7) -#define RT5640_R_MUTE_SFT 7 -#define RT5640_VOL_R_MUTE (0x1 << 6) -#define RT5640_VOL_R_SFT 6 -#define RT5640_L_VOL_MASK (0x3f << 8) -#define RT5640_L_VOL_SFT 8 -#define RT5640_R_VOL_MASK (0x3f) -#define RT5640_R_VOL_SFT 0 - -/* SW Reset & Device ID (0x00) */ -#define RT5640_ID_MASK (0x3 << 1) -#define RT5640_ID_5639 (0x0 << 1) -#define RT5640_ID_5640 (0x2 << 1) -#define RT5640_ID_5642 (0x3 << 1) - - -/* IN1 and IN2 Control (0x0d) */ -/* IN3 and IN4 Control (0x0e) */ -#define RT5640_BST_SFT1 12 -#define RT5640_BST_SFT2 8 -#define RT5640_IN_DF1 (0x1 << 7) -#define RT5640_IN_SFT1 7 -#define RT5640_IN_DF2 (0x1 << 6) -#define RT5640_IN_SFT2 6 - -/* INL and INR Volume Control (0x0f) */ -#define RT5640_INL_SEL_MASK (0x1 << 15) -#define RT5640_INL_SEL_SFT 15 -#define RT5640_INL_SEL_IN4P (0x0 << 15) -#define RT5640_INL_SEL_MONOP (0x1 << 15) -#define RT5640_INL_VOL_MASK (0x1f << 8) -#define RT5640_INL_VOL_SFT 8 -#define RT5640_INR_SEL_MASK (0x1 << 7) -#define RT5640_INR_SEL_SFT 7 -#define RT5640_INR_SEL_IN4N (0x0 << 7) -#define RT5640_INR_SEL_MONON (0x1 << 7) -#define RT5640_INR_VOL_MASK (0x1f) -#define RT5640_INR_VOL_SFT 0 - -/* DAC1 Digital Volume (0x19) */ -#define RT5640_DAC_L1_VOL_MASK (0xff << 8) -#define RT5640_DAC_L1_VOL_SFT 8 -#define RT5640_DAC_R1_VOL_MASK (0xff) -#define RT5640_DAC_R1_VOL_SFT 0 - -/* DAC2 Digital Volume (0x1a) */ -#define RT5640_DAC_L2_VOL_MASK (0xff << 8) -#define RT5640_DAC_L2_VOL_SFT 8 -#define RT5640_DAC_R2_VOL_MASK (0xff) -#define RT5640_DAC_R2_VOL_SFT 0 - -/* DAC2 Control (0x1b) */ -#define RT5640_M_DAC_L2_VOL (0x1 << 13) -#define RT5640_M_DAC_L2_VOL_SFT 13 -#define RT5640_M_DAC_R2_VOL (0x1 << 12) -#define RT5640_M_DAC_R2_VOL_SFT 12 - -/* ADC Digital Volume Control (0x1c) */ -#define RT5640_ADC_L_VOL_MASK (0x7f << 8) -#define RT5640_ADC_L_VOL_SFT 8 -#define RT5640_ADC_R_VOL_MASK (0x7f) -#define RT5640_ADC_R_VOL_SFT 0 - -/* Mono ADC Digital Volume Control (0x1d) */ -#define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8) -#define RT5640_MONO_ADC_L_VOL_SFT 8 -#define RT5640_MONO_ADC_R_VOL_MASK (0x7f) -#define RT5640_MONO_ADC_R_VOL_SFT 0 - -/* ADC Boost Volume Control (0x1e) */ -#define RT5640_ADC_L_BST_MASK (0x3 << 14) -#define RT5640_ADC_L_BST_SFT 14 -#define RT5640_ADC_R_BST_MASK (0x3 << 12) -#define RT5640_ADC_R_BST_SFT 12 -#define RT5640_ADC_COMP_MASK (0x3 << 10) -#define RT5640_ADC_COMP_SFT 10 - -/* Stereo ADC Mixer Control (0x27) */ -#define RT5640_M_ADC_L1 (0x1 << 14) -#define RT5640_M_ADC_L1_SFT 14 -#define RT5640_M_ADC_L2 (0x1 << 13) -#define RT5640_M_ADC_L2_SFT 13 -#define RT5640_ADC_1_SRC_MASK (0x1 << 12) -#define RT5640_ADC_1_SRC_SFT 12 -#define RT5640_ADC_1_SRC_ADC (0x1 << 12) -#define RT5640_ADC_1_SRC_DACMIX (0x0 << 12) -#define RT5640_ADC_2_SRC_MASK (0x3 << 10) -#define RT5640_ADC_2_SRC_SFT 10 -#define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10) -#define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10) -#define RT5640_ADC_2_SRC_DACMIX (0x2 << 10) -#define RT5640_M_ADC_R1 (0x1 << 6) -#define RT5640_M_ADC_R1_SFT 6 -#define RT5640_M_ADC_R2 (0x1 << 5) -#define RT5640_M_ADC_R2_SFT 5 - -/* Mono ADC Mixer Control (0x28) */ -#define RT5640_M_MONO_ADC_L1 (0x1 << 14) -#define RT5640_M_MONO_ADC_L1_SFT 14 -#define RT5640_M_MONO_ADC_L2 (0x1 << 13) -#define RT5640_M_MONO_ADC_L2_SFT 13 -#define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12) -#define RT5640_MONO_ADC_L1_SRC_SFT 12 -#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) -#define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12) -#define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10) -#define RT5640_MONO_ADC_L2_SRC_SFT 10 -#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10) -#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10) -#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10) -#define RT5640_M_MONO_ADC_R1 (0x1 << 6) -#define RT5640_M_MONO_ADC_R1_SFT 6 -#define RT5640_M_MONO_ADC_R2 (0x1 << 5) -#define RT5640_M_MONO_ADC_R2_SFT 5 -#define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4) -#define RT5640_MONO_ADC_R1_SRC_SFT 4 -#define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4) -#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) -#define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2) -#define RT5640_MONO_ADC_R2_SRC_SFT 2 -#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2) -#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2) -#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2) - -/* ADC Mixer to DAC Mixer Control (0x29) */ -#define RT5640_M_ADCMIX_L (0x1 << 15) -#define RT5640_M_ADCMIX_L_SFT 15 -#define RT5640_M_IF1_DAC_L (0x1 << 14) -#define RT5640_M_IF1_DAC_L_SFT 14 -#define RT5640_M_ADCMIX_R (0x1 << 7) -#define RT5640_M_ADCMIX_R_SFT 7 -#define RT5640_M_IF1_DAC_R (0x1 << 6) -#define RT5640_M_IF1_DAC_R_SFT 6 - -/* Stereo DAC Mixer Control (0x2a) */ -#define RT5640_M_DAC_L1 (0x1 << 14) -#define RT5640_M_DAC_L1_SFT 14 -#define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13) -#define RT5640_DAC_L1_STO_L_VOL_SFT 13 -#define RT5640_M_DAC_L2 (0x1 << 12) -#define RT5640_M_DAC_L2_SFT 12 -#define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11) -#define RT5640_DAC_L2_STO_L_VOL_SFT 11 -#define RT5640_M_ANC_DAC_L (0x1 << 10) -#define RT5640_M_ANC_DAC_L_SFT 10 -#define RT5640_M_DAC_R1 (0x1 << 6) -#define RT5640_M_DAC_R1_SFT 6 -#define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5) -#define RT5640_DAC_R1_STO_R_VOL_SFT 5 -#define RT5640_M_DAC_R2 (0x1 << 4) -#define RT5640_M_DAC_R2_SFT 4 -#define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3) -#define RT5640_DAC_R2_STO_R_VOL_SFT 3 -#define RT5640_M_ANC_DAC_R (0x1 << 2) -#define RT5640_M_ANC_DAC_R_SFT 2 - -/* Mono DAC Mixer Control (0x2b) */ -#define RT5640_M_DAC_L1_MONO_L (0x1 << 14) -#define RT5640_M_DAC_L1_MONO_L_SFT 14 -#define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) -#define RT5640_DAC_L1_MONO_L_VOL_SFT 13 -#define RT5640_M_DAC_L2_MONO_L (0x1 << 12) -#define RT5640_M_DAC_L2_MONO_L_SFT 12 -#define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) -#define RT5640_DAC_L2_MONO_L_VOL_SFT 11 -#define RT5640_M_DAC_R2_MONO_L (0x1 << 10) -#define RT5640_M_DAC_R2_MONO_L_SFT 10 -#define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) -#define RT5640_DAC_R2_MONO_L_VOL_SFT 9 -#define RT5640_M_DAC_R1_MONO_R (0x1 << 6) -#define RT5640_M_DAC_R1_MONO_R_SFT 6 -#define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) -#define RT5640_DAC_R1_MONO_R_VOL_SFT 5 -#define RT5640_M_DAC_R2_MONO_R (0x1 << 4) -#define RT5640_M_DAC_R2_MONO_R_SFT 4 -#define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) -#define RT5640_DAC_R2_MONO_R_VOL_SFT 3 -#define RT5640_M_DAC_L2_MONO_R (0x1 << 2) -#define RT5640_M_DAC_L2_MONO_R_SFT 2 -#define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) -#define RT5640_DAC_L2_MONO_R_VOL_SFT 1 - -/* Digital Mixer Control (0x2c) */ -#define RT5640_M_STO_L_DAC_L (0x1 << 15) -#define RT5640_M_STO_L_DAC_L_SFT 15 -#define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14) -#define RT5640_STO_L_DAC_L_VOL_SFT 14 -#define RT5640_M_DAC_L2_DAC_L (0x1 << 13) -#define RT5640_M_DAC_L2_DAC_L_SFT 13 -#define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) -#define RT5640_DAC_L2_DAC_L_VOL_SFT 12 -#define RT5640_M_STO_R_DAC_R (0x1 << 11) -#define RT5640_M_STO_R_DAC_R_SFT 11 -#define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10) -#define RT5640_STO_R_DAC_R_VOL_SFT 10 -#define RT5640_M_DAC_R2_DAC_R (0x1 << 9) -#define RT5640_M_DAC_R2_DAC_R_SFT 9 -#define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) -#define RT5640_DAC_R2_DAC_R_VOL_SFT 8 - -/* DSP Path Control 1 (0x2d) */ -#define RT5640_RXDP_SRC_MASK (0x1 << 15) -#define RT5640_RXDP_SRC_SFT 15 -#define RT5640_RXDP_SRC_NOR (0x0 << 15) -#define RT5640_RXDP_SRC_DIV3 (0x1 << 15) -#define RT5640_TXDP_SRC_MASK (0x1 << 14) -#define RT5640_TXDP_SRC_SFT 14 -#define RT5640_TXDP_SRC_NOR (0x0 << 14) -#define RT5640_TXDP_SRC_DIV3 (0x1 << 14) - -/* DSP Path Control 2 (0x2e) */ -#define RT5640_DAC_L2_SEL_MASK (0x3 << 14) -#define RT5640_DAC_L2_SEL_SFT 14 -#define RT5640_DAC_L2_SEL_IF2 (0x0 << 14) -#define RT5640_DAC_L2_SEL_IF3 (0x1 << 14) -#define RT5640_DAC_L2_SEL_TXDC (0x2 << 14) -#define RT5640_DAC_L2_SEL_BASS (0x3 << 14) -#define RT5640_DAC_R2_SEL_MASK (0x3 << 12) -#define RT5640_DAC_R2_SEL_SFT 12 -#define RT5640_DAC_R2_SEL_IF2 (0x0 << 12) -#define RT5640_DAC_R2_SEL_IF3 (0x1 << 12) -#define RT5640_DAC_R2_SEL_TXDC (0x2 << 12) -#define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11) -#define RT5640_IF2_ADC_L_SEL_SFT 11 -#define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11) -#define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11) -#define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10) -#define RT5640_IF2_ADC_R_SEL_SFT 10 -#define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10) -#define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10) -#define RT5640_RXDC_SEL_MASK (0x3 << 8) -#define RT5640_RXDC_SEL_SFT 8 -#define RT5640_RXDC_SEL_NOR (0x0 << 8) -#define RT5640_RXDC_SEL_L2R (0x1 << 8) -#define RT5640_RXDC_SEL_R2L (0x2 << 8) -#define RT5640_RXDC_SEL_SWAP (0x3 << 8) -#define RT5640_RXDP_SEL_MASK (0x3 << 6) -#define RT5640_RXDP_SEL_SFT 6 -#define RT5640_RXDP_SEL_NOR (0x0 << 6) -#define RT5640_RXDP_SEL_L2R (0x1 << 6) -#define RT5640_RXDP_SEL_R2L (0x2 << 6) -#define RT5640_RXDP_SEL_SWAP (0x3 << 6) -#define RT5640_TXDC_SEL_MASK (0x3 << 4) -#define RT5640_TXDC_SEL_SFT 4 -#define RT5640_TXDC_SEL_NOR (0x0 << 4) -#define RT5640_TXDC_SEL_L2R (0x1 << 4) -#define RT5640_TXDC_SEL_R2L (0x2 << 4) -#define RT5640_TXDC_SEL_SWAP (0x3 << 4) -#define RT5640_TXDP_SEL_MASK (0x3 << 2) -#define RT5640_TXDP_SEL_SFT 2 -#define RT5640_TXDP_SEL_NOR (0x0 << 2) -#define RT5640_TXDP_SEL_L2R (0x1 << 2) -#define RT5640_TXDP_SEL_R2L (0x2 << 2) -#define RT5640_TRXDP_SEL_SWAP (0x3 << 2) - -/* Digital Interface Data Control (0x2f) */ -#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14) -#define RT5640_IF1_DAC_SEL_SFT 14 -#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14) -#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14) -#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14) -#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14) -#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12) -#define RT5640_IF1_ADC_SEL_SFT 12 -#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12) -#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12) -#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12) -#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12) -#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10) -#define RT5640_IF2_DAC_SEL_SFT 10 -#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10) -#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10) -#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10) -#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10) -#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8) -#define RT5640_IF2_ADC_SEL_SFT 8 -#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8) -#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8) -#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8) -#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8) -#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6) -#define RT5640_IF3_DAC_SEL_SFT 6 -#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6) -#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6) -#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6) -#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6) -#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4) -#define RT5640_IF3_ADC_SEL_SFT 4 -#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4) -#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4) -#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4) -#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4) - -/* REC Left Mixer Control 1 (0x3b) */ -#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13) -#define RT5640_G_HP_L_RM_L_SFT 13 -#define RT5640_G_IN_L_RM_L_MASK (0x7 << 10) -#define RT5640_G_IN_L_RM_L_SFT 10 -#define RT5640_G_BST4_RM_L_MASK (0x7 << 7) -#define RT5640_G_BST4_RM_L_SFT 7 -#define RT5640_G_BST3_RM_L_MASK (0x7 << 4) -#define RT5640_G_BST3_RM_L_SFT 4 -#define RT5640_G_BST2_RM_L_MASK (0x7 << 1) -#define RT5640_G_BST2_RM_L_SFT 1 - -/* REC Left Mixer Control 2 (0x3c) */ -#define RT5640_G_BST1_RM_L_MASK (0x7 << 13) -#define RT5640_G_BST1_RM_L_SFT 13 -#define RT5640_G_OM_L_RM_L_MASK (0x7 << 10) -#define RT5640_G_OM_L_RM_L_SFT 10 -#define RT5640_M_HP_L_RM_L (0x1 << 6) -#define RT5640_M_HP_L_RM_L_SFT 6 -#define RT5640_M_IN_L_RM_L (0x1 << 5) -#define RT5640_M_IN_L_RM_L_SFT 5 -#define RT5640_M_BST4_RM_L (0x1 << 4) -#define RT5640_M_BST4_RM_L_SFT 4 -#define RT5640_M_BST3_RM_L (0x1 << 3) -#define RT5640_M_BST3_RM_L_SFT 3 -#define RT5640_M_BST2_RM_L (0x1 << 2) -#define RT5640_M_BST2_RM_L_SFT 2 -#define RT5640_M_BST1_RM_L (0x1 << 1) -#define RT5640_M_BST1_RM_L_SFT 1 -#define RT5640_M_OM_L_RM_L (0x1) -#define RT5640_M_OM_L_RM_L_SFT 0 - -/* REC Right Mixer Control 1 (0x3d) */ -#define RT5640_G_HP_R_RM_R_MASK (0x7 << 13) -#define RT5640_G_HP_R_RM_R_SFT 13 -#define RT5640_G_IN_R_RM_R_MASK (0x7 << 10) -#define RT5640_G_IN_R_RM_R_SFT 10 -#define RT5640_G_BST4_RM_R_MASK (0x7 << 7) -#define RT5640_G_BST4_RM_R_SFT 7 -#define RT5640_G_BST3_RM_R_MASK (0x7 << 4) -#define RT5640_G_BST3_RM_R_SFT 4 -#define RT5640_G_BST2_RM_R_MASK (0x7 << 1) -#define RT5640_G_BST2_RM_R_SFT 1 - -/* REC Right Mixer Control 2 (0x3e) */ -#define RT5640_G_BST1_RM_R_MASK (0x7 << 13) -#define RT5640_G_BST1_RM_R_SFT 13 -#define RT5640_G_OM_R_RM_R_MASK (0x7 << 10) -#define RT5640_G_OM_R_RM_R_SFT 10 -#define RT5640_M_HP_R_RM_R (0x1 << 6) -#define RT5640_M_HP_R_RM_R_SFT 6 -#define RT5640_M_IN_R_RM_R (0x1 << 5) -#define RT5640_M_IN_R_RM_R_SFT 5 -#define RT5640_M_BST4_RM_R (0x1 << 4) -#define RT5640_M_BST4_RM_R_SFT 4 -#define RT5640_M_BST3_RM_R (0x1 << 3) -#define RT5640_M_BST3_RM_R_SFT 3 -#define RT5640_M_BST2_RM_R (0x1 << 2) -#define RT5640_M_BST2_RM_R_SFT 2 -#define RT5640_M_BST1_RM_R (0x1 << 1) -#define RT5640_M_BST1_RM_R_SFT 1 -#define RT5640_M_OM_R_RM_R (0x1) -#define RT5640_M_OM_R_RM_R_SFT 0 - -/* HPMIX Control (0x45) */ -#define RT5640_M_DAC2_HM (0x1 << 15) -#define RT5640_M_DAC2_HM_SFT 15 -#define RT5640_M_DAC1_HM (0x1 << 14) -#define RT5640_M_DAC1_HM_SFT 14 -#define RT5640_M_HPVOL_HM (0x1 << 13) -#define RT5640_M_HPVOL_HM_SFT 13 -#define RT5640_G_HPOMIX_MASK (0x1 << 12) -#define RT5640_G_HPOMIX_SFT 12 - -/* SPK Left Mixer Control (0x46) */ -#define RT5640_G_RM_L_SM_L_MASK (0x3 << 14) -#define RT5640_G_RM_L_SM_L_SFT 14 -#define RT5640_G_IN_L_SM_L_MASK (0x3 << 12) -#define RT5640_G_IN_L_SM_L_SFT 12 -#define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10) -#define RT5640_G_DAC_L1_SM_L_SFT 10 -#define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8) -#define RT5640_G_DAC_L2_SM_L_SFT 8 -#define RT5640_G_OM_L_SM_L_MASK (0x3 << 6) -#define RT5640_G_OM_L_SM_L_SFT 6 -#define RT5640_M_RM_L_SM_L (0x1 << 5) -#define RT5640_M_RM_L_SM_L_SFT 5 -#define RT5640_M_IN_L_SM_L (0x1 << 4) -#define RT5640_M_IN_L_SM_L_SFT 4 -#define RT5640_M_DAC_L1_SM_L (0x1 << 3) -#define RT5640_M_DAC_L1_SM_L_SFT 3 -#define RT5640_M_DAC_L2_SM_L (0x1 << 2) -#define RT5640_M_DAC_L2_SM_L_SFT 2 -#define RT5640_M_OM_L_SM_L (0x1 << 1) -#define RT5640_M_OM_L_SM_L_SFT 1 - -/* SPK Right Mixer Control (0x47) */ -#define RT5640_G_RM_R_SM_R_MASK (0x3 << 14) -#define RT5640_G_RM_R_SM_R_SFT 14 -#define RT5640_G_IN_R_SM_R_MASK (0x3 << 12) -#define RT5640_G_IN_R_SM_R_SFT 12 -#define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10) -#define RT5640_G_DAC_R1_SM_R_SFT 10 -#define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8) -#define RT5640_G_DAC_R2_SM_R_SFT 8 -#define RT5640_G_OM_R_SM_R_MASK (0x3 << 6) -#define RT5640_G_OM_R_SM_R_SFT 6 -#define RT5640_M_RM_R_SM_R (0x1 << 5) -#define RT5640_M_RM_R_SM_R_SFT 5 -#define RT5640_M_IN_R_SM_R (0x1 << 4) -#define RT5640_M_IN_R_SM_R_SFT 4 -#define RT5640_M_DAC_R1_SM_R (0x1 << 3) -#define RT5640_M_DAC_R1_SM_R_SFT 3 -#define RT5640_M_DAC_R2_SM_R (0x1 << 2) -#define RT5640_M_DAC_R2_SM_R_SFT 2 -#define RT5640_M_OM_R_SM_R (0x1 << 1) -#define RT5640_M_OM_R_SM_R_SFT 1 - -/* SPOLMIX Control (0x48) */ -#define RT5640_M_DAC_R1_SPM_L (0x1 << 15) -#define RT5640_M_DAC_R1_SPM_L_SFT 15 -#define RT5640_M_DAC_L1_SPM_L (0x1 << 14) -#define RT5640_M_DAC_L1_SPM_L_SFT 14 -#define RT5640_M_SV_R_SPM_L (0x1 << 13) -#define RT5640_M_SV_R_SPM_L_SFT 13 -#define RT5640_M_SV_L_SPM_L (0x1 << 12) -#define RT5640_M_SV_L_SPM_L_SFT 12 -#define RT5640_M_BST1_SPM_L (0x1 << 11) -#define RT5640_M_BST1_SPM_L_SFT 11 - -/* SPORMIX Control (0x49) */ -#define RT5640_M_DAC_R1_SPM_R (0x1 << 13) -#define RT5640_M_DAC_R1_SPM_R_SFT 13 -#define RT5640_M_SV_R_SPM_R (0x1 << 12) -#define RT5640_M_SV_R_SPM_R_SFT 12 -#define RT5640_M_BST1_SPM_R (0x1 << 11) -#define RT5640_M_BST1_SPM_R_SFT 11 - -/* SPOLMIX / SPORMIX Ratio Control (0x4a) */ -#define RT5640_SPO_CLSD_RATIO_MASK (0x7) -#define RT5640_SPO_CLSD_RATIO_SFT 0 - -/* Mono Output Mixer Control (0x4c) */ -#define RT5640_M_DAC_R2_MM (0x1 << 15) -#define RT5640_M_DAC_R2_MM_SFT 15 -#define RT5640_M_DAC_L2_MM (0x1 << 14) -#define RT5640_M_DAC_L2_MM_SFT 14 -#define RT5640_M_OV_R_MM (0x1 << 13) -#define RT5640_M_OV_R_MM_SFT 13 -#define RT5640_M_OV_L_MM (0x1 << 12) -#define RT5640_M_OV_L_MM_SFT 12 -#define RT5640_M_BST1_MM (0x1 << 11) -#define RT5640_M_BST1_MM_SFT 11 -#define RT5640_G_MONOMIX_MASK (0x1 << 10) -#define RT5640_G_MONOMIX_SFT 10 - -/* Output Left Mixer Control 1 (0x4d) */ -#define RT5640_G_BST3_OM_L_MASK (0x7 << 13) -#define RT5640_G_BST3_OM_L_SFT 13 -#define RT5640_G_BST2_OM_L_MASK (0x7 << 10) -#define RT5640_G_BST2_OM_L_SFT 10 -#define RT5640_G_BST1_OM_L_MASK (0x7 << 7) -#define RT5640_G_BST1_OM_L_SFT 7 -#define RT5640_G_IN_L_OM_L_MASK (0x7 << 4) -#define RT5640_G_IN_L_OM_L_SFT 4 -#define RT5640_G_RM_L_OM_L_MASK (0x7 << 1) -#define RT5640_G_RM_L_OM_L_SFT 1 - -/* Output Left Mixer Control 2 (0x4e) */ -#define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13) -#define RT5640_G_DAC_R2_OM_L_SFT 13 -#define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10) -#define RT5640_G_DAC_L2_OM_L_SFT 10 -#define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7) -#define RT5640_G_DAC_L1_OM_L_SFT 7 - -/* Output Left Mixer Control 3 (0x4f) */ -#define RT5640_M_SM_L_OM_L (0x1 << 8) -#define RT5640_M_SM_L_OM_L_SFT 8 -#define RT5640_M_BST3_OM_L (0x1 << 7) -#define RT5640_M_BST3_OM_L_SFT 7 -#define RT5640_M_BST2_OM_L (0x1 << 6) -#define RT5640_M_BST2_OM_L_SFT 6 -#define RT5640_M_BST1_OM_L (0x1 << 5) -#define RT5640_M_BST1_OM_L_SFT 5 -#define RT5640_M_IN_L_OM_L (0x1 << 4) -#define RT5640_M_IN_L_OM_L_SFT 4 -#define RT5640_M_RM_L_OM_L (0x1 << 3) -#define RT5640_M_RM_L_OM_L_SFT 3 -#define RT5640_M_DAC_R2_OM_L (0x1 << 2) -#define RT5640_M_DAC_R2_OM_L_SFT 2 -#define RT5640_M_DAC_L2_OM_L (0x1 << 1) -#define RT5640_M_DAC_L2_OM_L_SFT 1 -#define RT5640_M_DAC_L1_OM_L (0x1) -#define RT5640_M_DAC_L1_OM_L_SFT 0 - -/* Output Right Mixer Control 1 (0x50) */ -#define RT5640_G_BST4_OM_R_MASK (0x7 << 13) -#define RT5640_G_BST4_OM_R_SFT 13 -#define RT5640_G_BST2_OM_R_MASK (0x7 << 10) -#define RT5640_G_BST2_OM_R_SFT 10 -#define RT5640_G_BST1_OM_R_MASK (0x7 << 7) -#define RT5640_G_BST1_OM_R_SFT 7 -#define RT5640_G_IN_R_OM_R_MASK (0x7 << 4) -#define RT5640_G_IN_R_OM_R_SFT 4 -#define RT5640_G_RM_R_OM_R_MASK (0x7 << 1) -#define RT5640_G_RM_R_OM_R_SFT 1 - -/* Output Right Mixer Control 2 (0x51) */ -#define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13) -#define RT5640_G_DAC_L2_OM_R_SFT 13 -#define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10) -#define RT5640_G_DAC_R2_OM_R_SFT 10 -#define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7) -#define RT5640_G_DAC_R1_OM_R_SFT 7 - -/* Output Right Mixer Control 3 (0x52) */ -#define RT5640_M_SM_L_OM_R (0x1 << 8) -#define RT5640_M_SM_L_OM_R_SFT 8 -#define RT5640_M_BST4_OM_R (0x1 << 7) -#define RT5640_M_BST4_OM_R_SFT 7 -#define RT5640_M_BST2_OM_R (0x1 << 6) -#define RT5640_M_BST2_OM_R_SFT 6 -#define RT5640_M_BST1_OM_R (0x1 << 5) -#define RT5640_M_BST1_OM_R_SFT 5 -#define RT5640_M_IN_R_OM_R (0x1 << 4) -#define RT5640_M_IN_R_OM_R_SFT 4 -#define RT5640_M_RM_R_OM_R (0x1 << 3) -#define RT5640_M_RM_R_OM_R_SFT 3 -#define RT5640_M_DAC_L2_OM_R (0x1 << 2) -#define RT5640_M_DAC_L2_OM_R_SFT 2 -#define RT5640_M_DAC_R2_OM_R (0x1 << 1) -#define RT5640_M_DAC_R2_OM_R_SFT 1 -#define RT5640_M_DAC_R1_OM_R (0x1) -#define RT5640_M_DAC_R1_OM_R_SFT 0 - -/* LOUT Mixer Control (0x53) */ -#define RT5640_M_DAC_L1_LM (0x1 << 15) -#define RT5640_M_DAC_L1_LM_SFT 15 -#define RT5640_M_DAC_R1_LM (0x1 << 14) -#define RT5640_M_DAC_R1_LM_SFT 14 -#define RT5640_M_OV_L_LM (0x1 << 13) -#define RT5640_M_OV_L_LM_SFT 13 -#define RT5640_M_OV_R_LM (0x1 << 12) -#define RT5640_M_OV_R_LM_SFT 12 -#define RT5640_G_LOUTMIX_MASK (0x1 << 11) -#define RT5640_G_LOUTMIX_SFT 11 - -/* Power Management for Digital 1 (0x61) */ -#define RT5640_PWR_I2S1 (0x1 << 15) -#define RT5640_PWR_I2S1_BIT 15 -#define RT5640_PWR_I2S2 (0x1 << 14) -#define RT5640_PWR_I2S2_BIT 14 -#define RT5640_PWR_DAC_L1 (0x1 << 12) -#define RT5640_PWR_DAC_L1_BIT 12 -#define RT5640_PWR_DAC_R1 (0x1 << 11) -#define RT5640_PWR_DAC_R1_BIT 11 -#define RT5640_PWR_DAC_L2 (0x1 << 7) -#define RT5640_PWR_DAC_L2_BIT 7 -#define RT5640_PWR_DAC_R2 (0x1 << 6) -#define RT5640_PWR_DAC_R2_BIT 6 -#define RT5640_PWR_ADC_L (0x1 << 2) -#define RT5640_PWR_ADC_L_BIT 2 -#define RT5640_PWR_ADC_R (0x1 << 1) -#define RT5640_PWR_ADC_R_BIT 1 -#define RT5640_PWR_CLS_D (0x1) -#define RT5640_PWR_CLS_D_BIT 0 - -/* Power Management for Digital 2 (0x62) */ -#define RT5640_PWR_ADC_SF (0x1 << 15) -#define RT5640_PWR_ADC_SF_BIT 15 -#define RT5640_PWR_ADC_MF_L (0x1 << 14) -#define RT5640_PWR_ADC_MF_L_BIT 14 -#define RT5640_PWR_ADC_MF_R (0x1 << 13) -#define RT5640_PWR_ADC_MF_R_BIT 13 -#define RT5640_PWR_I2S_DSP (0x1 << 12) -#define RT5640_PWR_I2S_DSP_BIT 12 - -/* Power Management for Analog 1 (0x63) */ -#define RT5640_PWR_VREF1 (0x1 << 15) -#define RT5640_PWR_VREF1_BIT 15 -#define RT5640_PWR_FV1 (0x1 << 14) -#define RT5640_PWR_FV1_BIT 14 -#define RT5640_PWR_MB (0x1 << 13) -#define RT5640_PWR_MB_BIT 13 -#define RT5640_PWR_LM (0x1 << 12) -#define RT5640_PWR_LM_BIT 12 -#define RT5640_PWR_BG (0x1 << 11) -#define RT5640_PWR_BG_BIT 11 -#define RT5640_PWR_MM (0x1 << 10) -#define RT5640_PWR_MM_BIT 10 -#define RT5640_PWR_MA (0x1 << 8) -#define RT5640_PWR_MA_BIT 8 -#define RT5640_PWR_HP_L (0x1 << 7) -#define RT5640_PWR_HP_L_BIT 7 -#define RT5640_PWR_HP_R (0x1 << 6) -#define RT5640_PWR_HP_R_BIT 6 -#define RT5640_PWR_HA (0x1 << 5) -#define RT5640_PWR_HA_BIT 5 -#define RT5640_PWR_VREF2 (0x1 << 4) -#define RT5640_PWR_VREF2_BIT 4 -#define RT5640_PWR_FV2 (0x1 << 3) -#define RT5640_PWR_FV2_BIT 3 -#define RT5640_PWR_LDO2 (0x1 << 2) -#define RT5640_PWR_LDO2_BIT 2 - -/* Power Management for Analog 2 (0x64) */ -#define RT5640_PWR_BST1 (0x1 << 15) -#define RT5640_PWR_BST1_BIT 15 -#define RT5640_PWR_BST2 (0x1 << 14) -#define RT5640_PWR_BST2_BIT 14 -#define RT5640_PWR_BST3 (0x1 << 13) -#define RT5640_PWR_BST3_BIT 13 -#define RT5640_PWR_BST4 (0x1 << 12) -#define RT5640_PWR_BST4_BIT 12 -#define RT5640_PWR_MB1 (0x1 << 11) -#define RT5640_PWR_MB1_BIT 11 -#define RT5640_PWR_PLL (0x1 << 9) -#define RT5640_PWR_PLL_BIT 9 - -/* Power Management for Mixer (0x65) */ -#define RT5640_PWR_OM_L (0x1 << 15) -#define RT5640_PWR_OM_L_BIT 15 -#define RT5640_PWR_OM_R (0x1 << 14) -#define RT5640_PWR_OM_R_BIT 14 -#define RT5640_PWR_SM_L (0x1 << 13) -#define RT5640_PWR_SM_L_BIT 13 -#define RT5640_PWR_SM_R (0x1 << 12) -#define RT5640_PWR_SM_R_BIT 12 -#define RT5640_PWR_RM_L (0x1 << 11) -#define RT5640_PWR_RM_L_BIT 11 -#define RT5640_PWR_RM_R (0x1 << 10) -#define RT5640_PWR_RM_R_BIT 10 - -/* Power Management for Volume (0x66) */ -#define RT5640_PWR_SV_L (0x1 << 15) -#define RT5640_PWR_SV_L_BIT 15 -#define RT5640_PWR_SV_R (0x1 << 14) -#define RT5640_PWR_SV_R_BIT 14 -#define RT5640_PWR_OV_L (0x1 << 13) -#define RT5640_PWR_OV_L_BIT 13 -#define RT5640_PWR_OV_R (0x1 << 12) -#define RT5640_PWR_OV_R_BIT 12 -#define RT5640_PWR_HV_L (0x1 << 11) -#define RT5640_PWR_HV_L_BIT 11 -#define RT5640_PWR_HV_R (0x1 << 10) -#define RT5640_PWR_HV_R_BIT 10 -#define RT5640_PWR_IN_L (0x1 << 9) -#define RT5640_PWR_IN_L_BIT 9 -#define RT5640_PWR_IN_R (0x1 << 8) -#define RT5640_PWR_IN_R_BIT 8 - -/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */ -#define RT5640_I2S_MS_MASK (0x1 << 15) -#define RT5640_I2S_MS_SFT 15 -#define RT5640_I2S_MS_M (0x0 << 15) -#define RT5640_I2S_MS_S (0x1 << 15) -#define RT5640_I2S_IF_MASK (0x7 << 12) -#define RT5640_I2S_IF_SFT 12 -#define RT5640_I2S_O_CP_MASK (0x3 << 10) -#define RT5640_I2S_O_CP_SFT 10 -#define RT5640_I2S_O_CP_OFF (0x0 << 10) -#define RT5640_I2S_O_CP_U_LAW (0x1 << 10) -#define RT5640_I2S_O_CP_A_LAW (0x2 << 10) -#define RT5640_I2S_I_CP_MASK (0x3 << 8) -#define RT5640_I2S_I_CP_SFT 8 -#define RT5640_I2S_I_CP_OFF (0x0 << 8) -#define RT5640_I2S_I_CP_U_LAW (0x1 << 8) -#define RT5640_I2S_I_CP_A_LAW (0x2 << 8) -#define RT5640_I2S_BP_MASK (0x1 << 7) -#define RT5640_I2S_BP_SFT 7 -#define RT5640_I2S_BP_NOR (0x0 << 7) -#define RT5640_I2S_BP_INV (0x1 << 7) -#define RT5640_I2S_DL_MASK (0x3 << 2) -#define RT5640_I2S_DL_SFT 2 -#define RT5640_I2S_DL_16 (0x0 << 2) -#define RT5640_I2S_DL_20 (0x1 << 2) -#define RT5640_I2S_DL_24 (0x2 << 2) -#define RT5640_I2S_DL_8 (0x3 << 2) -#define RT5640_I2S_DF_MASK (0x3) -#define RT5640_I2S_DF_SFT 0 -#define RT5640_I2S_DF_I2S (0x0) -#define RT5640_I2S_DF_LEFT (0x1) -#define RT5640_I2S_DF_PCM_A (0x2) -#define RT5640_I2S_DF_PCM_B (0x3) - -/* I2S2 Audio Serial Data Port Control (0x71) */ -#define RT5640_I2S2_SDI_MASK (0x1 << 6) -#define RT5640_I2S2_SDI_SFT 6 -#define RT5640_I2S2_SDI_I2S1 (0x0 << 6) -#define RT5640_I2S2_SDI_I2S2 (0x1 << 6) - -/* ADC/DAC Clock Control 1 (0x73) */ -#define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15) -#define RT5640_I2S_BCLK_MS1_SFT 15 -#define RT5640_I2S_BCLK_MS1_32 (0x0 << 15) -#define RT5640_I2S_BCLK_MS1_64 (0x1 << 15) -#define RT5640_I2S_PD1_MASK (0x7 << 12) -#define RT5640_I2S_PD1_SFT 12 -#define RT5640_I2S_PD1_1 (0x0 << 12) -#define RT5640_I2S_PD1_2 (0x1 << 12) -#define RT5640_I2S_PD1_3 (0x2 << 12) -#define RT5640_I2S_PD1_4 (0x3 << 12) -#define RT5640_I2S_PD1_6 (0x4 << 12) -#define RT5640_I2S_PD1_8 (0x5 << 12) -#define RT5640_I2S_PD1_12 (0x6 << 12) -#define RT5640_I2S_PD1_16 (0x7 << 12) -#define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11) -#define RT5640_I2S_BCLK_MS2_SFT 11 -#define RT5640_I2S_BCLK_MS2_32 (0x0 << 11) -#define RT5640_I2S_BCLK_MS2_64 (0x1 << 11) -#define RT5640_I2S_PD2_MASK (0x7 << 8) -#define RT5640_I2S_PD2_SFT 8 -#define RT5640_I2S_PD2_1 (0x0 << 8) -#define RT5640_I2S_PD2_2 (0x1 << 8) -#define RT5640_I2S_PD2_3 (0x2 << 8) -#define RT5640_I2S_PD2_4 (0x3 << 8) -#define RT5640_I2S_PD2_6 (0x4 << 8) -#define RT5640_I2S_PD2_8 (0x5 << 8) -#define RT5640_I2S_PD2_12 (0x6 << 8) -#define RT5640_I2S_PD2_16 (0x7 << 8) -#define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7) -#define RT5640_I2S_BCLK_MS3_SFT 7 -#define RT5640_I2S_BCLK_MS3_32 (0x0 << 7) -#define RT5640_I2S_BCLK_MS3_64 (0x1 << 7) -#define RT5640_I2S_PD3_MASK (0x7 << 4) -#define RT5640_I2S_PD3_SFT 4 -#define RT5640_I2S_PD3_1 (0x0 << 4) -#define RT5640_I2S_PD3_2 (0x1 << 4) -#define RT5640_I2S_PD3_3 (0x2 << 4) -#define RT5640_I2S_PD3_4 (0x3 << 4) -#define RT5640_I2S_PD3_6 (0x4 << 4) -#define RT5640_I2S_PD3_8 (0x5 << 4) -#define RT5640_I2S_PD3_12 (0x6 << 4) -#define RT5640_I2S_PD3_16 (0x7 << 4) -#define RT5640_DAC_OSR_MASK (0x3 << 2) -#define RT5640_DAC_OSR_SFT 2 -#define RT5640_DAC_OSR_128 (0x0 << 2) -#define RT5640_DAC_OSR_64 (0x1 << 2) -#define RT5640_DAC_OSR_32 (0x2 << 2) -#define RT5640_DAC_OSR_16 (0x3 << 2) -#define RT5640_ADC_OSR_MASK (0x3) -#define RT5640_ADC_OSR_SFT 0 -#define RT5640_ADC_OSR_128 (0x0) -#define RT5640_ADC_OSR_64 (0x1) -#define RT5640_ADC_OSR_32 (0x2) -#define RT5640_ADC_OSR_16 (0x3) - -/* ADC/DAC Clock Control 2 (0x74) */ -#define RT5640_DAC_L_OSR_MASK (0x3 << 14) -#define RT5640_DAC_L_OSR_SFT 14 -#define RT5640_DAC_L_OSR_128 (0x0 << 14) -#define RT5640_DAC_L_OSR_64 (0x1 << 14) -#define RT5640_DAC_L_OSR_32 (0x2 << 14) -#define RT5640_DAC_L_OSR_16 (0x3 << 14) -#define RT5640_ADC_R_OSR_MASK (0x3 << 12) -#define RT5640_ADC_R_OSR_SFT 12 -#define RT5640_ADC_R_OSR_128 (0x0 << 12) -#define RT5640_ADC_R_OSR_64 (0x1 << 12) -#define RT5640_ADC_R_OSR_32 (0x2 << 12) -#define RT5640_ADC_R_OSR_16 (0x3 << 12) -#define RT5640_DAHPF_EN (0x1 << 11) -#define RT5640_DAHPF_EN_SFT 11 -#define RT5640_ADHPF_EN (0x1 << 10) -#define RT5640_ADHPF_EN_SFT 10 - -/* Digital Microphone Control (0x75) */ -#define RT5640_DMIC_1_EN_MASK (0x1 << 15) -#define RT5640_DMIC_1_EN_SFT 15 -#define RT5640_DMIC_1_DIS (0x0 << 15) -#define RT5640_DMIC_1_EN (0x1 << 15) -#define RT5640_DMIC_2_EN_MASK (0x1 << 14) -#define RT5640_DMIC_2_EN_SFT 14 -#define RT5640_DMIC_2_DIS (0x0 << 14) -#define RT5640_DMIC_2_EN (0x1 << 14) -#define RT5640_DMIC_1L_LH_MASK (0x1 << 13) -#define RT5640_DMIC_1L_LH_SFT 13 -#define RT5640_DMIC_1L_LH_FALLING (0x0 << 13) -#define RT5640_DMIC_1L_LH_RISING (0x1 << 13) -#define RT5640_DMIC_1R_LH_MASK (0x1 << 12) -#define RT5640_DMIC_1R_LH_SFT 12 -#define RT5640_DMIC_1R_LH_FALLING (0x0 << 12) -#define RT5640_DMIC_1R_LH_RISING (0x1 << 12) -#define RT5640_DMIC_1_DP_MASK (0x1 << 11) -#define RT5640_DMIC_1_DP_SFT 11 -#define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11) -#define RT5640_DMIC_1_DP_IN1P (0x1 << 11) -#define RT5640_DMIC_2_DP_MASK (0x1 << 10) -#define RT5640_DMIC_2_DP_SFT 10 -#define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10) -#define RT5640_DMIC_2_DP_IN1N (0x1 << 10) -#define RT5640_DMIC_2L_LH_MASK (0x1 << 9) -#define RT5640_DMIC_2L_LH_SFT 9 -#define RT5640_DMIC_2L_LH_FALLING (0x0 << 9) -#define RT5640_DMIC_2L_LH_RISING (0x1 << 9) -#define RT5640_DMIC_2R_LH_MASK (0x1 << 8) -#define RT5640_DMIC_2R_LH_SFT 8 -#define RT5640_DMIC_2R_LH_FALLING (0x0 << 8) -#define RT5640_DMIC_2R_LH_RISING (0x1 << 8) -#define RT5640_DMIC_CLK_MASK (0x7 << 5) -#define RT5640_DMIC_CLK_SFT 5 - -/* Global Clock Control (0x80) */ -#define RT5640_SCLK_SRC_MASK (0x3 << 14) -#define RT5640_SCLK_SRC_SFT 14 -#define RT5640_SCLK_SRC_MCLK (0x0 << 14) -#define RT5640_SCLK_SRC_PLL1 (0x1 << 14) -#define RT5640_SCLK_SRC_RCCLK (0x2 << 14) -#define RT5640_PLL1_SRC_MASK (0x3 << 12) -#define RT5640_PLL1_SRC_SFT 12 -#define RT5640_PLL1_SRC_MCLK (0x0 << 12) -#define RT5640_PLL1_SRC_BCLK1 (0x1 << 12) -#define RT5640_PLL1_SRC_BCLK2 (0x2 << 12) -#define RT5640_PLL1_SRC_BCLK3 (0x3 << 12) -#define RT5640_PLL1_PD_MASK (0x1 << 3) -#define RT5640_PLL1_PD_SFT 3 -#define RT5640_PLL1_PD_1 (0x0 << 3) -#define RT5640_PLL1_PD_2 (0x1 << 3) - -#define RT5640_PLL_INP_MAX 40000000 -#define RT5640_PLL_INP_MIN 256000 -/* PLL M/N/K Code Control 1 (0x81) */ -#define RT5640_PLL_N_MAX 0x1ff -#define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7) -#define RT5640_PLL_N_SFT 7 -#define RT5640_PLL_K_MAX 0x1f -#define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX) -#define RT5640_PLL_K_SFT 0 - -/* PLL M/N/K Code Control 2 (0x82) */ -#define RT5640_PLL_M_MAX 0xf -#define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12) -#define RT5640_PLL_M_SFT 12 -#define RT5640_PLL_M_BP (0x1 << 11) -#define RT5640_PLL_M_BP_SFT 11 - -/* ASRC Control 1 (0x83) */ -#define RT5640_STO_T_MASK (0x1 << 15) -#define RT5640_STO_T_SFT 15 -#define RT5640_STO_T_SCLK (0x0 << 15) -#define RT5640_STO_T_LRCK1 (0x1 << 15) -#define RT5640_M1_T_MASK (0x1 << 14) -#define RT5640_M1_T_SFT 14 -#define RT5640_M1_T_I2S2 (0x0 << 14) -#define RT5640_M1_T_I2S2_D3 (0x1 << 14) -#define RT5640_I2S2_F_MASK (0x1 << 12) -#define RT5640_I2S2_F_SFT 12 -#define RT5640_I2S2_F_I2S2_D2 (0x0 << 12) -#define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12) -#define RT5640_DMIC_1_M_MASK (0x1 << 9) -#define RT5640_DMIC_1_M_SFT 9 -#define RT5640_DMIC_1_M_NOR (0x0 << 9) -#define RT5640_DMIC_1_M_ASYN (0x1 << 9) -#define RT5640_DMIC_2_M_MASK (0x1 << 8) -#define RT5640_DMIC_2_M_SFT 8 -#define RT5640_DMIC_2_M_NOR (0x0 << 8) -#define RT5640_DMIC_2_M_ASYN (0x1 << 8) - -/* ASRC clock source selection (0x84) */ -#define RT5640_CLK_SEL_SYS (0x0) -#define RT5640_CLK_SEL_ASRC (0x1) - -/* ASRC Control 2 (0x84) */ -#define RT5640_MDA_L_M_MASK (0x1 << 15) -#define RT5640_MDA_L_M_SFT 15 -#define RT5640_MDA_L_M_NOR (0x0 << 15) -#define RT5640_MDA_L_M_ASYN (0x1 << 15) -#define RT5640_MDA_R_M_MASK (0x1 << 14) -#define RT5640_MDA_R_M_SFT 14 -#define RT5640_MDA_R_M_NOR (0x0 << 14) -#define RT5640_MDA_R_M_ASYN (0x1 << 14) -#define RT5640_MAD_L_M_MASK (0x1 << 13) -#define RT5640_MAD_L_M_SFT 13 -#define RT5640_MAD_L_M_NOR (0x0 << 13) -#define RT5640_MAD_L_M_ASYN (0x1 << 13) -#define RT5640_MAD_R_M_MASK (0x1 << 12) -#define RT5640_MAD_R_M_SFT 12 -#define RT5640_MAD_R_M_NOR (0x0 << 12) -#define RT5640_MAD_R_M_ASYN (0x1 << 12) -#define RT5640_ADC_M_MASK (0x1 << 11) -#define RT5640_ADC_M_SFT 11 -#define RT5640_ADC_M_NOR (0x0 << 11) -#define RT5640_ADC_M_ASYN (0x1 << 11) -#define RT5640_STO_DAC_M_MASK (0x1 << 5) -#define RT5640_STO_DAC_M_SFT 5 -#define RT5640_STO_DAC_M_NOR (0x0 << 5) -#define RT5640_STO_DAC_M_ASYN (0x1 << 5) -#define RT5640_I2S1_R_D_MASK (0x1 << 4) -#define RT5640_I2S1_R_D_SFT 4 -#define RT5640_I2S1_R_D_DIS (0x0 << 4) -#define RT5640_I2S1_R_D_EN (0x1 << 4) -#define RT5640_I2S2_R_D_MASK (0x1 << 3) -#define RT5640_I2S2_R_D_SFT 3 -#define RT5640_I2S2_R_D_DIS (0x0 << 3) -#define RT5640_I2S2_R_D_EN (0x1 << 3) -#define RT5640_PRE_SCLK_MASK (0x3) -#define RT5640_PRE_SCLK_SFT 0 -#define RT5640_PRE_SCLK_512 (0x0) -#define RT5640_PRE_SCLK_1024 (0x1) -#define RT5640_PRE_SCLK_2048 (0x2) - -/* ASRC Control 3 (0x85) */ -#define RT5640_I2S1_RATE_MASK (0xf << 12) -#define RT5640_I2S1_RATE_SFT 12 -#define RT5640_I2S2_RATE_MASK (0xf << 8) -#define RT5640_I2S2_RATE_SFT 8 - -/* ASRC Control 4 (0x89) */ -#define RT5640_I2S1_PD_MASK (0x7 << 12) -#define RT5640_I2S1_PD_SFT 12 -#define RT5640_I2S2_PD_MASK (0x7 << 8) -#define RT5640_I2S2_PD_SFT 8 - -/* HPOUT Over Current Detection (0x8b) */ -#define RT5640_HP_OVCD_MASK (0x1 << 10) -#define RT5640_HP_OVCD_SFT 10 -#define RT5640_HP_OVCD_DIS (0x0 << 10) -#define RT5640_HP_OVCD_EN (0x1 << 10) -#define RT5640_HP_OC_TH_MASK (0x3 << 8) -#define RT5640_HP_OC_TH_SFT 8 -#define RT5640_HP_OC_TH_90 (0x0 << 8) -#define RT5640_HP_OC_TH_105 (0x1 << 8) -#define RT5640_HP_OC_TH_120 (0x2 << 8) -#define RT5640_HP_OC_TH_135 (0x3 << 8) - -/* Class D Over Current Control (0x8c) */ -#define RT5640_CLSD_OC_MASK (0x1 << 9) -#define RT5640_CLSD_OC_SFT 9 -#define RT5640_CLSD_OC_PU (0x0 << 9) -#define RT5640_CLSD_OC_PD (0x1 << 9) -#define RT5640_AUTO_PD_MASK (0x1 << 8) -#define RT5640_AUTO_PD_SFT 8 -#define RT5640_AUTO_PD_DIS (0x0 << 8) -#define RT5640_AUTO_PD_EN (0x1 << 8) -#define RT5640_CLSD_OC_TH_MASK (0x3f) -#define RT5640_CLSD_OC_TH_SFT 0 - -/* Class D Output Control (0x8d) */ -#define RT5640_CLSD_RATIO_MASK (0xf << 12) -#define RT5640_CLSD_RATIO_SFT 12 -#define RT5640_CLSD_OM_MASK (0x1 << 11) -#define RT5640_CLSD_OM_SFT 11 -#define RT5640_CLSD_OM_MONO (0x0 << 11) -#define RT5640_CLSD_OM_STO (0x1 << 11) -#define RT5640_CLSD_SCH_MASK (0x1 << 10) -#define RT5640_CLSD_SCH_SFT 10 -#define RT5640_CLSD_SCH_L (0x0 << 10) -#define RT5640_CLSD_SCH_S (0x1 << 10) - -/* Depop Mode Control 1 (0x8e) */ -#define RT5640_SMT_TRIG_MASK (0x1 << 15) -#define RT5640_SMT_TRIG_SFT 15 -#define RT5640_SMT_TRIG_DIS (0x0 << 15) -#define RT5640_SMT_TRIG_EN (0x1 << 15) -#define RT5640_HP_L_SMT_MASK (0x1 << 9) -#define RT5640_HP_L_SMT_SFT 9 -#define RT5640_HP_L_SMT_DIS (0x0 << 9) -#define RT5640_HP_L_SMT_EN (0x1 << 9) -#define RT5640_HP_R_SMT_MASK (0x1 << 8) -#define RT5640_HP_R_SMT_SFT 8 -#define RT5640_HP_R_SMT_DIS (0x0 << 8) -#define RT5640_HP_R_SMT_EN (0x1 << 8) -#define RT5640_HP_CD_PD_MASK (0x1 << 7) -#define RT5640_HP_CD_PD_SFT 7 -#define RT5640_HP_CD_PD_DIS (0x0 << 7) -#define RT5640_HP_CD_PD_EN (0x1 << 7) -#define RT5640_RSTN_MASK (0x1 << 6) -#define RT5640_RSTN_SFT 6 -#define RT5640_RSTN_DIS (0x0 << 6) -#define RT5640_RSTN_EN (0x1 << 6) -#define RT5640_RSTP_MASK (0x1 << 5) -#define RT5640_RSTP_SFT 5 -#define RT5640_RSTP_DIS (0x0 << 5) -#define RT5640_RSTP_EN (0x1 << 5) -#define RT5640_HP_CO_MASK (0x1 << 4) -#define RT5640_HP_CO_SFT 4 -#define RT5640_HP_CO_DIS (0x0 << 4) -#define RT5640_HP_CO_EN (0x1 << 4) -#define RT5640_HP_CP_MASK (0x1 << 3) -#define RT5640_HP_CP_SFT 3 -#define RT5640_HP_CP_PD (0x0 << 3) -#define RT5640_HP_CP_PU (0x1 << 3) -#define RT5640_HP_SG_MASK (0x1 << 2) -#define RT5640_HP_SG_SFT 2 -#define RT5640_HP_SG_DIS (0x0 << 2) -#define RT5640_HP_SG_EN (0x1 << 2) -#define RT5640_HP_DP_MASK (0x1 << 1) -#define RT5640_HP_DP_SFT 1 -#define RT5640_HP_DP_PD (0x0 << 1) -#define RT5640_HP_DP_PU (0x1 << 1) -#define RT5640_HP_CB_MASK (0x1) -#define RT5640_HP_CB_SFT 0 -#define RT5640_HP_CB_PD (0x0) -#define RT5640_HP_CB_PU (0x1) - -/* Depop Mode Control 2 (0x8f) */ -#define RT5640_DEPOP_MASK (0x1 << 13) -#define RT5640_DEPOP_SFT 13 -#define RT5640_DEPOP_AUTO (0x0 << 13) -#define RT5640_DEPOP_MAN (0x1 << 13) -#define RT5640_RAMP_MASK (0x1 << 12) -#define RT5640_RAMP_SFT 12 -#define RT5640_RAMP_DIS (0x0 << 12) -#define RT5640_RAMP_EN (0x1 << 12) -#define RT5640_BPS_MASK (0x1 << 11) -#define RT5640_BPS_SFT 11 -#define RT5640_BPS_DIS (0x0 << 11) -#define RT5640_BPS_EN (0x1 << 11) -#define RT5640_FAST_UPDN_MASK (0x1 << 10) -#define RT5640_FAST_UPDN_SFT 10 -#define RT5640_FAST_UPDN_DIS (0x0 << 10) -#define RT5640_FAST_UPDN_EN (0x1 << 10) -#define RT5640_MRES_MASK (0x3 << 8) -#define RT5640_MRES_SFT 8 -#define RT5640_MRES_15MO (0x0 << 8) -#define RT5640_MRES_25MO (0x1 << 8) -#define RT5640_MRES_35MO (0x2 << 8) -#define RT5640_MRES_45MO (0x3 << 8) -#define RT5640_VLO_MASK (0x1 << 7) -#define RT5640_VLO_SFT 7 -#define RT5640_VLO_3V (0x0 << 7) -#define RT5640_VLO_32V (0x1 << 7) -#define RT5640_DIG_DP_MASK (0x1 << 6) -#define RT5640_DIG_DP_SFT 6 -#define RT5640_DIG_DP_DIS (0x0 << 6) -#define RT5640_DIG_DP_EN (0x1 << 6) -#define RT5640_DP_TH_MASK (0x3 << 4) -#define RT5640_DP_TH_SFT 4 - -/* Depop Mode Control 3 (0x90) */ -#define RT5640_CP_SYS_MASK (0x7 << 12) -#define RT5640_CP_SYS_SFT 12 -#define RT5640_CP_FQ1_MASK (0x7 << 8) -#define RT5640_CP_FQ1_SFT 8 -#define RT5640_CP_FQ2_MASK (0x7 << 4) -#define RT5640_CP_FQ2_SFT 4 -#define RT5640_CP_FQ3_MASK (0x7) -#define RT5640_CP_FQ3_SFT 0 -#define RT5640_CP_FQ_1_5_KHZ 0 -#define RT5640_CP_FQ_3_KHZ 1 -#define RT5640_CP_FQ_6_KHZ 2 -#define RT5640_CP_FQ_12_KHZ 3 -#define RT5640_CP_FQ_24_KHZ 4 -#define RT5640_CP_FQ_48_KHZ 5 -#define RT5640_CP_FQ_96_KHZ 6 -#define RT5640_CP_FQ_192_KHZ 7 - -/* HPOUT charge pump (0x91) */ -#define RT5640_OSW_L_MASK (0x1 << 11) -#define RT5640_OSW_L_SFT 11 -#define RT5640_OSW_L_DIS (0x0 << 11) -#define RT5640_OSW_L_EN (0x1 << 11) -#define RT5640_OSW_R_MASK (0x1 << 10) -#define RT5640_OSW_R_SFT 10 -#define RT5640_OSW_R_DIS (0x0 << 10) -#define RT5640_OSW_R_EN (0x1 << 10) -#define RT5640_PM_HP_MASK (0x3 << 8) -#define RT5640_PM_HP_SFT 8 -#define RT5640_PM_HP_LV (0x0 << 8) -#define RT5640_PM_HP_MV (0x1 << 8) -#define RT5640_PM_HP_HV (0x2 << 8) -#define RT5640_IB_HP_MASK (0x3 << 6) -#define RT5640_IB_HP_SFT 6 -#define RT5640_IB_HP_125IL (0x0 << 6) -#define RT5640_IB_HP_25IL (0x1 << 6) -#define RT5640_IB_HP_5IL (0x2 << 6) -#define RT5640_IB_HP_1IL (0x3 << 6) - -/* PV detection and SPK gain control (0x92) */ -#define RT5640_PVDD_DET_MASK (0x1 << 15) -#define RT5640_PVDD_DET_SFT 15 -#define RT5640_PVDD_DET_DIS (0x0 << 15) -#define RT5640_PVDD_DET_EN (0x1 << 15) -#define RT5640_SPK_AG_MASK (0x1 << 14) -#define RT5640_SPK_AG_SFT 14 -#define RT5640_SPK_AG_DIS (0x0 << 14) -#define RT5640_SPK_AG_EN (0x1 << 14) - -/* Micbias Control (0x93) */ -#define RT5640_MIC1_BS_MASK (0x1 << 15) -#define RT5640_MIC1_BS_SFT 15 -#define RT5640_MIC1_BS_9AV (0x0 << 15) -#define RT5640_MIC1_BS_75AV (0x1 << 15) -#define RT5640_MIC2_BS_MASK (0x1 << 14) -#define RT5640_MIC2_BS_SFT 14 -#define RT5640_MIC2_BS_9AV (0x0 << 14) -#define RT5640_MIC2_BS_75AV (0x1 << 14) -#define RT5640_MIC1_CLK_MASK (0x1 << 13) -#define RT5640_MIC1_CLK_SFT 13 -#define RT5640_MIC1_CLK_DIS (0x0 << 13) -#define RT5640_MIC1_CLK_EN (0x1 << 13) -#define RT5640_MIC2_CLK_MASK (0x1 << 12) -#define RT5640_MIC2_CLK_SFT 12 -#define RT5640_MIC2_CLK_DIS (0x0 << 12) -#define RT5640_MIC2_CLK_EN (0x1 << 12) -#define RT5640_MIC1_OVCD_MASK (0x1 << 11) -#define RT5640_MIC1_OVCD_SFT 11 -#define RT5640_MIC1_OVCD_DIS (0x0 << 11) -#define RT5640_MIC1_OVCD_EN (0x1 << 11) -#define RT5640_MIC1_OVTH_MASK (0x3 << 9) -#define RT5640_MIC1_OVTH_SFT 9 -#define RT5640_MIC1_OVTH_600UA (0x0 << 9) -#define RT5640_MIC1_OVTH_1500UA (0x1 << 9) -#define RT5640_MIC1_OVTH_2000UA (0x2 << 9) -#define RT5640_MIC2_OVCD_MASK (0x1 << 8) -#define RT5640_MIC2_OVCD_SFT 8 -#define RT5640_MIC2_OVCD_DIS (0x0 << 8) -#define RT5640_MIC2_OVCD_EN (0x1 << 8) -#define RT5640_MIC2_OVTH_MASK (0x3 << 6) -#define RT5640_MIC2_OVTH_SFT 6 -#define RT5640_MIC2_OVTH_600UA (0x0 << 6) -#define RT5640_MIC2_OVTH_1500UA (0x1 << 6) -#define RT5640_MIC2_OVTH_2000UA (0x2 << 6) -#define RT5640_PWR_MB_MASK (0x1 << 5) -#define RT5640_PWR_MB_SFT 5 -#define RT5640_PWR_MB_PD (0x0 << 5) -#define RT5640_PWR_MB_PU (0x1 << 5) -#define RT5640_PWR_CLK25M_MASK (0x1 << 4) -#define RT5640_PWR_CLK25M_SFT 4 -#define RT5640_PWR_CLK25M_PD (0x0 << 4) -#define RT5640_PWR_CLK25M_PU (0x1 << 4) - -/* EQ Control 1 (0xb0) */ -#define RT5640_EQ_SRC_MASK (0x1 << 15) -#define RT5640_EQ_SRC_SFT 15 -#define RT5640_EQ_SRC_DAC (0x0 << 15) -#define RT5640_EQ_SRC_ADC (0x1 << 15) -#define RT5640_EQ_UPD (0x1 << 14) -#define RT5640_EQ_UPD_BIT 14 -#define RT5640_EQ_CD_MASK (0x1 << 13) -#define RT5640_EQ_CD_SFT 13 -#define RT5640_EQ_CD_DIS (0x0 << 13) -#define RT5640_EQ_CD_EN (0x1 << 13) -#define RT5640_EQ_DITH_MASK (0x3 << 8) -#define RT5640_EQ_DITH_SFT 8 -#define RT5640_EQ_DITH_NOR (0x0 << 8) -#define RT5640_EQ_DITH_LSB (0x1 << 8) -#define RT5640_EQ_DITH_LSB_1 (0x2 << 8) -#define RT5640_EQ_DITH_LSB_2 (0x3 << 8) - -/* EQ Control 2 (0xb1) */ -#define RT5640_EQ_HPF1_M_MASK (0x1 << 8) -#define RT5640_EQ_HPF1_M_SFT 8 -#define RT5640_EQ_HPF1_M_HI (0x0 << 8) -#define RT5640_EQ_HPF1_M_1ST (0x1 << 8) -#define RT5640_EQ_LPF1_M_MASK (0x1 << 7) -#define RT5640_EQ_LPF1_M_SFT 7 -#define RT5640_EQ_LPF1_M_LO (0x0 << 7) -#define RT5640_EQ_LPF1_M_1ST (0x1 << 7) -#define RT5640_EQ_HPF2_MASK (0x1 << 6) -#define RT5640_EQ_HPF2_SFT 6 -#define RT5640_EQ_HPF2_DIS (0x0 << 6) -#define RT5640_EQ_HPF2_EN (0x1 << 6) -#define RT5640_EQ_HPF1_MASK (0x1 << 5) -#define RT5640_EQ_HPF1_SFT 5 -#define RT5640_EQ_HPF1_DIS (0x0 << 5) -#define RT5640_EQ_HPF1_EN (0x1 << 5) -#define RT5640_EQ_BPF4_MASK (0x1 << 4) -#define RT5640_EQ_BPF4_SFT 4 -#define RT5640_EQ_BPF4_DIS (0x0 << 4) -#define RT5640_EQ_BPF4_EN (0x1 << 4) -#define RT5640_EQ_BPF3_MASK (0x1 << 3) -#define RT5640_EQ_BPF3_SFT 3 -#define RT5640_EQ_BPF3_DIS (0x0 << 3) -#define RT5640_EQ_BPF3_EN (0x1 << 3) -#define RT5640_EQ_BPF2_MASK (0x1 << 2) -#define RT5640_EQ_BPF2_SFT 2 -#define RT5640_EQ_BPF2_DIS (0x0 << 2) -#define RT5640_EQ_BPF2_EN (0x1 << 2) -#define RT5640_EQ_BPF1_MASK (0x1 << 1) -#define RT5640_EQ_BPF1_SFT 1 -#define RT5640_EQ_BPF1_DIS (0x0 << 1) -#define RT5640_EQ_BPF1_EN (0x1 << 1) -#define RT5640_EQ_LPF_MASK (0x1) -#define RT5640_EQ_LPF_SFT 0 -#define RT5640_EQ_LPF_DIS (0x0) -#define RT5640_EQ_LPF_EN (0x1) - -/* Memory Test (0xb2) */ -#define RT5640_MT_MASK (0x1 << 15) -#define RT5640_MT_SFT 15 -#define RT5640_MT_DIS (0x0 << 15) -#define RT5640_MT_EN (0x1 << 15) - -/* DRC/AGC Control 1 (0xb4) */ -#define RT5640_DRC_AGC_P_MASK (0x1 << 15) -#define RT5640_DRC_AGC_P_SFT 15 -#define RT5640_DRC_AGC_P_DAC (0x0 << 15) -#define RT5640_DRC_AGC_P_ADC (0x1 << 15) -#define RT5640_DRC_AGC_MASK (0x1 << 14) -#define RT5640_DRC_AGC_SFT 14 -#define RT5640_DRC_AGC_DIS (0x0 << 14) -#define RT5640_DRC_AGC_EN (0x1 << 14) -#define RT5640_DRC_AGC_UPD (0x1 << 13) -#define RT5640_DRC_AGC_UPD_BIT 13 -#define RT5640_DRC_AGC_AR_MASK (0x1f << 8) -#define RT5640_DRC_AGC_AR_SFT 8 -#define RT5640_DRC_AGC_R_MASK (0x7 << 5) -#define RT5640_DRC_AGC_R_SFT 5 -#define RT5640_DRC_AGC_R_48K (0x1 << 5) -#define RT5640_DRC_AGC_R_96K (0x2 << 5) -#define RT5640_DRC_AGC_R_192K (0x3 << 5) -#define RT5640_DRC_AGC_R_441K (0x5 << 5) -#define RT5640_DRC_AGC_R_882K (0x6 << 5) -#define RT5640_DRC_AGC_R_1764K (0x7 << 5) -#define RT5640_DRC_AGC_RC_MASK (0x1f) -#define RT5640_DRC_AGC_RC_SFT 0 - -/* DRC/AGC Control 2 (0xb5) */ -#define RT5640_DRC_AGC_POB_MASK (0x3f << 8) -#define RT5640_DRC_AGC_POB_SFT 8 -#define RT5640_DRC_AGC_CP_MASK (0x1 << 7) -#define RT5640_DRC_AGC_CP_SFT 7 -#define RT5640_DRC_AGC_CP_DIS (0x0 << 7) -#define RT5640_DRC_AGC_CP_EN (0x1 << 7) -#define RT5640_DRC_AGC_CPR_MASK (0x3 << 5) -#define RT5640_DRC_AGC_CPR_SFT 5 -#define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5) -#define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5) -#define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5) -#define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5) -#define RT5640_DRC_AGC_PRB_MASK (0x1f) -#define RT5640_DRC_AGC_PRB_SFT 0 - -/* DRC/AGC Control 3 (0xb6) */ -#define RT5640_DRC_AGC_NGB_MASK (0xf << 12) -#define RT5640_DRC_AGC_NGB_SFT 12 -#define RT5640_DRC_AGC_TAR_MASK (0x1f << 7) -#define RT5640_DRC_AGC_TAR_SFT 7 -#define RT5640_DRC_AGC_NG_MASK (0x1 << 6) -#define RT5640_DRC_AGC_NG_SFT 6 -#define RT5640_DRC_AGC_NG_DIS (0x0 << 6) -#define RT5640_DRC_AGC_NG_EN (0x1 << 6) -#define RT5640_DRC_AGC_NGH_MASK (0x1 << 5) -#define RT5640_DRC_AGC_NGH_SFT 5 -#define RT5640_DRC_AGC_NGH_DIS (0x0 << 5) -#define RT5640_DRC_AGC_NGH_EN (0x1 << 5) -#define RT5640_DRC_AGC_NGT_MASK (0x1f) -#define RT5640_DRC_AGC_NGT_SFT 0 - -/* ANC Control 1 (0xb8) */ -#define RT5640_ANC_M_MASK (0x1 << 15) -#define RT5640_ANC_M_SFT 15 -#define RT5640_ANC_M_NOR (0x0 << 15) -#define RT5640_ANC_M_REV (0x1 << 15) -#define RT5640_ANC_MASK (0x1 << 14) -#define RT5640_ANC_SFT 14 -#define RT5640_ANC_DIS (0x0 << 14) -#define RT5640_ANC_EN (0x1 << 14) -#define RT5640_ANC_MD_MASK (0x3 << 12) -#define RT5640_ANC_MD_SFT 12 -#define RT5640_ANC_MD_DIS (0x0 << 12) -#define RT5640_ANC_MD_67MS (0x1 << 12) -#define RT5640_ANC_MD_267MS (0x2 << 12) -#define RT5640_ANC_MD_1067MS (0x3 << 12) -#define RT5640_ANC_SN_MASK (0x1 << 11) -#define RT5640_ANC_SN_SFT 11 -#define RT5640_ANC_SN_DIS (0x0 << 11) -#define RT5640_ANC_SN_EN (0x1 << 11) -#define RT5640_ANC_CLK_MASK (0x1 << 10) -#define RT5640_ANC_CLK_SFT 10 -#define RT5640_ANC_CLK_ANC (0x0 << 10) -#define RT5640_ANC_CLK_REG (0x1 << 10) -#define RT5640_ANC_ZCD_MASK (0x3 << 8) -#define RT5640_ANC_ZCD_SFT 8 -#define RT5640_ANC_ZCD_DIS (0x0 << 8) -#define RT5640_ANC_ZCD_T1 (0x1 << 8) -#define RT5640_ANC_ZCD_T2 (0x2 << 8) -#define RT5640_ANC_ZCD_WT (0x3 << 8) -#define RT5640_ANC_CS_MASK (0x1 << 7) -#define RT5640_ANC_CS_SFT 7 -#define RT5640_ANC_CS_DIS (0x0 << 7) -#define RT5640_ANC_CS_EN (0x1 << 7) -#define RT5640_ANC_SW_MASK (0x1 << 6) -#define RT5640_ANC_SW_SFT 6 -#define RT5640_ANC_SW_NOR (0x0 << 6) -#define RT5640_ANC_SW_AUTO (0x1 << 6) -#define RT5640_ANC_CO_L_MASK (0x3f) -#define RT5640_ANC_CO_L_SFT 0 - -/* ANC Control 2 (0xb6) */ -#define RT5640_ANC_FG_R_MASK (0xf << 12) -#define RT5640_ANC_FG_R_SFT 12 -#define RT5640_ANC_FG_L_MASK (0xf << 8) -#define RT5640_ANC_FG_L_SFT 8 -#define RT5640_ANC_CG_R_MASK (0xf << 4) -#define RT5640_ANC_CG_R_SFT 4 -#define RT5640_ANC_CG_L_MASK (0xf) -#define RT5640_ANC_CG_L_SFT 0 - -/* ANC Control 3 (0xb6) */ -#define RT5640_ANC_CD_MASK (0x1 << 6) -#define RT5640_ANC_CD_SFT 6 -#define RT5640_ANC_CD_BOTH (0x0 << 6) -#define RT5640_ANC_CD_IND (0x1 << 6) -#define RT5640_ANC_CO_R_MASK (0x3f) -#define RT5640_ANC_CO_R_SFT 0 - -/* Jack Detect Control (0xbb) */ -#define RT5640_JD_MASK (0x7 << 13) -#define RT5640_JD_SFT 13 -#define RT5640_JD_DIS (0x0 << 13) -#define RT5640_JD_GPIO1 (0x1 << 13) -#define RT5640_JD_JD1_IN4P (0x2 << 13) -#define RT5640_JD_JD2_IN4N (0x3 << 13) -#define RT5640_JD_GPIO2 (0x4 << 13) -#define RT5640_JD_GPIO3 (0x5 << 13) -#define RT5640_JD_GPIO4 (0x6 << 13) -#define RT5640_JD_HP_MASK (0x1 << 11) -#define RT5640_JD_HP_SFT 11 -#define RT5640_JD_HP_DIS (0x0 << 11) -#define RT5640_JD_HP_EN (0x1 << 11) -#define RT5640_JD_HP_TRG_MASK (0x1 << 10) -#define RT5640_JD_HP_TRG_SFT 10 -#define RT5640_JD_HP_TRG_LO (0x0 << 10) -#define RT5640_JD_HP_TRG_HI (0x1 << 10) -#define RT5640_JD_SPL_MASK (0x1 << 9) -#define RT5640_JD_SPL_SFT 9 -#define RT5640_JD_SPL_DIS (0x0 << 9) -#define RT5640_JD_SPL_EN (0x1 << 9) -#define RT5640_JD_SPL_TRG_MASK (0x1 << 8) -#define RT5640_JD_SPL_TRG_SFT 8 -#define RT5640_JD_SPL_TRG_LO (0x0 << 8) -#define RT5640_JD_SPL_TRG_HI (0x1 << 8) -#define RT5640_JD_SPR_MASK (0x1 << 7) -#define RT5640_JD_SPR_SFT 7 -#define RT5640_JD_SPR_DIS (0x0 << 7) -#define RT5640_JD_SPR_EN (0x1 << 7) -#define RT5640_JD_SPR_TRG_MASK (0x1 << 6) -#define RT5640_JD_SPR_TRG_SFT 6 -#define RT5640_JD_SPR_TRG_LO (0x0 << 6) -#define RT5640_JD_SPR_TRG_HI (0x1 << 6) -#define RT5640_JD_MO_MASK (0x1 << 5) -#define RT5640_JD_MO_SFT 5 -#define RT5640_JD_MO_DIS (0x0 << 5) -#define RT5640_JD_MO_EN (0x1 << 5) -#define RT5640_JD_MO_TRG_MASK (0x1 << 4) -#define RT5640_JD_MO_TRG_SFT 4 -#define RT5640_JD_MO_TRG_LO (0x0 << 4) -#define RT5640_JD_MO_TRG_HI (0x1 << 4) -#define RT5640_JD_LO_MASK (0x1 << 3) -#define RT5640_JD_LO_SFT 3 -#define RT5640_JD_LO_DIS (0x0 << 3) -#define RT5640_JD_LO_EN (0x1 << 3) -#define RT5640_JD_LO_TRG_MASK (0x1 << 2) -#define RT5640_JD_LO_TRG_SFT 2 -#define RT5640_JD_LO_TRG_LO (0x0 << 2) -#define RT5640_JD_LO_TRG_HI (0x1 << 2) -#define RT5640_JD1_IN4P_MASK (0x1 << 1) -#define RT5640_JD1_IN4P_SFT 1 -#define RT5640_JD1_IN4P_DIS (0x0 << 1) -#define RT5640_JD1_IN4P_EN (0x1 << 1) -#define RT5640_JD2_IN4N_MASK (0x1) -#define RT5640_JD2_IN4N_SFT 0 -#define RT5640_JD2_IN4N_DIS (0x0) -#define RT5640_JD2_IN4N_EN (0x1) - -/* Jack detect for ANC (0xbc) */ -#define RT5640_ANC_DET_MASK (0x3 << 4) -#define RT5640_ANC_DET_SFT 4 -#define RT5640_ANC_DET_DIS (0x0 << 4) -#define RT5640_ANC_DET_MB1 (0x1 << 4) -#define RT5640_ANC_DET_MB2 (0x2 << 4) -#define RT5640_ANC_DET_JD (0x3 << 4) -#define RT5640_AD_TRG_MASK (0x1 << 3) -#define RT5640_AD_TRG_SFT 3 -#define RT5640_AD_TRG_LO (0x0 << 3) -#define RT5640_AD_TRG_HI (0x1 << 3) -#define RT5640_ANCM_DET_MASK (0x3 << 4) -#define RT5640_ANCM_DET_SFT 4 -#define RT5640_ANCM_DET_DIS (0x0 << 4) -#define RT5640_ANCM_DET_MB1 (0x1 << 4) -#define RT5640_ANCM_DET_MB2 (0x2 << 4) -#define RT5640_ANCM_DET_JD (0x3 << 4) -#define RT5640_AMD_TRG_MASK (0x1 << 3) -#define RT5640_AMD_TRG_SFT 3 -#define RT5640_AMD_TRG_LO (0x0 << 3) -#define RT5640_AMD_TRG_HI (0x1 << 3) - -/* IRQ Control 1 (0xbd) */ -#define RT5640_IRQ_JD_MASK (0x1 << 15) -#define RT5640_IRQ_JD_SFT 15 -#define RT5640_IRQ_JD_BP (0x0 << 15) -#define RT5640_IRQ_JD_NOR (0x1 << 15) -#define RT5640_IRQ_OT_MASK (0x1 << 14) -#define RT5640_IRQ_OT_SFT 14 -#define RT5640_IRQ_OT_BP (0x0 << 14) -#define RT5640_IRQ_OT_NOR (0x1 << 14) -#define RT5640_JD_STKY_MASK (0x1 << 13) -#define RT5640_JD_STKY_SFT 13 -#define RT5640_JD_STKY_DIS (0x0 << 13) -#define RT5640_JD_STKY_EN (0x1 << 13) -#define RT5640_OT_STKY_MASK (0x1 << 12) -#define RT5640_OT_STKY_SFT 12 -#define RT5640_OT_STKY_DIS (0x0 << 12) -#define RT5640_OT_STKY_EN (0x1 << 12) -#define RT5640_JD_P_MASK (0x1 << 11) -#define RT5640_JD_P_SFT 11 -#define RT5640_JD_P_NOR (0x0 << 11) -#define RT5640_JD_P_INV (0x1 << 11) -#define RT5640_OT_P_MASK (0x1 << 10) -#define RT5640_OT_P_SFT 10 -#define RT5640_OT_P_NOR (0x0 << 10) -#define RT5640_OT_P_INV (0x1 << 10) - -/* IRQ Control 2 (0xbe) */ -#define RT5640_IRQ_MB1_OC_MASK (0x1 << 15) -#define RT5640_IRQ_MB1_OC_SFT 15 -#define RT5640_IRQ_MB1_OC_BP (0x0 << 15) -#define RT5640_IRQ_MB1_OC_NOR (0x1 << 15) -#define RT5640_IRQ_MB2_OC_MASK (0x1 << 14) -#define RT5640_IRQ_MB2_OC_SFT 14 -#define RT5640_IRQ_MB2_OC_BP (0x0 << 14) -#define RT5640_IRQ_MB2_OC_NOR (0x1 << 14) -#define RT5640_MB1_OC_STKY_MASK (0x1 << 11) -#define RT5640_MB1_OC_STKY_SFT 11 -#define RT5640_MB1_OC_STKY_DIS (0x0 << 11) -#define RT5640_MB1_OC_STKY_EN (0x1 << 11) -#define RT5640_MB2_OC_STKY_MASK (0x1 << 10) -#define RT5640_MB2_OC_STKY_SFT 10 -#define RT5640_MB2_OC_STKY_DIS (0x0 << 10) -#define RT5640_MB2_OC_STKY_EN (0x1 << 10) -#define RT5640_MB1_OC_P_MASK (0x1 << 7) -#define RT5640_MB1_OC_P_SFT 7 -#define RT5640_MB1_OC_P_NOR (0x0 << 7) -#define RT5640_MB1_OC_P_INV (0x1 << 7) -#define RT5640_MB2_OC_P_MASK (0x1 << 6) -#define RT5640_MB2_OC_P_SFT 6 -#define RT5640_MB2_OC_P_NOR (0x0 << 6) -#define RT5640_MB2_OC_P_INV (0x1 << 6) -#define RT5640_MB1_OC_STATUS (0x1 << 3) -#define RT5640_MB1_OC_STATUS_SFT 3 -#define RT5640_MB2_OC_STATUS (0x1 << 2) -#define RT5640_MB2_OC_STATUS_SFT 2 - -/* GPIO and Internal Status (0xbf) */ -#define RT5640_GPIO1_STATUS (0x1 << 8) -#define RT5640_GPIO2_STATUS (0x1 << 7) -#define RT5640_JD_STATUS (0x1 << 4) -#define RT5640_OVT_STATUS (0x1 << 3) -#define RT5640_CLS_D_OVCD_STATUS (0x1 << 0) - -/* GPIO Control 1 (0xc0) */ -#define RT5640_GP1_PIN_MASK (0x1 << 15) -#define RT5640_GP1_PIN_SFT 15 -#define RT5640_GP1_PIN_GPIO1 (0x0 << 15) -#define RT5640_GP1_PIN_IRQ (0x1 << 15) -#define RT5640_GP2_PIN_MASK (0x1 << 14) -#define RT5640_GP2_PIN_SFT 14 -#define RT5640_GP2_PIN_GPIO2 (0x0 << 14) -#define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14) -#define RT5640_GP3_PIN_MASK (0x3 << 12) -#define RT5640_GP3_PIN_SFT 12 -#define RT5640_GP3_PIN_GPIO3 (0x0 << 12) -#define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12) -#define RT5640_GP3_PIN_IRQ (0x2 << 12) -#define RT5640_GP4_PIN_MASK (0x1 << 11) -#define RT5640_GP4_PIN_SFT 11 -#define RT5640_GP4_PIN_GPIO4 (0x0 << 11) -#define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11) -#define RT5640_DP_SIG_MASK (0x1 << 10) -#define RT5640_DP_SIG_SFT 10 -#define RT5640_DP_SIG_TEST (0x0 << 10) -#define RT5640_DP_SIG_AP (0x1 << 10) -#define RT5640_GPIO_M_MASK (0x1 << 9) -#define RT5640_GPIO_M_SFT 9 -#define RT5640_GPIO_M_FLT (0x0 << 9) -#define RT5640_GPIO_M_PH (0x1 << 9) - -/* GPIO Control 3 (0xc2) */ -#define RT5640_GP4_PF_MASK (0x1 << 11) -#define RT5640_GP4_PF_SFT 11 -#define RT5640_GP4_PF_IN (0x0 << 11) -#define RT5640_GP4_PF_OUT (0x1 << 11) -#define RT5640_GP4_OUT_MASK (0x1 << 10) -#define RT5640_GP4_OUT_SFT 10 -#define RT5640_GP4_OUT_LO (0x0 << 10) -#define RT5640_GP4_OUT_HI (0x1 << 10) -#define RT5640_GP4_P_MASK (0x1 << 9) -#define RT5640_GP4_P_SFT 9 -#define RT5640_GP4_P_NOR (0x0 << 9) -#define RT5640_GP4_P_INV (0x1 << 9) -#define RT5640_GP3_PF_MASK (0x1 << 8) -#define RT5640_GP3_PF_SFT 8 -#define RT5640_GP3_PF_IN (0x0 << 8) -#define RT5640_GP3_PF_OUT (0x1 << 8) -#define RT5640_GP3_OUT_MASK (0x1 << 7) -#define RT5640_GP3_OUT_SFT 7 -#define RT5640_GP3_OUT_LO (0x0 << 7) -#define RT5640_GP3_OUT_HI (0x1 << 7) -#define RT5640_GP3_P_MASK (0x1 << 6) -#define RT5640_GP3_P_SFT 6 -#define RT5640_GP3_P_NOR (0x0 << 6) -#define RT5640_GP3_P_INV (0x1 << 6) -#define RT5640_GP2_PF_MASK (0x1 << 5) -#define RT5640_GP2_PF_SFT 5 -#define RT5640_GP2_PF_IN (0x0 << 5) -#define RT5640_GP2_PF_OUT (0x1 << 5) -#define RT5640_GP2_OUT_MASK (0x1 << 4) -#define RT5640_GP2_OUT_SFT 4 -#define RT5640_GP2_OUT_LO (0x0 << 4) -#define RT5640_GP2_OUT_HI (0x1 << 4) -#define RT5640_GP2_P_MASK (0x1 << 3) -#define RT5640_GP2_P_SFT 3 -#define RT5640_GP2_P_NOR (0x0 << 3) -#define RT5640_GP2_P_INV (0x1 << 3) -#define RT5640_GP1_PF_MASK (0x1 << 2) -#define RT5640_GP1_PF_SFT 2 -#define RT5640_GP1_PF_IN (0x0 << 2) -#define RT5640_GP1_PF_OUT (0x1 << 2) -#define RT5640_GP1_OUT_MASK (0x1 << 1) -#define RT5640_GP1_OUT_SFT 1 -#define RT5640_GP1_OUT_LO (0x0 << 1) -#define RT5640_GP1_OUT_HI (0x1 << 1) -#define RT5640_GP1_P_MASK (0x1) -#define RT5640_GP1_P_SFT 0 -#define RT5640_GP1_P_NOR (0x0) -#define RT5640_GP1_P_INV (0x1) - -/* FM34-500 Register Control 1 (0xc4) */ -#define RT5640_DSP_ADD_SFT 0 - -/* FM34-500 Register Control 2 (0xc5) */ -#define RT5640_DSP_DAT_SFT 0 - -/* FM34-500 Register Control 3 (0xc6) */ -#define RT5640_DSP_BUSY_MASK (0x1 << 15) -#define RT5640_DSP_BUSY_BIT 15 -#define RT5640_DSP_DS_MASK (0x1 << 14) -#define RT5640_DSP_DS_SFT 14 -#define RT5640_DSP_DS_FM3010 (0x1 << 14) -#define RT5640_DSP_DS_TEMP (0x1 << 14) -#define RT5640_DSP_CLK_MASK (0x3 << 12) -#define RT5640_DSP_CLK_SFT 12 -#define RT5640_DSP_CLK_384K (0x0 << 12) -#define RT5640_DSP_CLK_192K (0x1 << 12) -#define RT5640_DSP_CLK_96K (0x2 << 12) -#define RT5640_DSP_CLK_64K (0x3 << 12) -#define RT5640_DSP_PD_PIN_MASK (0x1 << 11) -#define RT5640_DSP_PD_PIN_SFT 11 -#define RT5640_DSP_PD_PIN_LO (0x0 << 11) -#define RT5640_DSP_PD_PIN_HI (0x1 << 11) -#define RT5640_DSP_RST_PIN_MASK (0x1 << 10) -#define RT5640_DSP_RST_PIN_SFT 10 -#define RT5640_DSP_RST_PIN_LO (0x0 << 10) -#define RT5640_DSP_RST_PIN_HI (0x1 << 10) -#define RT5640_DSP_R_EN (0x1 << 9) -#define RT5640_DSP_R_EN_BIT 9 -#define RT5640_DSP_W_EN (0x1 << 8) -#define RT5640_DSP_W_EN_BIT 8 -#define RT5640_DSP_CMD_MASK (0xff) -#define RT5640_DSP_CMD_SFT 0 -#define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */ -#define RT5640_DSP_CMD_MR (0x37) /* Memory Read */ -#define RT5640_DSP_CMD_RR (0x60) /* Register Read */ -#define RT5640_DSP_CMD_RW (0x68) /* Register Write */ - -/* Programmable Register Array Control 1 (0xc8) */ -#define RT5640_REG_SEQ_MASK (0xf << 12) -#define RT5640_REG_SEQ_SFT 12 -#define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/ -#define RT5640_SEQ1_ST_SFT 11 -#define RT5640_SEQ1_ST_RUN (0x0 << 11) -#define RT5640_SEQ1_ST_FIN (0x1 << 11) -#define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/ -#define RT5640_SEQ2_ST_SFT 10 -#define RT5640_SEQ2_ST_RUN (0x0 << 10) -#define RT5640_SEQ2_ST_FIN (0x1 << 10) -#define RT5640_REG_LV_MASK (0x1 << 9) -#define RT5640_REG_LV_SFT 9 -#define RT5640_REG_LV_MX (0x0 << 9) -#define RT5640_REG_LV_PR (0x1 << 9) -#define RT5640_SEQ_2_PT_MASK (0x1 << 8) -#define RT5640_SEQ_2_PT_BIT 8 -#define RT5640_REG_IDX_MASK (0xff) -#define RT5640_REG_IDX_SFT 0 - -/* Programmable Register Array Control 2 (0xc9) */ -#define RT5640_REG_DAT_MASK (0xffff) -#define RT5640_REG_DAT_SFT 0 - -/* Programmable Register Array Control 3 (0xca) */ -#define RT5640_SEQ_DLY_MASK (0xff << 8) -#define RT5640_SEQ_DLY_SFT 8 -#define RT5640_PROG_MASK (0x1 << 7) -#define RT5640_PROG_SFT 7 -#define RT5640_PROG_DIS (0x0 << 7) -#define RT5640_PROG_EN (0x1 << 7) -#define RT5640_SEQ1_PT_RUN (0x1 << 6) -#define RT5640_SEQ1_PT_RUN_BIT 6 -#define RT5640_SEQ2_PT_RUN (0x1 << 5) -#define RT5640_SEQ2_PT_RUN_BIT 5 - -/* Programmable Register Array Control 4 (0xcb) */ -#define RT5640_SEQ1_START_MASK (0xf << 8) -#define RT5640_SEQ1_START_SFT 8 -#define RT5640_SEQ1_END_MASK (0xf) -#define RT5640_SEQ1_END_SFT 0 - -/* Programmable Register Array Control 5 (0xcc) */ -#define RT5640_SEQ2_START_MASK (0xf << 8) -#define RT5640_SEQ2_START_SFT 8 -#define RT5640_SEQ2_END_MASK (0xf) -#define RT5640_SEQ2_END_SFT 0 - -/* Scramble Function (0xcd) */ -#define RT5640_SCB_KEY_MASK (0xff) -#define RT5640_SCB_KEY_SFT 0 - -/* Scramble Control (0xce) */ -#define RT5640_SCB_SWAP_MASK (0x1 << 15) -#define RT5640_SCB_SWAP_SFT 15 -#define RT5640_SCB_SWAP_DIS (0x0 << 15) -#define RT5640_SCB_SWAP_EN (0x1 << 15) -#define RT5640_SCB_MASK (0x1 << 14) -#define RT5640_SCB_SFT 14 -#define RT5640_SCB_DIS (0x0 << 14) -#define RT5640_SCB_EN (0x1 << 14) - -/* Baseback Control (0xcf) */ -#define RT5640_BB_MASK (0x1 << 15) -#define RT5640_BB_SFT 15 -#define RT5640_BB_DIS (0x0 << 15) -#define RT5640_BB_EN (0x1 << 15) -#define RT5640_BB_CT_MASK (0x7 << 12) -#define RT5640_BB_CT_SFT 12 -#define RT5640_BB_CT_A (0x0 << 12) -#define RT5640_BB_CT_B (0x1 << 12) -#define RT5640_BB_CT_C (0x2 << 12) -#define RT5640_BB_CT_D (0x3 << 12) -#define RT5640_M_BB_L_MASK (0x1 << 9) -#define RT5640_M_BB_L_SFT 9 -#define RT5640_M_BB_R_MASK (0x1 << 8) -#define RT5640_M_BB_R_SFT 8 -#define RT5640_M_BB_HPF_L_MASK (0x1 << 7) -#define RT5640_M_BB_HPF_L_SFT 7 -#define RT5640_M_BB_HPF_R_MASK (0x1 << 6) -#define RT5640_M_BB_HPF_R_SFT 6 -#define RT5640_G_BB_BST_MASK (0x3f) -#define RT5640_G_BB_BST_SFT 0 - -/* MP3 Plus Control 1 (0xd0) */ -#define RT5640_M_MP3_L_MASK (0x1 << 15) -#define RT5640_M_MP3_L_SFT 15 -#define RT5640_M_MP3_R_MASK (0x1 << 14) -#define RT5640_M_MP3_R_SFT 14 -#define RT5640_M_MP3_MASK (0x1 << 13) -#define RT5640_M_MP3_SFT 13 -#define RT5640_M_MP3_DIS (0x0 << 13) -#define RT5640_M_MP3_EN (0x1 << 13) -#define RT5640_EG_MP3_MASK (0x1f << 8) -#define RT5640_EG_MP3_SFT 8 -#define RT5640_MP3_HLP_MASK (0x1 << 7) -#define RT5640_MP3_HLP_SFT 7 -#define RT5640_MP3_HLP_DIS (0x0 << 7) -#define RT5640_MP3_HLP_EN (0x1 << 7) -#define RT5640_M_MP3_ORG_L_MASK (0x1 << 6) -#define RT5640_M_MP3_ORG_L_SFT 6 -#define RT5640_M_MP3_ORG_R_MASK (0x1 << 5) -#define RT5640_M_MP3_ORG_R_SFT 5 - -/* MP3 Plus Control 2 (0xd1) */ -#define RT5640_MP3_WT_MASK (0x1 << 13) -#define RT5640_MP3_WT_SFT 13 -#define RT5640_MP3_WT_1_4 (0x0 << 13) -#define RT5640_MP3_WT_1_2 (0x1 << 13) -#define RT5640_OG_MP3_MASK (0x1f << 8) -#define RT5640_OG_MP3_SFT 8 -#define RT5640_HG_MP3_MASK (0x3f) -#define RT5640_HG_MP3_SFT 0 - -/* 3D HP Control 1 (0xd2) */ -#define RT5640_3D_CF_MASK (0x1 << 15) -#define RT5640_3D_CF_SFT 15 -#define RT5640_3D_CF_DIS (0x0 << 15) -#define RT5640_3D_CF_EN (0x1 << 15) -#define RT5640_3D_HP_MASK (0x1 << 14) -#define RT5640_3D_HP_SFT 14 -#define RT5640_3D_HP_DIS (0x0 << 14) -#define RT5640_3D_HP_EN (0x1 << 14) -#define RT5640_3D_BT_MASK (0x1 << 13) -#define RT5640_3D_BT_SFT 13 -#define RT5640_3D_BT_DIS (0x0 << 13) -#define RT5640_3D_BT_EN (0x1 << 13) -#define RT5640_3D_1F_MIX_MASK (0x3 << 11) -#define RT5640_3D_1F_MIX_SFT 11 -#define RT5640_3D_HP_M_MASK (0x1 << 10) -#define RT5640_3D_HP_M_SFT 10 -#define RT5640_3D_HP_M_SUR (0x0 << 10) -#define RT5640_3D_HP_M_FRO (0x1 << 10) -#define RT5640_M_3D_HRTF_MASK (0x1 << 9) -#define RT5640_M_3D_HRTF_SFT 9 -#define RT5640_M_3D_D2H_MASK (0x1 << 8) -#define RT5640_M_3D_D2H_SFT 8 -#define RT5640_M_3D_D2R_MASK (0x1 << 7) -#define RT5640_M_3D_D2R_SFT 7 -#define RT5640_M_3D_REVB_MASK (0x1 << 6) -#define RT5640_M_3D_REVB_SFT 6 - -/* Adjustable high pass filter control 1 (0xd3) */ -#define RT5640_2ND_HPF_MASK (0x1 << 15) -#define RT5640_2ND_HPF_SFT 15 -#define RT5640_2ND_HPF_DIS (0x0 << 15) -#define RT5640_2ND_HPF_EN (0x1 << 15) -#define RT5640_HPF_CF_L_MASK (0x7 << 12) -#define RT5640_HPF_CF_L_SFT 12 -#define RT5640_1ST_HPF_MASK (0x1 << 11) -#define RT5640_1ST_HPF_SFT 11 -#define RT5640_1ST_HPF_DIS (0x0 << 11) -#define RT5640_1ST_HPF_EN (0x1 << 11) -#define RT5640_HPF_CF_R_MASK (0x7 << 8) -#define RT5640_HPF_CF_R_SFT 8 -#define RT5640_ZD_T_MASK (0x3 << 6) -#define RT5640_ZD_T_SFT 6 -#define RT5640_ZD_F_MASK (0x3 << 4) -#define RT5640_ZD_F_SFT 4 -#define RT5640_ZD_F_IM (0x0 << 4) -#define RT5640_ZD_F_ZC_IM (0x1 << 4) -#define RT5640_ZD_F_ZC_IOD (0x2 << 4) -#define RT5640_ZD_F_UN (0x3 << 4) - -/* HP calibration control and Amp detection (0xd6) */ -#define RT5640_SI_DAC_MASK (0x1 << 11) -#define RT5640_SI_DAC_SFT 11 -#define RT5640_SI_DAC_AUTO (0x0 << 11) -#define RT5640_SI_DAC_TEST (0x1 << 11) -#define RT5640_DC_CAL_M_MASK (0x1 << 10) -#define RT5640_DC_CAL_M_SFT 10 -#define RT5640_DC_CAL_M_CAL (0x0 << 10) -#define RT5640_DC_CAL_M_NOR (0x1 << 10) -#define RT5640_DC_CAL_MASK (0x1 << 9) -#define RT5640_DC_CAL_SFT 9 -#define RT5640_DC_CAL_DIS (0x0 << 9) -#define RT5640_DC_CAL_EN (0x1 << 9) -#define RT5640_HPD_RCV_MASK (0x7 << 6) -#define RT5640_HPD_RCV_SFT 6 -#define RT5640_HPD_PS_MASK (0x1 << 5) -#define RT5640_HPD_PS_SFT 5 -#define RT5640_HPD_PS_DIS (0x0 << 5) -#define RT5640_HPD_PS_EN (0x1 << 5) -#define RT5640_CAL_M_MASK (0x1 << 4) -#define RT5640_CAL_M_SFT 4 -#define RT5640_CAL_M_DEP (0x0 << 4) -#define RT5640_CAL_M_CAL (0x1 << 4) -#define RT5640_CAL_MASK (0x1 << 3) -#define RT5640_CAL_SFT 3 -#define RT5640_CAL_DIS (0x0 << 3) -#define RT5640_CAL_EN (0x1 << 3) -#define RT5640_CAL_TEST_MASK (0x1 << 2) -#define RT5640_CAL_TEST_SFT 2 -#define RT5640_CAL_TEST_DIS (0x0 << 2) -#define RT5640_CAL_TEST_EN (0x1 << 2) -#define RT5640_CAL_P_MASK (0x3) -#define RT5640_CAL_P_SFT 0 -#define RT5640_CAL_P_NONE (0x0) -#define RT5640_CAL_P_CAL (0x1) -#define RT5640_CAL_P_DAC_CAL (0x2) - -/* Soft volume and zero cross control 1 (0xd9) */ -#define RT5640_SV_MASK (0x1 << 15) -#define RT5640_SV_SFT 15 -#define RT5640_SV_DIS (0x0 << 15) -#define RT5640_SV_EN (0x1 << 15) -#define RT5640_SPO_SV_MASK (0x1 << 14) -#define RT5640_SPO_SV_SFT 14 -#define RT5640_SPO_SV_DIS (0x0 << 14) -#define RT5640_SPO_SV_EN (0x1 << 14) -#define RT5640_OUT_SV_MASK (0x1 << 13) -#define RT5640_OUT_SV_SFT 13 -#define RT5640_OUT_SV_DIS (0x0 << 13) -#define RT5640_OUT_SV_EN (0x1 << 13) -#define RT5640_HP_SV_MASK (0x1 << 12) -#define RT5640_HP_SV_SFT 12 -#define RT5640_HP_SV_DIS (0x0 << 12) -#define RT5640_HP_SV_EN (0x1 << 12) -#define RT5640_ZCD_DIG_MASK (0x1 << 11) -#define RT5640_ZCD_DIG_SFT 11 -#define RT5640_ZCD_DIG_DIS (0x0 << 11) -#define RT5640_ZCD_DIG_EN (0x1 << 11) -#define RT5640_ZCD_MASK (0x1 << 10) -#define RT5640_ZCD_SFT 10 -#define RT5640_ZCD_PD (0x0 << 10) -#define RT5640_ZCD_PU (0x1 << 10) -#define RT5640_M_ZCD_MASK (0x3f << 4) -#define RT5640_M_ZCD_SFT 4 -#define RT5640_M_ZCD_RM_L (0x1 << 9) -#define RT5640_M_ZCD_RM_R (0x1 << 8) -#define RT5640_M_ZCD_SM_L (0x1 << 7) -#define RT5640_M_ZCD_SM_R (0x1 << 6) -#define RT5640_M_ZCD_OM_L (0x1 << 5) -#define RT5640_M_ZCD_OM_R (0x1 << 4) -#define RT5640_SV_DLY_MASK (0xf) -#define RT5640_SV_DLY_SFT 0 - -/* Soft volume and zero cross control 2 (0xda) */ -#define RT5640_ZCD_HP_MASK (0x1 << 15) -#define RT5640_ZCD_HP_SFT 15 -#define RT5640_ZCD_HP_DIS (0x0 << 15) -#define RT5640_ZCD_HP_EN (0x1 << 15) - -/* General Control 1 (0xfa) */ -#define RT5640_M_MONO_ADC_L (0x1 << 13) -#define RT5640_M_MONO_ADC_L_SFT 13 -#define RT5640_M_MONO_ADC_R (0x1 << 12) -#define RT5640_M_MONO_ADC_R_SFT 12 -#define RT5640_MCLK_DET (0x1 << 11) - -/* Codec Private Register definition */ - -/* MIC Over current threshold scale factor (0x15) */ -#define RT5640_MIC_OVCD_SF_MASK (0x3 << 8) -#define RT5640_MIC_OVCD_SF_SFT 8 -#define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8) -#define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8) -#define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8) -#define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8) - -/* 3D Speaker Control (0x63) */ -#define RT5640_3D_SPK_MASK (0x1 << 15) -#define RT5640_3D_SPK_SFT 15 -#define RT5640_3D_SPK_DIS (0x0 << 15) -#define RT5640_3D_SPK_EN (0x1 << 15) -#define RT5640_3D_SPK_M_MASK (0x3 << 13) -#define RT5640_3D_SPK_M_SFT 13 -#define RT5640_3D_SPK_CG_MASK (0x1f << 8) -#define RT5640_3D_SPK_CG_SFT 8 -#define RT5640_3D_SPK_SG_MASK (0x1f) -#define RT5640_3D_SPK_SG_SFT 0 - -/* Wind Noise Detection Control 1 (0x6c) */ -#define RT5640_WND_MASK (0x1 << 15) -#define RT5640_WND_SFT 15 -#define RT5640_WND_DIS (0x0 << 15) -#define RT5640_WND_EN (0x1 << 15) - -/* Wind Noise Detection Control 2 (0x6d) */ -#define RT5640_WND_FC_NW_MASK (0x3f << 10) -#define RT5640_WND_FC_NW_SFT 10 -#define RT5640_WND_FC_WK_MASK (0x3f << 4) -#define RT5640_WND_FC_WK_SFT 4 - -/* Wind Noise Detection Control 3 (0x6e) */ -#define RT5640_HPF_FC_MASK (0x3f << 6) -#define RT5640_HPF_FC_SFT 6 -#define RT5640_WND_FC_ST_MASK (0x3f) -#define RT5640_WND_FC_ST_SFT 0 - -/* Wind Noise Detection Control 4 (0x6f) */ -#define RT5640_WND_TH_LO_MASK (0x3ff) -#define RT5640_WND_TH_LO_SFT 0 - -/* Wind Noise Detection Control 5 (0x70) */ -#define RT5640_WND_TH_HI_MASK (0x3ff) -#define RT5640_WND_TH_HI_SFT 0 - -/* Wind Noise Detection Control 8 (0x73) */ -#define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */ -#define RT5640_WND_WIND_SFT 13 -#define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ -#define RT5640_WND_STRONG_SFT 12 -enum { - RT5640_NO_WIND, - RT5640_BREEZE, - RT5640_STORM, -}; - -/* Dipole Speaker Interface (0x75) */ -#define RT5640_DP_ATT_MASK (0x3 << 14) -#define RT5640_DP_ATT_SFT 14 -#define RT5640_DP_SPK_MASK (0x1 << 10) -#define RT5640_DP_SPK_SFT 10 -#define RT5640_DP_SPK_DIS (0x0 << 10) -#define RT5640_DP_SPK_EN (0x1 << 10) - -/* EQ Pre Volume Control (0xb3) */ -#define RT5640_EQ_PRE_VOL_MASK (0xffff) -#define RT5640_EQ_PRE_VOL_SFT 0 - -/* EQ Post Volume Control (0xb4) */ -#define RT5640_EQ_PST_VOL_MASK (0xffff) -#define RT5640_EQ_PST_VOL_SFT 0 - -#define RT5640_NO_JACK BIT(0) -#define RT5640_HEADSET_DET BIT(1) -#define RT5640_HEADPHO_DET BIT(2) - -/* System Clock Source */ -#define RT5640_SCLK_S_MCLK 0 -#define RT5640_SCLK_S_PLL1 1 -#define RT5640_SCLK_S_PLL1_TK 2 -#define RT5640_SCLK_S_RCCLK 3 - -/* PLL1 Source */ -#define RT5640_PLL1_S_MCLK 0 -#define RT5640_PLL1_S_BCLK1 1 -#define RT5640_PLL1_S_BCLK2 2 -#define RT5640_PLL1_S_BCLK3 3 - - -enum { - RT5640_AIF1, - RT5640_AIF2, - RT5640_AIF3, - RT5640_AIFS, -}; - -enum { - RT5640_U_IF1 = 0x1, - RT5640_U_IF2 = 0x2, - RT5640_U_IF3 = 0x4, -}; - -enum { - RT5640_IF_123, - RT5640_IF_132, - RT5640_IF_312, - RT5640_IF_321, - RT5640_IF_231, - RT5640_IF_213, - RT5640_IF_113, - RT5640_IF_223, - RT5640_IF_ALL, -}; - -enum { - RT5640_DMIC_DIS, - RT5640_DMIC1, - RT5640_DMIC2, -}; - -/* filter mask */ -enum { - RT5640_DA_STEREO_FILTER = 0x1, - RT5640_DA_MONO_L_FILTER = (0x1 << 1), - RT5640_DA_MONO_R_FILTER = (0x1 << 2), - RT5640_AD_STEREO_FILTER = (0x1 << 3), - RT5640_AD_MONO_L_FILTER = (0x1 << 4), - RT5640_AD_MONO_R_FILTER = (0x1 << 5), -}; - -struct rt5640_priv { - struct snd_soc_component *component; - struct regmap *regmap; - struct clk *mclk; - - int ldo1_en; /* GPIO for LDO1_EN */ - int irq; - int sysclk; - int sysclk_src; - int lrck[RT5640_AIFS]; - int bclk[RT5640_AIFS]; - int master[RT5640_AIFS]; - - int pll_src; - int pll_in; - int pll_out; - - bool hp_mute; - bool asrc_en; - - /* Jack and button detect data */ - bool ovcd_irq_enabled; - bool pressed; - bool press_reported; - int press_count; - int release_count; - int poll_count; - struct delayed_work bp_work; - struct work_struct jack_work; - struct snd_soc_jack *jack; - unsigned int jd_src; - bool jd_inverted; - unsigned int ovcd_th; - unsigned int ovcd_sf; -}; - -int rt5640_dmic_enable(struct snd_soc_component *component, - bool dmic1_data_pin, bool dmic2_data_pin); -int rt5640_sel_asrc_clk_src(struct snd_soc_component *component, - unsigned int filter_mask, unsigned int clk_src); - -void rt5640_set_ovcd_params(struct snd_soc_component *component); -void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component); -void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component); -int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio); - -#endif diff --git a/include/drivers-private/sound/soc/codecs/rt5659.h b/include/drivers-private/sound/soc/codecs/rt5659.h deleted file mode 100644 index b49fd8ba..00000000 --- a/include/drivers-private/sound/soc/codecs/rt5659.h +++ /dev/null @@ -1,1821 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver - * - * Copyright 2015 Realtek Microelectronics - * Author: Bard Liao - */ - -#ifndef __RT5659_H__ -#define __RT5659_H__ - -#include - -#define DEVICE_ID 0x6311 - -/* Info */ -#define RT5659_RESET 0x0000 -#define RT5659_VENDOR_ID 0x00fd -#define RT5659_VENDOR_ID_1 0x00fe -#define RT5659_DEVICE_ID 0x00ff -/* I/O - Output */ -#define RT5659_SPO_VOL 0x0001 -#define RT5659_HP_VOL 0x0002 -#define RT5659_LOUT 0x0003 -#define RT5659_MONO_OUT 0x0004 -#define RT5659_HPL_GAIN 0x0005 -#define RT5659_HPR_GAIN 0x0006 -#define RT5659_MONO_GAIN 0x0007 -#define RT5659_SPDIF_CTRL_1 0x0008 -#define RT5659_SPDIF_CTRL_2 0x0009 -/* I/O - Input */ -#define RT5659_CAL_BST_CTRL 0x000a -#define RT5659_IN1_IN2 0x000c -#define RT5659_IN3_IN4 0x000d -#define RT5659_INL1_INR1_VOL 0x000f -/* I/O - Speaker */ -#define RT5659_EJD_CTRL_1 0x0010 -#define RT5659_EJD_CTRL_2 0x0011 -#define RT5659_EJD_CTRL_3 0x0012 -#define RT5659_SILENCE_CTRL 0x0015 -#define RT5659_PSV_CTRL 0x0016 -/* I/O - Sidetone */ -#define RT5659_SIDETONE_CTRL 0x0018 -/* I/O - ADC/DAC/DMIC */ -#define RT5659_DAC1_DIG_VOL 0x0019 -#define RT5659_DAC2_DIG_VOL 0x001a -#define RT5659_DAC_CTRL 0x001b -#define RT5659_STO1_ADC_DIG_VOL 0x001c -#define RT5659_MONO_ADC_DIG_VOL 0x001d -#define RT5659_STO2_ADC_DIG_VOL 0x001e -#define RT5659_STO1_BOOST 0x001f -#define RT5659_MONO_BOOST 0x0020 -#define RT5659_STO2_BOOST 0x0021 -#define RT5659_HP_IMP_GAIN_1 0x0022 -#define RT5659_HP_IMP_GAIN_2 0x0023 -/* Mixer - D-D */ -#define RT5659_STO1_ADC_MIXER 0x0026 -#define RT5659_MONO_ADC_MIXER 0x0027 -#define RT5659_AD_DA_MIXER 0x0029 -#define RT5659_STO_DAC_MIXER 0x002a -#define RT5659_MONO_DAC_MIXER 0x002b -#define RT5659_DIG_MIXER 0x002c -#define RT5659_A_DAC_MUX 0x002d -#define RT5659_DIG_INF23_DATA 0x002f -/* Mixer - PDM */ -#define RT5659_PDM_OUT_CTRL 0x0031 -#define RT5659_PDM_DATA_CTRL_1 0x0032 -#define RT5659_PDM_DATA_CTRL_2 0x0033 -#define RT5659_PDM_DATA_CTRL_3 0x0034 -#define RT5659_PDM_DATA_CTRL_4 0x0035 -#define RT5659_SPDIF_CTRL 0x0036 - -/* Mixer - ADC */ -#define RT5659_REC1_GAIN 0x003a -#define RT5659_REC1_L1_MIXER 0x003b -#define RT5659_REC1_L2_MIXER 0x003c -#define RT5659_REC1_R1_MIXER 0x003d -#define RT5659_REC1_R2_MIXER 0x003e -#define RT5659_CAL_REC 0x0040 -#define RT5659_REC2_L1_MIXER 0x009b -#define RT5659_REC2_L2_MIXER 0x009c -#define RT5659_REC2_R1_MIXER 0x009d -#define RT5659_REC2_R2_MIXER 0x009e -#define RT5659_RC_CLK_CTRL 0x009f -/* Mixer - DAC */ -#define RT5659_SPK_L_MIXER 0x0046 -#define RT5659_SPK_R_MIXER 0x0047 -#define RT5659_SPO_AMP_GAIN 0x0048 -#define RT5659_ALC_BACK_GAIN 0x0049 -#define RT5659_MONOMIX_GAIN 0x004a -#define RT5659_MONOMIX_IN_GAIN 0x004b -#define RT5659_OUT_L_GAIN 0x004d -#define RT5659_OUT_L_MIXER 0x004e -#define RT5659_OUT_R_GAIN 0x004f -#define RT5659_OUT_R_MIXER 0x0050 -#define RT5659_LOUT_MIXER 0x0052 - -#define RT5659_HAPTIC_GEN_CTRL_1 0x0053 -#define RT5659_HAPTIC_GEN_CTRL_2 0x0054 -#define RT5659_HAPTIC_GEN_CTRL_3 0x0055 -#define RT5659_HAPTIC_GEN_CTRL_4 0x0056 -#define RT5659_HAPTIC_GEN_CTRL_5 0x0057 -#define RT5659_HAPTIC_GEN_CTRL_6 0x0058 -#define RT5659_HAPTIC_GEN_CTRL_7 0x0059 -#define RT5659_HAPTIC_GEN_CTRL_8 0x005a -#define RT5659_HAPTIC_GEN_CTRL_9 0x005b -#define RT5659_HAPTIC_GEN_CTRL_10 0x005c -#define RT5659_HAPTIC_GEN_CTRL_11 0x005d -#define RT5659_HAPTIC_LPF_CTRL_1 0x005e -#define RT5659_HAPTIC_LPF_CTRL_2 0x005f -#define RT5659_HAPTIC_LPF_CTRL_3 0x0060 -/* Power */ -#define RT5659_PWR_DIG_1 0x0061 -#define RT5659_PWR_DIG_2 0x0062 -#define RT5659_PWR_ANLG_1 0x0063 -#define RT5659_PWR_ANLG_2 0x0064 -#define RT5659_PWR_ANLG_3 0x0065 -#define RT5659_PWR_MIXER 0x0066 -#define RT5659_PWR_VOL 0x0067 -/* Private Register Control */ -#define RT5659_PRIV_INDEX 0x006a -#define RT5659_CLK_DET 0x006b -#define RT5659_PRIV_DATA 0x006c -/* System Clock Pre Divider Gating Control */ -#define RT5659_PRE_DIV_1 0x006e -#define RT5659_PRE_DIV_2 0x006f -/* Format - ADC/DAC */ -#define RT5659_I2S1_SDP 0x0070 -#define RT5659_I2S2_SDP 0x0071 -#define RT5659_I2S3_SDP 0x0072 -#define RT5659_ADDA_CLK_1 0x0073 -#define RT5659_ADDA_CLK_2 0x0074 -#define RT5659_DMIC_CTRL_1 0x0075 -#define RT5659_DMIC_CTRL_2 0x0076 -/* Format - TDM Control */ -#define RT5659_TDM_CTRL_1 0x0077 -#define RT5659_TDM_CTRL_2 0x0078 -#define RT5659_TDM_CTRL_3 0x0079 -#define RT5659_TDM_CTRL_4 0x007a -#define RT5659_TDM_CTRL_5 0x007b - -/* Function - Analog */ -#define RT5659_GLB_CLK 0x0080 -#define RT5659_PLL_CTRL_1 0x0081 -#define RT5659_PLL_CTRL_2 0x0082 -#define RT5659_ASRC_1 0x0083 -#define RT5659_ASRC_2 0x0084 -#define RT5659_ASRC_3 0x0085 -#define RT5659_ASRC_4 0x0086 -#define RT5659_ASRC_5 0x0087 -#define RT5659_ASRC_6 0x0088 -#define RT5659_ASRC_7 0x0089 -#define RT5659_ASRC_8 0x008a -#define RT5659_ASRC_9 0x008b -#define RT5659_ASRC_10 0x008c -#define RT5659_DEPOP_1 0x008e -#define RT5659_DEPOP_2 0x008f -#define RT5659_DEPOP_3 0x0090 -#define RT5659_HP_CHARGE_PUMP_1 0x0091 -#define RT5659_HP_CHARGE_PUMP_2 0x0092 -#define RT5659_MICBIAS_1 0x0093 -#define RT5659_MICBIAS_2 0x0094 -#define RT5659_ASRC_11 0x0097 -#define RT5659_ASRC_12 0x0098 -#define RT5659_ASRC_13 0x0099 -#define RT5659_REC_M1_M2_GAIN_CTRL 0x009a -#define RT5659_CLASSD_CTRL_1 0x00a0 -#define RT5659_CLASSD_CTRL_2 0x00a1 - -/* Function - Digital */ -#define RT5659_ADC_EQ_CTRL_1 0x00ae -#define RT5659_ADC_EQ_CTRL_2 0x00af -#define RT5659_DAC_EQ_CTRL_1 0x00b0 -#define RT5659_DAC_EQ_CTRL_2 0x00b1 -#define RT5659_DAC_EQ_CTRL_3 0x00b2 - -#define RT5659_IRQ_CTRL_1 0x00b6 -#define RT5659_IRQ_CTRL_2 0x00b7 -#define RT5659_IRQ_CTRL_3 0x00b8 -#define RT5659_IRQ_CTRL_4 0x00ba -#define RT5659_IRQ_CTRL_5 0x00bb -#define RT5659_IRQ_CTRL_6 0x00bc -#define RT5659_INT_ST_1 0x00be -#define RT5659_INT_ST_2 0x00bf -#define RT5659_GPIO_CTRL_1 0x00c0 -#define RT5659_GPIO_CTRL_2 0x00c1 -#define RT5659_GPIO_CTRL_3 0x00c2 -#define RT5659_GPIO_CTRL_4 0x00c3 -#define RT5659_GPIO_CTRL_5 0x00c4 -#define RT5659_GPIO_STA 0x00c5 -#define RT5659_SINE_GEN_CTRL_1 0x00cb -#define RT5659_SINE_GEN_CTRL_2 0x00cc -#define RT5659_SINE_GEN_CTRL_3 0x00cd -#define RT5659_HP_AMP_DET_CTRL_1 0x00d6 -#define RT5659_HP_AMP_DET_CTRL_2 0x00d7 -#define RT5659_SV_ZCD_1 0x00d9 -#define RT5659_SV_ZCD_2 0x00da -#define RT5659_IL_CMD_1 0x00db -#define RT5659_IL_CMD_2 0x00dc -#define RT5659_IL_CMD_3 0x00dd -#define RT5659_IL_CMD_4 0x00de -#define RT5659_4BTN_IL_CMD_1 0x00df -#define RT5659_4BTN_IL_CMD_2 0x00e0 -#define RT5659_4BTN_IL_CMD_3 0x00e1 -#define RT5659_PSV_IL_CMD_1 0x00e4 -#define RT5659_PSV_IL_CMD_2 0x00e5 - -#define RT5659_ADC_STO1_HP_CTRL_1 0x00ea -#define RT5659_ADC_STO1_HP_CTRL_2 0x00eb -#define RT5659_ADC_MONO_HP_CTRL_1 0x00ec -#define RT5659_ADC_MONO_HP_CTRL_2 0x00ed -#define RT5659_AJD1_CTRL 0x00f0 -#define RT5659_AJD2_AJD3_CTRL 0x00f1 -#define RT5659_JD1_THD 0x00f2 -#define RT5659_JD2_THD 0x00f3 -#define RT5659_JD3_THD 0x00f4 -#define RT5659_JD_CTRL_1 0x00f6 -#define RT5659_JD_CTRL_2 0x00f7 -#define RT5659_JD_CTRL_3 0x00f8 -#define RT5659_JD_CTRL_4 0x00f9 -/* General Control */ -#define RT5659_DIG_MISC 0x00fa -#define RT5659_DUMMY_2 0x00fb -#define RT5659_DUMMY_3 0x00fc - -#define RT5659_DAC_ADC_DIG_VOL 0x0100 -#define RT5659_BIAS_CUR_CTRL_1 0x010a -#define RT5659_BIAS_CUR_CTRL_2 0x010b -#define RT5659_BIAS_CUR_CTRL_3 0x010c -#define RT5659_BIAS_CUR_CTRL_4 0x010d -#define RT5659_BIAS_CUR_CTRL_5 0x010e -#define RT5659_BIAS_CUR_CTRL_6 0x010f -#define RT5659_BIAS_CUR_CTRL_7 0x0110 -#define RT5659_BIAS_CUR_CTRL_8 0x0111 -#define RT5659_BIAS_CUR_CTRL_9 0x0112 -#define RT5659_BIAS_CUR_CTRL_10 0x0113 -#define RT5659_MEMORY_TEST 0x0116 -#define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117 -#define RT5659_CLASSD_0 0x011a -#define RT5659_CLASSD_1 0x011b -#define RT5659_CLASSD_2 0x011c -#define RT5659_CLASSD_3 0x011d -#define RT5659_CLASSD_4 0x011e -#define RT5659_CLASSD_5 0x011f -#define RT5659_CLASSD_6 0x0120 -#define RT5659_CLASSD_7 0x0121 -#define RT5659_CLASSD_8 0x0122 -#define RT5659_CLASSD_9 0x0123 -#define RT5659_CLASSD_10 0x0124 -#define RT5659_CHARGE_PUMP_1 0x0125 -#define RT5659_CHARGE_PUMP_2 0x0126 -#define RT5659_DIG_IN_CTRL_1 0x0132 -#define RT5659_DIG_IN_CTRL_2 0x0133 -#define RT5659_PAD_DRIVING_CTRL 0x0137 -#define RT5659_SOFT_RAMP_DEPOP 0x0138 -#define RT5659_PLL 0x0139 -#define RT5659_CHOP_DAC 0x013a -#define RT5659_CHOP_ADC 0x013b -#define RT5659_CALIB_ADC_CTRL 0x013c -#define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e -#define RT5659_VOL_TEST 0x013f -#define RT5659_TEST_MODE_CTRL_1 0x0145 -#define RT5659_TEST_MODE_CTRL_2 0x0146 -#define RT5659_TEST_MODE_CTRL_3 0x0147 -#define RT5659_TEST_MODE_CTRL_4 0x0148 -#define RT5659_BASSBACK_CTRL 0x0150 -#define RT5659_MP3_PLUS_CTRL_1 0x0151 -#define RT5659_MP3_PLUS_CTRL_2 0x0152 -#define RT5659_MP3_HPF_A1 0x0153 -#define RT5659_MP3_HPF_A2 0x0154 -#define RT5659_MP3_HPF_H0 0x0155 -#define RT5659_MP3_LPF_H0 0x0156 -#define RT5659_3D_SPK_CTRL 0x0157 -#define RT5659_3D_SPK_COEF_1 0x0158 -#define RT5659_3D_SPK_COEF_2 0x0159 -#define RT5659_3D_SPK_COEF_3 0x015a -#define RT5659_3D_SPK_COEF_4 0x015b -#define RT5659_3D_SPK_COEF_5 0x015c -#define RT5659_3D_SPK_COEF_6 0x015d -#define RT5659_3D_SPK_COEF_7 0x015e -#define RT5659_STO_NG2_CTRL_1 0x0160 -#define RT5659_STO_NG2_CTRL_2 0x0161 -#define RT5659_STO_NG2_CTRL_3 0x0162 -#define RT5659_STO_NG2_CTRL_4 0x0163 -#define RT5659_STO_NG2_CTRL_5 0x0164 -#define RT5659_STO_NG2_CTRL_6 0x0165 -#define RT5659_STO_NG2_CTRL_7 0x0166 -#define RT5659_STO_NG2_CTRL_8 0x0167 -#define RT5659_MONO_NG2_CTRL_1 0x0170 -#define RT5659_MONO_NG2_CTRL_2 0x0171 -#define RT5659_MONO_NG2_CTRL_3 0x0172 -#define RT5659_MONO_NG2_CTRL_4 0x0173 -#define RT5659_MONO_NG2_CTRL_5 0x0174 -#define RT5659_MONO_NG2_CTRL_6 0x0175 -#define RT5659_MID_HP_AMP_DET 0x0190 -#define RT5659_LOW_HP_AMP_DET 0x0191 -#define RT5659_LDO_CTRL 0x0192 -#define RT5659_HP_DECROSS_CTRL_1 0x01b0 -#define RT5659_HP_DECROSS_CTRL_2 0x01b1 -#define RT5659_HP_DECROSS_CTRL_3 0x01b2 -#define RT5659_HP_DECROSS_CTRL_4 0x01b3 -#define RT5659_HP_IMP_SENS_CTRL_1 0x01c0 -#define RT5659_HP_IMP_SENS_CTRL_2 0x01c1 -#define RT5659_HP_IMP_SENS_CTRL_3 0x01c2 -#define RT5659_HP_IMP_SENS_CTRL_4 0x01c3 -#define RT5659_HP_IMP_SENS_MAP_1 0x01c7 -#define RT5659_HP_IMP_SENS_MAP_2 0x01c8 -#define RT5659_HP_IMP_SENS_MAP_3 0x01c9 -#define RT5659_HP_IMP_SENS_MAP_4 0x01ca -#define RT5659_HP_IMP_SENS_MAP_5 0x01cb -#define RT5659_HP_IMP_SENS_MAP_6 0x01cc -#define RT5659_HP_IMP_SENS_MAP_7 0x01cd -#define RT5659_HP_IMP_SENS_MAP_8 0x01ce -#define RT5659_HP_LOGIC_CTRL_1 0x01da -#define RT5659_HP_LOGIC_CTRL_2 0x01db -#define RT5659_HP_CALIB_CTRL_1 0x01de -#define RT5659_HP_CALIB_CTRL_2 0x01df -#define RT5659_HP_CALIB_CTRL_3 0x01e0 -#define RT5659_HP_CALIB_CTRL_4 0x01e1 -#define RT5659_HP_CALIB_CTRL_5 0x01e2 -#define RT5659_HP_CALIB_CTRL_6 0x01e3 -#define RT5659_HP_CALIB_CTRL_7 0x01e4 -#define RT5659_HP_CALIB_CTRL_9 0x01e6 -#define RT5659_HP_CALIB_CTRL_10 0x01e7 -#define RT5659_HP_CALIB_CTRL_11 0x01e8 -#define RT5659_HP_CALIB_STA_1 0x01ea -#define RT5659_HP_CALIB_STA_2 0x01eb -#define RT5659_HP_CALIB_STA_3 0x01ec -#define RT5659_HP_CALIB_STA_4 0x01ed -#define RT5659_HP_CALIB_STA_5 0x01ee -#define RT5659_HP_CALIB_STA_6 0x01ef -#define RT5659_HP_CALIB_STA_7 0x01f0 -#define RT5659_HP_CALIB_STA_8 0x01f1 -#define RT5659_HP_CALIB_STA_9 0x01f2 -#define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6 -#define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7 -#define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8 -#define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9 -#define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa -#define RT5659_MONO_AMP_CALIB_STA_1 0x01fb -#define RT5659_MONO_AMP_CALIB_STA_2 0x01fc -#define RT5659_MONO_AMP_CALIB_STA_3 0x01fd -#define RT5659_MONO_AMP_CALIB_STA_4 0x01fe -#define RT5659_SPK_PWR_LMT_CTRL_1 0x0200 -#define RT5659_SPK_PWR_LMT_CTRL_2 0x0201 -#define RT5659_SPK_PWR_LMT_CTRL_3 0x0202 -#define RT5659_SPK_PWR_LMT_STA_1 0x0203 -#define RT5659_SPK_PWR_LMT_STA_2 0x0204 -#define RT5659_SPK_PWR_LMT_STA_3 0x0205 -#define RT5659_SPK_PWR_LMT_STA_4 0x0206 -#define RT5659_SPK_PWR_LMT_STA_5 0x0207 -#define RT5659_SPK_PWR_LMT_STA_6 0x0208 -#define RT5659_FLEX_SPK_BST_CTRL_1 0x0256 -#define RT5659_FLEX_SPK_BST_CTRL_2 0x0257 -#define RT5659_FLEX_SPK_BST_CTRL_3 0x0258 -#define RT5659_FLEX_SPK_BST_CTRL_4 0x0259 -#define RT5659_SPK_EX_LMT_CTRL_1 0x025a -#define RT5659_SPK_EX_LMT_CTRL_2 0x025b -#define RT5659_SPK_EX_LMT_CTRL_3 0x025c -#define RT5659_SPK_EX_LMT_CTRL_4 0x025d -#define RT5659_SPK_EX_LMT_CTRL_5 0x025e -#define RT5659_SPK_EX_LMT_CTRL_6 0x025f -#define RT5659_SPK_EX_LMT_CTRL_7 0x0260 -#define RT5659_ADJ_HPF_CTRL_1 0x0261 -#define RT5659_ADJ_HPF_CTRL_2 0x0262 -#define RT5659_SPK_DC_CAILB_CTRL_1 0x0265 -#define RT5659_SPK_DC_CAILB_CTRL_2 0x0266 -#define RT5659_SPK_DC_CAILB_CTRL_3 0x0267 -#define RT5659_SPK_DC_CAILB_CTRL_4 0x0268 -#define RT5659_SPK_DC_CAILB_CTRL_5 0x0269 -#define RT5659_SPK_DC_CAILB_STA_1 0x026a -#define RT5659_SPK_DC_CAILB_STA_2 0x026b -#define RT5659_SPK_DC_CAILB_STA_3 0x026c -#define RT5659_SPK_DC_CAILB_STA_4 0x026d -#define RT5659_SPK_DC_CAILB_STA_5 0x026e -#define RT5659_SPK_DC_CAILB_STA_6 0x026f -#define RT5659_SPK_DC_CAILB_STA_7 0x0270 -#define RT5659_SPK_DC_CAILB_STA_8 0x0271 -#define RT5659_SPK_DC_CAILB_STA_9 0x0272 -#define RT5659_SPK_DC_CAILB_STA_10 0x0273 -#define RT5659_SPK_VDD_STA_1 0x0280 -#define RT5659_SPK_VDD_STA_2 0x0281 -#define RT5659_SPK_DC_DET_CTRL_1 0x0282 -#define RT5659_SPK_DC_DET_CTRL_2 0x0283 -#define RT5659_SPK_DC_DET_CTRL_3 0x0284 -#define RT5659_PURE_DC_DET_CTRL_1 0x0290 -#define RT5659_PURE_DC_DET_CTRL_2 0x0291 -#define RT5659_DUMMY_4 0x02fa -#define RT5659_DUMMY_5 0x02fb -#define RT5659_DUMMY_6 0x02fc -#define RT5659_DRC1_CTRL_1 0x0300 -#define RT5659_DRC1_CTRL_2 0x0301 -#define RT5659_DRC1_CTRL_3 0x0302 -#define RT5659_DRC1_CTRL_4 0x0303 -#define RT5659_DRC1_CTRL_5 0x0304 -#define RT5659_DRC1_CTRL_6 0x0305 -#define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306 -#define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307 -#define RT5659_DRC2_CTRL_1 0x0308 -#define RT5659_DRC2_CTRL_2 0x0309 -#define RT5659_DRC2_CTRL_3 0x030a -#define RT5659_DRC2_CTRL_4 0x030b -#define RT5659_DRC2_CTRL_5 0x030c -#define RT5659_DRC2_CTRL_6 0x030d -#define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e -#define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f -#define RT5659_DRC1_PRIV_1 0x0310 -#define RT5659_DRC1_PRIV_2 0x0311 -#define RT5659_DRC1_PRIV_3 0x0312 -#define RT5659_DRC1_PRIV_4 0x0313 -#define RT5659_DRC1_PRIV_5 0x0314 -#define RT5659_DRC1_PRIV_6 0x0315 -#define RT5659_DRC1_PRIV_7 0x0316 -#define RT5659_DRC2_PRIV_1 0x0317 -#define RT5659_DRC2_PRIV_2 0x0318 -#define RT5659_DRC2_PRIV_3 0x0319 -#define RT5659_DRC2_PRIV_4 0x031a -#define RT5659_DRC2_PRIV_5 0x031b -#define RT5659_DRC2_PRIV_6 0x031c -#define RT5659_DRC2_PRIV_7 0x031d -#define RT5659_MULTI_DRC_CTRL 0x0320 -#define RT5659_CROSS_OVER_1 0x0321 -#define RT5659_CROSS_OVER_2 0x0322 -#define RT5659_CROSS_OVER_3 0x0323 -#define RT5659_CROSS_OVER_4 0x0324 -#define RT5659_CROSS_OVER_5 0x0325 -#define RT5659_CROSS_OVER_6 0x0326 -#define RT5659_CROSS_OVER_7 0x0327 -#define RT5659_CROSS_OVER_8 0x0328 -#define RT5659_CROSS_OVER_9 0x0329 -#define RT5659_CROSS_OVER_10 0x032a -#define RT5659_ALC_PGA_CTRL_1 0x0330 -#define RT5659_ALC_PGA_CTRL_2 0x0331 -#define RT5659_ALC_PGA_CTRL_3 0x0332 -#define RT5659_ALC_PGA_CTRL_4 0x0333 -#define RT5659_ALC_PGA_CTRL_5 0x0334 -#define RT5659_ALC_PGA_CTRL_6 0x0335 -#define RT5659_ALC_PGA_CTRL_7 0x0336 -#define RT5659_ALC_PGA_CTRL_8 0x0337 -#define RT5659_ALC_PGA_STA_1 0x0338 -#define RT5659_ALC_PGA_STA_2 0x0339 -#define RT5659_ALC_PGA_STA_3 0x033a -#define RT5659_DAC_L_EQ_PRE_VOL 0x0340 -#define RT5659_DAC_R_EQ_PRE_VOL 0x0341 -#define RT5659_DAC_L_EQ_POST_VOL 0x0342 -#define RT5659_DAC_R_EQ_POST_VOL 0x0343 -#define RT5659_DAC_L_EQ_LPF1_A1 0x0344 -#define RT5659_DAC_L_EQ_LPF1_H0 0x0345 -#define RT5659_DAC_R_EQ_LPF1_A1 0x0346 -#define RT5659_DAC_R_EQ_LPF1_H0 0x0347 -#define RT5659_DAC_L_EQ_BPF2_A1 0x0348 -#define RT5659_DAC_L_EQ_BPF2_A2 0x0349 -#define RT5659_DAC_L_EQ_BPF2_H0 0x034a -#define RT5659_DAC_R_EQ_BPF2_A1 0x034b -#define RT5659_DAC_R_EQ_BPF2_A2 0x034c -#define RT5659_DAC_R_EQ_BPF2_H0 0x034d -#define RT5659_DAC_L_EQ_BPF3_A1 0x034e -#define RT5659_DAC_L_EQ_BPF3_A2 0x034f -#define RT5659_DAC_L_EQ_BPF3_H0 0x0350 -#define RT5659_DAC_R_EQ_BPF3_A1 0x0351 -#define RT5659_DAC_R_EQ_BPF3_A2 0x0352 -#define RT5659_DAC_R_EQ_BPF3_H0 0x0353 -#define RT5659_DAC_L_EQ_BPF4_A1 0x0354 -#define RT5659_DAC_L_EQ_BPF4_A2 0x0355 -#define RT5659_DAC_L_EQ_BPF4_H0 0x0356 -#define RT5659_DAC_R_EQ_BPF4_A1 0x0357 -#define RT5659_DAC_R_EQ_BPF4_A2 0x0358 -#define RT5659_DAC_R_EQ_BPF4_H0 0x0359 -#define RT5659_DAC_L_EQ_HPF1_A1 0x035a -#define RT5659_DAC_L_EQ_HPF1_H0 0x035b -#define RT5659_DAC_R_EQ_HPF1_A1 0x035c -#define RT5659_DAC_R_EQ_HPF1_H0 0x035d -#define RT5659_DAC_L_EQ_HPF2_A1 0x035e -#define RT5659_DAC_L_EQ_HPF2_A2 0x035f -#define RT5659_DAC_L_EQ_HPF2_H0 0x0360 -#define RT5659_DAC_R_EQ_HPF2_A1 0x0361 -#define RT5659_DAC_R_EQ_HPF2_A2 0x0362 -#define RT5659_DAC_R_EQ_HPF2_H0 0x0363 -#define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364 -#define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365 -#define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366 -#define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367 -#define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368 -#define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369 -#define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a -#define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b -#define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c -#define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d -#define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e -#define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f -#define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370 -#define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371 -#define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372 -#define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373 -#define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374 -#define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375 -#define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376 -#define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377 -#define RT5659_ADC_L_EQ_LPF1_A1 0x03d0 -#define RT5659_ADC_R_EQ_LPF1_A1 0x03d1 -#define RT5659_ADC_L_EQ_LPF1_H0 0x03d2 -#define RT5659_ADC_R_EQ_LPF1_H0 0x03d3 -#define RT5659_ADC_L_EQ_BPF1_A1 0x03d4 -#define RT5659_ADC_R_EQ_BPF1_A1 0x03d5 -#define RT5659_ADC_L_EQ_BPF1_A2 0x03d6 -#define RT5659_ADC_R_EQ_BPF1_A2 0x03d7 -#define RT5659_ADC_L_EQ_BPF1_H0 0x03d8 -#define RT5659_ADC_R_EQ_BPF1_H0 0x03d9 -#define RT5659_ADC_L_EQ_BPF2_A1 0x03da -#define RT5659_ADC_R_EQ_BPF2_A1 0x03db -#define RT5659_ADC_L_EQ_BPF2_A2 0x03dc -#define RT5659_ADC_R_EQ_BPF2_A2 0x03dd -#define RT5659_ADC_L_EQ_BPF2_H0 0x03de -#define RT5659_ADC_R_EQ_BPF2_H0 0x03df -#define RT5659_ADC_L_EQ_BPF3_A1 0x03e0 -#define RT5659_ADC_R_EQ_BPF3_A1 0x03e1 -#define RT5659_ADC_L_EQ_BPF3_A2 0x03e2 -#define RT5659_ADC_R_EQ_BPF3_A2 0x03e3 -#define RT5659_ADC_L_EQ_BPF3_H0 0x03e4 -#define RT5659_ADC_R_EQ_BPF3_H0 0x03e5 -#define RT5659_ADC_L_EQ_BPF4_A1 0x03e6 -#define RT5659_ADC_R_EQ_BPF4_A1 0x03e7 -#define RT5659_ADC_L_EQ_BPF4_A2 0x03e8 -#define RT5659_ADC_R_EQ_BPF4_A2 0x03e9 -#define RT5659_ADC_L_EQ_BPF4_H0 0x03ea -#define RT5659_ADC_R_EQ_BPF4_H0 0x03eb -#define RT5659_ADC_L_EQ_HPF1_A1 0x03ec -#define RT5659_ADC_R_EQ_HPF1_A1 0x03ed -#define RT5659_ADC_L_EQ_HPF1_H0 0x03ee -#define RT5659_ADC_R_EQ_HPF1_H0 0x03ef -#define RT5659_ADC_L_EQ_PRE_VOL 0x03f0 -#define RT5659_ADC_R_EQ_PRE_VOL 0x03f1 -#define RT5659_ADC_L_EQ_POST_VOL 0x03f2 -#define RT5659_ADC_R_EQ_POST_VOL 0x03f3 - - - -/* global definition */ -#define RT5659_L_MUTE (0x1 << 15) -#define RT5659_L_MUTE_SFT 15 -#define RT5659_VOL_L_MUTE (0x1 << 14) -#define RT5659_VOL_L_SFT 14 -#define RT5659_R_MUTE (0x1 << 7) -#define RT5659_R_MUTE_SFT 7 -#define RT5659_VOL_R_MUTE (0x1 << 6) -#define RT5659_VOL_R_SFT 6 -#define RT5659_L_VOL_MASK (0x3f << 8) -#define RT5659_L_VOL_SFT 8 -#define RT5659_R_VOL_MASK (0x3f) -#define RT5659_R_VOL_SFT 0 - -/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ -#define RT5659_G_HP (0x1f << 8) -#define RT5659_G_HP_SFT 8 -#define RT5659_G_STO_DA_DMIX (0x1f) -#define RT5659_G_STO_DA_SFT 0 - -/* IN1/IN2 Control (0x000c) */ -#define RT5659_IN1_DF_MASK (0x1 << 15) -#define RT5659_IN1_DF 15 -#define RT5659_BST1_MASK (0x7f << 8) -#define RT5659_BST1_SFT 8 -#define RT5659_BST2_MASK (0x7f) -#define RT5659_BST2_SFT 0 - -/* IN3/IN4 Control (0x000d) */ -#define RT5659_IN3_DF_MASK (0x1 << 15) -#define RT5659_IN3_DF 15 -#define RT5659_BST3_MASK (0x7f << 8) -#define RT5659_BST3_SFT 8 -#define RT5659_IN4_DF_MASK (0x1 << 7) -#define RT5659_IN4_DF 7 -#define RT5659_BST4_MASK (0x7f) -#define RT5659_BST4_SFT 0 - -/* INL and INR Volume Control (0x000f) */ -#define RT5659_INL_VOL_MASK (0x1f << 8) -#define RT5659_INL_VOL_SFT 8 -#define RT5659_INR_VOL_MASK (0x1f) -#define RT5659_INR_VOL_SFT 0 - -/* Embeeded Jack and Type Detection Control 1 (0x0010) */ -#define RT5659_EMB_JD_EN (0x1 << 15) -#define RT5659_EMB_JD_EN_SFT 15 -#define RT5659_JD_MODE (0x1 << 13) -#define RT5659_JD_MODE_SFT 13 -#define RT5659_EXT_JD_EN (0x1 << 11) -#define RT5659_EXT_JD_EN_SFT 11 -#define RT5659_EXT_JD_DIG (0x1 << 9) - -/* Embeeded Jack and Type Detection Control 2 (0x0011) */ -#define RT5659_EXT_JD_SRC (0x7 << 4) -#define RT5659_EXT_JD_SRC_SFT 4 -#define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) -#define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) -#define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4) -#define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4) -#define RT5659_EXT_JD_SRC_JD2 (0x4 << 4) -#define RT5659_EXT_JD_SRC_JD3 (0x5 << 4) -#define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4) - -/* Slience Detection Control (0x0015) */ -#define RT5659_SIL_DET_MASK (0x1 << 15) -#define RT5659_SIL_DET_DIS (0x0 << 15) -#define RT5659_SIL_DET_EN (0x1 << 15) - -/* Sidetone Control (0x0018) */ -#define RT5659_ST_SEL_MASK (0x7 << 9) -#define RT5659_ST_SEL_SFT 9 -#define RT5659_ST_EN (0x1 << 6) -#define RT5659_ST_EN_SFT 6 - -/* DAC1 Digital Volume (0x0019) */ -#define RT5659_DAC_L1_VOL_MASK (0xff << 8) -#define RT5659_DAC_L1_VOL_SFT 8 -#define RT5659_DAC_R1_VOL_MASK (0xff) -#define RT5659_DAC_R1_VOL_SFT 0 - -/* DAC2 Digital Volume (0x001a) */ -#define RT5659_DAC_L2_VOL_MASK (0xff << 8) -#define RT5659_DAC_L2_VOL_SFT 8 -#define RT5659_DAC_R2_VOL_MASK (0xff) -#define RT5659_DAC_R2_VOL_SFT 0 - -/* DAC2 Control (0x001b) */ -#define RT5659_M_DAC2_L_VOL (0x1 << 13) -#define RT5659_M_DAC2_L_VOL_SFT 13 -#define RT5659_M_DAC2_R_VOL (0x1 << 12) -#define RT5659_M_DAC2_R_VOL_SFT 12 -#define RT5659_DAC_L2_SEL_MASK (0x7 << 4) -#define RT5659_DAC_L2_SEL_SFT 4 -#define RT5659_DAC_R2_SEL_MASK (0x7 << 0) -#define RT5659_DAC_R2_SEL_SFT 0 - -/* ADC Digital Volume Control (0x001c) */ -#define RT5659_ADC_L_VOL_MASK (0x7f << 8) -#define RT5659_ADC_L_VOL_SFT 8 -#define RT5659_ADC_R_VOL_MASK (0x7f) -#define RT5659_ADC_R_VOL_SFT 0 - -/* Mono ADC Digital Volume Control (0x001d) */ -#define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8) -#define RT5659_MONO_ADC_L_VOL_SFT 8 -#define RT5659_MONO_ADC_R_VOL_MASK (0x7f) -#define RT5659_MONO_ADC_R_VOL_SFT 0 - -/* Stereo1 ADC Boost Gain Control (0x001f) */ -#define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14) -#define RT5659_STO1_ADC_L_BST_SFT 14 -#define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12) -#define RT5659_STO1_ADC_R_BST_SFT 12 - -/* Mono ADC Boost Gain Control (0x0020) */ -#define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14) -#define RT5659_MONO_ADC_L_BST_SFT 14 -#define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12) -#define RT5659_MONO_ADC_R_BST_SFT 12 - -/* Stereo1 ADC Boost Gain Control (0x001f) */ -#define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14) -#define RT5659_STO2_ADC_L_BST_SFT 14 -#define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12) -#define RT5659_STO2_ADC_R_BST_SFT 12 - -/* Stereo ADC Mixer Control (0x0026) */ -#define RT5659_M_STO1_ADC_L1 (0x1 << 15) -#define RT5659_M_STO1_ADC_L1_SFT 15 -#define RT5659_M_STO1_ADC_L2 (0x1 << 14) -#define RT5659_M_STO1_ADC_L2_SFT 14 -#define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13) -#define RT5659_STO1_ADC1_SRC_SFT 13 -#define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13) -#define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13) -#define RT5659_STO1_ADC_SRC_MASK (0x1 << 12) -#define RT5659_STO1_ADC_SRC_SFT 12 -#define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12) -#define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12) -#define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11) -#define RT5659_STO1_ADC2_SRC_SFT 11 -#define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8) -#define RT5659_STO1_DMIC_SRC_SFT 8 -#define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8) -#define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8) -#define RT5659_M_STO1_ADC_R1 (0x1 << 6) -#define RT5659_M_STO1_ADC_R1_SFT 6 -#define RT5659_M_STO1_ADC_R2 (0x1 << 5) -#define RT5659_M_STO1_ADC_R2_SFT 5 - -/* Mono1 ADC Mixer control (0x0027) */ -#define RT5659_M_MONO_ADC_L1 (0x1 << 15) -#define RT5659_M_MONO_ADC_L1_SFT 15 -#define RT5659_M_MONO_ADC_L2 (0x1 << 14) -#define RT5659_M_MONO_ADC_L2_SFT 14 -#define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12) -#define RT5659_MONO_ADC_L2_SRC_SFT 12 -#define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11) -#define RT5659_MONO_ADC_L1_SRC_SFT 11 -#define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9) -#define RT5659_MONO_ADC_L_SRC_SFT 9 -#define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8) -#define RT5659_MONO_DMIC_L_SRC_SFT 8 -#define RT5659_M_MONO_ADC_R1 (0x1 << 7) -#define RT5659_M_MONO_ADC_R1_SFT 7 -#define RT5659_M_MONO_ADC_R2 (0x1 << 6) -#define RT5659_M_MONO_ADC_R2_SFT 6 -#define RT5659_STO2_ADC_SRC_MASK (0x1 << 5) -#define RT5659_STO2_ADC_SRC_SFT 5 -#define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4) -#define RT5659_MONO_ADC_R2_SRC_SFT 4 -#define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3) -#define RT5659_MONO_ADC_R1_SRC_SFT 3 -#define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1) -#define RT5659_MONO_ADC_R_SRC_SFT 1 -#define RT5659_MONO_DMIC_R_SRC_MASK 0x1 -#define RT5659_MONO_DMIC_R_SRC_SFT 0 - -/* ADC Mixer to DAC Mixer Control (0x0029) */ -#define RT5659_M_ADCMIX_L (0x1 << 15) -#define RT5659_M_ADCMIX_L_SFT 15 -#define RT5659_M_DAC1_L (0x1 << 14) -#define RT5659_M_DAC1_L_SFT 14 -#define RT5659_DAC1_R_SEL_MASK (0x3 << 10) -#define RT5659_DAC1_R_SEL_SFT 10 -#define RT5659_DAC1_R_SEL_IF1 (0x0 << 10) -#define RT5659_DAC1_R_SEL_IF2 (0x1 << 10) -#define RT5659_DAC1_R_SEL_IF3 (0x2 << 10) -#define RT5659_DAC1_L_SEL_MASK (0x3 << 8) -#define RT5659_DAC1_L_SEL_SFT 8 -#define RT5659_DAC1_L_SEL_IF1 (0x0 << 8) -#define RT5659_DAC1_L_SEL_IF2 (0x1 << 8) -#define RT5659_DAC1_L_SEL_IF3 (0x2 << 8) -#define RT5659_M_ADCMIX_R (0x1 << 7) -#define RT5659_M_ADCMIX_R_SFT 7 -#define RT5659_M_DAC1_R (0x1 << 6) -#define RT5659_M_DAC1_R_SFT 6 - -/* Stereo DAC Mixer Control (0x002a) */ -#define RT5659_M_DAC_L1_STO_L (0x1 << 15) -#define RT5659_M_DAC_L1_STO_L_SFT 15 -#define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14) -#define RT5659_G_DAC_L1_STO_L_SFT 14 -#define RT5659_M_DAC_R1_STO_L (0x1 << 13) -#define RT5659_M_DAC_R1_STO_L_SFT 13 -#define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12) -#define RT5659_G_DAC_R1_STO_L_SFT 12 -#define RT5659_M_DAC_L2_STO_L (0x1 << 11) -#define RT5659_M_DAC_L2_STO_L_SFT 11 -#define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10) -#define RT5659_G_DAC_L2_STO_L_SFT 10 -#define RT5659_M_DAC_R2_STO_L (0x1 << 9) -#define RT5659_M_DAC_R2_STO_L_SFT 9 -#define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8) -#define RT5659_G_DAC_R2_STO_L_SFT 8 -#define RT5659_M_DAC_L1_STO_R (0x1 << 7) -#define RT5659_M_DAC_L1_STO_R_SFT 7 -#define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6) -#define RT5659_G_DAC_L1_STO_R_SFT 6 -#define RT5659_M_DAC_R1_STO_R (0x1 << 5) -#define RT5659_M_DAC_R1_STO_R_SFT 5 -#define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4) -#define RT5659_G_DAC_R1_STO_R_SFT 4 -#define RT5659_M_DAC_L2_STO_R (0x1 << 3) -#define RT5659_M_DAC_L2_STO_R_SFT 3 -#define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2) -#define RT5659_G_DAC_L2_STO_R_SFT 2 -#define RT5659_M_DAC_R2_STO_R (0x1 << 1) -#define RT5659_M_DAC_R2_STO_R_SFT 1 -#define RT5659_G_DAC_R2_STO_R_MASK (0x1) -#define RT5659_G_DAC_R2_STO_R_SFT 0 - -/* Mono DAC Mixer Control (0x002b) */ -#define RT5659_M_DAC_L1_MONO_L (0x1 << 15) -#define RT5659_M_DAC_L1_MONO_L_SFT 15 -#define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14) -#define RT5659_G_DAC_L1_MONO_L_SFT 14 -#define RT5659_M_DAC_R1_MONO_L (0x1 << 13) -#define RT5659_M_DAC_R1_MONO_L_SFT 13 -#define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12) -#define RT5659_G_DAC_R1_MONO_L_SFT 12 -#define RT5659_M_DAC_L2_MONO_L (0x1 << 11) -#define RT5659_M_DAC_L2_MONO_L_SFT 11 -#define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10) -#define RT5659_G_DAC_L2_MONO_L_SFT 10 -#define RT5659_M_DAC_R2_MONO_L (0x1 << 9) -#define RT5659_M_DAC_R2_MONO_L_SFT 9 -#define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8) -#define RT5659_G_DAC_R2_MONO_L_SFT 8 -#define RT5659_M_DAC_L1_MONO_R (0x1 << 7) -#define RT5659_M_DAC_L1_MONO_R_SFT 7 -#define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6) -#define RT5659_G_DAC_L1_MONO_R_SFT 6 -#define RT5659_M_DAC_R1_MONO_R (0x1 << 5) -#define RT5659_M_DAC_R1_MONO_R_SFT 5 -#define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4) -#define RT5659_G_DAC_R1_MONO_R_SFT 4 -#define RT5659_M_DAC_L2_MONO_R (0x1 << 3) -#define RT5659_M_DAC_L2_MONO_R_SFT 3 -#define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2) -#define RT5659_G_DAC_L2_MONO_R_SFT 2 -#define RT5659_M_DAC_R2_MONO_R (0x1 << 1) -#define RT5659_M_DAC_R2_MONO_R_SFT 1 -#define RT5659_G_DAC_R2_MONO_R_MASK (0x1) -#define RT5659_G_DAC_R2_MONO_R_SFT 0 - -/* Digital Mixer Control (0x002c) */ -#define RT5659_M_DAC_MIX_L (0x1 << 7) -#define RT5659_M_DAC_MIX_L_SFT 7 -#define RT5659_DAC_MIX_L_MASK (0x1 << 6) -#define RT5659_DAC_MIX_L_SFT 6 -#define RT5659_M_DAC_MIX_R (0x1 << 5) -#define RT5659_M_DAC_MIX_R_SFT 5 -#define RT5659_DAC_MIX_R_MASK (0x1 << 4) -#define RT5659_DAC_MIX_R_SFT 4 - -/* Analog DAC Input Source Control (0x002d) */ -#define RT5659_A_DACL1_SEL (0x1 << 3) -#define RT5659_A_DACL1_SFT 3 -#define RT5659_A_DACR1_SEL (0x1 << 2) -#define RT5659_A_DACR1_SFT 2 -#define RT5659_A_DACL2_SEL (0x1 << 1) -#define RT5659_A_DACL2_SFT 1 -#define RT5659_A_DACR2_SEL (0x1 << 0) -#define RT5659_A_DACR2_SFT 0 - -/* Digital Interface Data Control (0x002f) */ -#define RT5659_IF2_ADC3_IN_MASK (0x3 << 14) -#define RT5659_IF2_ADC3_IN_SFT 14 -#define RT5659_IF2_ADC_IN_MASK (0x3 << 12) -#define RT5659_IF2_ADC_IN_SFT 12 -#define RT5659_IF2_DAC_SEL_MASK (0x3 << 10) -#define RT5659_IF2_DAC_SEL_SFT 10 -#define RT5659_IF2_ADC_SEL_MASK (0x3 << 8) -#define RT5659_IF2_ADC_SEL_SFT 8 -#define RT5659_IF3_DAC_SEL_MASK (0x3 << 6) -#define RT5659_IF3_DAC_SEL_SFT 6 -#define RT5659_IF3_ADC_SEL_MASK (0x3 << 4) -#define RT5659_IF3_ADC_SEL_SFT 4 -#define RT5659_IF3_ADC_IN_MASK (0x3 << 0) -#define RT5659_IF3_ADC_IN_SFT 0 - -/* PDM Output Control (0x0031) */ -#define RT5659_PDM1_L_MASK (0x1 << 15) -#define RT5659_PDM1_L_SFT 15 -#define RT5659_M_PDM1_L (0x1 << 14) -#define RT5659_M_PDM1_L_SFT 14 -#define RT5659_PDM1_R_MASK (0x1 << 13) -#define RT5659_PDM1_R_SFT 13 -#define RT5659_M_PDM1_R (0x1 << 12) -#define RT5659_M_PDM1_R_SFT 12 -#define RT5659_PDM2_BUSY (0x1 << 7) -#define RT5659_PDM1_BUSY (0x1 << 6) -#define RT5659_PDM_PATTERN (0x1 << 5) -#define RT5659_PDM_GAIN (0x1 << 4) -#define RT5659_PDM_DIV_MASK (0x3) - -/*S/PDIF Output Control (0x0036) */ -#define RT5659_SPDIF_SEL_MASK (0x3 << 0) -#define RT5659_SPDIF_SEL_SFT 0 - -/* REC Left Mixer Control 2 (0x003c) */ -#define RT5659_M_BST1_RM1_L (0x1 << 5) -#define RT5659_M_BST1_RM1_L_SFT 5 -#define RT5659_M_BST2_RM1_L (0x1 << 4) -#define RT5659_M_BST2_RM1_L_SFT 4 -#define RT5659_M_BST3_RM1_L (0x1 << 3) -#define RT5659_M_BST3_RM1_L_SFT 3 -#define RT5659_M_BST4_RM1_L (0x1 << 2) -#define RT5659_M_BST4_RM1_L_SFT 2 -#define RT5659_M_INL_RM1_L (0x1 << 1) -#define RT5659_M_INL_RM1_L_SFT 1 -#define RT5659_M_SPKVOLL_RM1_L (0x1) -#define RT5659_M_SPKVOLL_RM1_L_SFT 0 - -/* REC Right Mixer Control 2 (0x003e) */ -#define RT5659_M_BST1_RM1_R (0x1 << 5) -#define RT5659_M_BST1_RM1_R_SFT 5 -#define RT5659_M_BST2_RM1_R (0x1 << 4) -#define RT5659_M_BST2_RM1_R_SFT 4 -#define RT5659_M_BST3_RM1_R (0x1 << 3) -#define RT5659_M_BST3_RM1_R_SFT 3 -#define RT5659_M_BST4_RM1_R (0x1 << 2) -#define RT5659_M_BST4_RM1_R_SFT 2 -#define RT5659_M_INR_RM1_R (0x1 << 1) -#define RT5659_M_INR_RM1_R_SFT 1 -#define RT5659_M_HPOVOLR_RM1_R (0x1) -#define RT5659_M_HPOVOLR_RM1_R_SFT 0 - -/* SPK Left Mixer Control (0x0046) */ -#define RT5659_M_BST3_SM_L (0x1 << 4) -#define RT5659_M_BST3_SM_L_SFT 4 -#define RT5659_M_IN_R_SM_L (0x1 << 3) -#define RT5659_M_IN_R_SM_L_SFT 3 -#define RT5659_M_IN_L_SM_L (0x1 << 2) -#define RT5659_M_IN_L_SM_L_SFT 2 -#define RT5659_M_BST1_SM_L (0x1 << 1) -#define RT5659_M_BST1_SM_L_SFT 1 -#define RT5659_M_DAC_L2_SM_L (0x1) -#define RT5659_M_DAC_L2_SM_L_SFT 0 - -/* SPK Right Mixer Control (0x0047) */ -#define RT5659_M_BST3_SM_R (0x1 << 4) -#define RT5659_M_BST3_SM_R_SFT 4 -#define RT5659_M_IN_R_SM_R (0x1 << 3) -#define RT5659_M_IN_R_SM_R_SFT 3 -#define RT5659_M_IN_L_SM_R (0x1 << 2) -#define RT5659_M_IN_L_SM_R_SFT 2 -#define RT5659_M_BST4_SM_R (0x1 << 1) -#define RT5659_M_BST4_SM_R_SFT 1 -#define RT5659_M_DAC_R2_SM_R (0x1) -#define RT5659_M_DAC_R2_SM_R_SFT 0 - -/* SPO Amp Input and Gain Control (0x0048) */ -#define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13) -#define RT5659_M_DAC_L2_SPKOMIX_SFT 13 -#define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12) -#define RT5659_M_SPKVOLL_SPKOMIX_SFT 12 -#define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9) -#define RT5659_M_DAC_R2_SPKOMIX_SFT 9 -#define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8) -#define RT5659_M_SPKVOLR_SPKOMIX_SFT 8 - -/* MONOMIX Input and Gain Control (0x004b) */ -#define RT5659_M_MONOVOL_MA (0x1 << 9) -#define RT5659_M_MONOVOL_MA_SFT 9 -#define RT5659_M_DAC_L2_MA (0x1 << 8) -#define RT5659_M_DAC_L2_MA_SFT 8 -#define RT5659_M_BST3_MM (0x1 << 4) -#define RT5659_M_BST3_MM_SFT 4 -#define RT5659_M_BST2_MM (0x1 << 3) -#define RT5659_M_BST2_MM_SFT 3 -#define RT5659_M_BST1_MM (0x1 << 2) -#define RT5659_M_BST1_MM_SFT 2 -#define RT5659_M_DAC_R2_MM (0x1 << 1) -#define RT5659_M_DAC_R2_MM_SFT 1 -#define RT5659_M_DAC_L2_MM (0x1) -#define RT5659_M_DAC_L2_MM_SFT 0 - -/* Output Left Mixer Control 1 (0x004d) */ -#define RT5659_G_BST3_OM_L_MASK (0x7 << 12) -#define RT5659_G_BST3_OM_L_SFT 12 -#define RT5659_G_BST2_OM_L_MASK (0x7 << 9) -#define RT5659_G_BST2_OM_L_SFT 9 -#define RT5659_G_BST1_OM_L_MASK (0x7 << 6) -#define RT5659_G_BST1_OM_L_SFT 6 -#define RT5659_G_IN_L_OM_L_MASK (0x7 << 3) -#define RT5659_G_IN_L_OM_L_SFT 3 -#define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0) -#define RT5659_G_DAC_L2_OM_L_SFT 0 - -/* Output Left Mixer Input Control (0x004e) */ -#define RT5659_M_BST3_OM_L (0x1 << 4) -#define RT5659_M_BST3_OM_L_SFT 4 -#define RT5659_M_BST2_OM_L (0x1 << 3) -#define RT5659_M_BST2_OM_L_SFT 3 -#define RT5659_M_BST1_OM_L (0x1 << 2) -#define RT5659_M_BST1_OM_L_SFT 2 -#define RT5659_M_IN_L_OM_L (0x1 << 1) -#define RT5659_M_IN_L_OM_L_SFT 1 -#define RT5659_M_DAC_L2_OM_L (0x1) -#define RT5659_M_DAC_L2_OM_L_SFT 0 - -/* Output Right Mixer Input Control (0x0050) */ -#define RT5659_M_BST4_OM_R (0x1 << 4) -#define RT5659_M_BST4_OM_R_SFT 4 -#define RT5659_M_BST3_OM_R (0x1 << 3) -#define RT5659_M_BST3_OM_R_SFT 3 -#define RT5659_M_BST2_OM_R (0x1 << 2) -#define RT5659_M_BST2_OM_R_SFT 2 -#define RT5659_M_IN_R_OM_R (0x1 << 1) -#define RT5659_M_IN_R_OM_R_SFT 1 -#define RT5659_M_DAC_R2_OM_R (0x1) -#define RT5659_M_DAC_R2_OM_R_SFT 0 - -/* LOUT Mixer Control (0x0052) */ -#define RT5659_M_DAC_L2_LM (0x1 << 15) -#define RT5659_M_DAC_L2_LM_SFT 15 -#define RT5659_M_DAC_R2_LM (0x1 << 14) -#define RT5659_M_DAC_R2_LM_SFT 14 -#define RT5659_M_OV_L_LM (0x1 << 13) -#define RT5659_M_OV_L_LM_SFT 13 -#define RT5659_M_OV_R_LM (0x1 << 12) -#define RT5659_M_OV_R_LM_SFT 12 - -/* Power Management for Digital 1 (0x0061) */ -#define RT5659_PWR_I2S1 (0x1 << 15) -#define RT5659_PWR_I2S1_BIT 15 -#define RT5659_PWR_I2S2 (0x1 << 14) -#define RT5659_PWR_I2S2_BIT 14 -#define RT5659_PWR_I2S3 (0x1 << 13) -#define RT5659_PWR_I2S3_BIT 13 -#define RT5659_PWR_SPDIF (0x1 << 12) -#define RT5659_PWR_SPDIF_BIT 12 -#define RT5659_PWR_DAC_L1 (0x1 << 11) -#define RT5659_PWR_DAC_L1_BIT 11 -#define RT5659_PWR_DAC_R1 (0x1 << 10) -#define RT5659_PWR_DAC_R1_BIT 10 -#define RT5659_PWR_DAC_L2 (0x1 << 9) -#define RT5659_PWR_DAC_L2_BIT 9 -#define RT5659_PWR_DAC_R2 (0x1 << 8) -#define RT5659_PWR_DAC_R2_BIT 8 -#define RT5659_PWR_LDO (0x1 << 7) -#define RT5659_PWR_LDO_BIT 7 -#define RT5659_PWR_ADC_L1 (0x1 << 4) -#define RT5659_PWR_ADC_L1_BIT 4 -#define RT5659_PWR_ADC_R1 (0x1 << 3) -#define RT5659_PWR_ADC_R1_BIT 3 -#define RT5659_PWR_ADC_L2 (0x1 << 2) -#define RT5659_PWR_ADC_L2_BIT 2 -#define RT5659_PWR_ADC_R2 (0x1 << 1) -#define RT5659_PWR_ADC_R2_BIT 1 -#define RT5659_PWR_CLS_D (0x1) -#define RT5659_PWR_CLS_D_BIT 0 - -/* Power Management for Digital 2 (0x0062) */ -#define RT5659_PWR_ADC_S1F (0x1 << 15) -#define RT5659_PWR_ADC_S1F_BIT 15 -#define RT5659_PWR_ADC_S2F (0x1 << 14) -#define RT5659_PWR_ADC_S2F_BIT 14 -#define RT5659_PWR_ADC_MF_L (0x1 << 13) -#define RT5659_PWR_ADC_MF_L_BIT 13 -#define RT5659_PWR_ADC_MF_R (0x1 << 12) -#define RT5659_PWR_ADC_MF_R_BIT 12 -#define RT5659_PWR_DAC_S1F (0x1 << 10) -#define RT5659_PWR_DAC_S1F_BIT 10 -#define RT5659_PWR_DAC_MF_L (0x1 << 9) -#define RT5659_PWR_DAC_MF_L_BIT 9 -#define RT5659_PWR_DAC_MF_R (0x1 << 8) -#define RT5659_PWR_DAC_MF_R_BIT 8 -#define RT5659_PWR_PDM1 (0x1 << 7) -#define RT5659_PWR_PDM1_BIT 7 - -/* Power Management for Analog 1 (0x0063) */ -#define RT5659_PWR_VREF1 (0x1 << 15) -#define RT5659_PWR_VREF1_BIT 15 -#define RT5659_PWR_FV1 (0x1 << 14) -#define RT5659_PWR_FV1_BIT 14 -#define RT5659_PWR_VREF2 (0x1 << 13) -#define RT5659_PWR_VREF2_BIT 13 -#define RT5659_PWR_FV2 (0x1 << 12) -#define RT5659_PWR_FV2_BIT 12 -#define RT5659_PWR_VREF3 (0x1 << 11) -#define RT5659_PWR_VREF3_BIT 11 -#define RT5659_PWR_FV3 (0x1 << 10) -#define RT5659_PWR_FV3_BIT 10 -#define RT5659_PWR_MB (0x1 << 9) -#define RT5659_PWR_MB_BIT 9 -#define RT5659_PWR_LM (0x1 << 8) -#define RT5659_PWR_LM_BIT 8 -#define RT5659_PWR_BG (0x1 << 7) -#define RT5659_PWR_BG_BIT 7 -#define RT5659_PWR_MA (0x1 << 6) -#define RT5659_PWR_MA_BIT 6 -#define RT5659_PWR_HA_L (0x1 << 5) -#define RT5659_PWR_HA_L_BIT 5 -#define RT5659_PWR_HA_R (0x1 << 4) -#define RT5659_PWR_HA_R_BIT 4 - -/* Power Management for Analog 2 (0x0064) */ -#define RT5659_PWR_BST1 (0x1 << 15) -#define RT5659_PWR_BST1_BIT 15 -#define RT5659_PWR_BST2 (0x1 << 14) -#define RT5659_PWR_BST2_BIT 14 -#define RT5659_PWR_BST3 (0x1 << 13) -#define RT5659_PWR_BST3_BIT 13 -#define RT5659_PWR_BST4 (0x1 << 12) -#define RT5659_PWR_BST4_BIT 12 -#define RT5659_PWR_MB1 (0x1 << 11) -#define RT5659_PWR_MB1_BIT 11 -#define RT5659_PWR_MB2 (0x1 << 10) -#define RT5659_PWR_MB2_BIT 10 -#define RT5659_PWR_MB3 (0x1 << 9) -#define RT5659_PWR_MB3_BIT 9 -#define RT5659_PWR_BST1_P (0x1 << 6) -#define RT5659_PWR_BST1_P_BIT 6 -#define RT5659_PWR_BST2_P (0x1 << 5) -#define RT5659_PWR_BST2_P_BIT 5 -#define RT5659_PWR_BST3_P (0x1 << 4) -#define RT5659_PWR_BST3_P_BIT 4 -#define RT5659_PWR_BST4_P (0x1 << 3) -#define RT5659_PWR_BST4_P_BIT 3 -#define RT5659_PWR_JD1 (0x1 << 2) -#define RT5659_PWR_JD1_BIT 2 -#define RT5659_PWR_JD2 (0x1 << 1) -#define RT5659_PWR_JD2_BIT 1 -#define RT5659_PWR_JD3 (0x1) -#define RT5659_PWR_JD3_BIT 0 - -/* Power Management for Analog 3 (0x0065) */ -#define RT5659_PWR_BST_L (0x1 << 8) -#define RT5659_PWR_BST_L_BIT 8 -#define RT5659_PWR_BST_R (0x1 << 7) -#define RT5659_PWR_BST_R_BIT 7 -#define RT5659_PWR_PLL (0x1 << 6) -#define RT5659_PWR_PLL_BIT 6 -#define RT5659_PWR_LDO5 (0x1 << 5) -#define RT5659_PWR_LDO5_BIT 5 -#define RT5659_PWR_LDO4 (0x1 << 4) -#define RT5659_PWR_LDO4_BIT 4 -#define RT5659_PWR_LDO3 (0x1 << 3) -#define RT5659_PWR_LDO3_BIT 3 -#define RT5659_PWR_LDO2 (0x1 << 2) -#define RT5659_PWR_LDO2_BIT 2 -#define RT5659_PWR_SVD (0x1 << 1) -#define RT5659_PWR_SVD_BIT 1 - -/* Power Management for Mixer (0x0066) */ -#define RT5659_PWR_OM_L (0x1 << 15) -#define RT5659_PWR_OM_L_BIT 15 -#define RT5659_PWR_OM_R (0x1 << 14) -#define RT5659_PWR_OM_R_BIT 14 -#define RT5659_PWR_SM_L (0x1 << 13) -#define RT5659_PWR_SM_L_BIT 13 -#define RT5659_PWR_SM_R (0x1 << 12) -#define RT5659_PWR_SM_R_BIT 12 -#define RT5659_PWR_RM1_L (0x1 << 11) -#define RT5659_PWR_RM1_L_BIT 11 -#define RT5659_PWR_RM1_R (0x1 << 10) -#define RT5659_PWR_RM1_R_BIT 10 -#define RT5659_PWR_MM (0x1 << 8) -#define RT5659_PWR_MM_BIT 8 -#define RT5659_PWR_RM2_L (0x1 << 3) -#define RT5659_PWR_RM2_L_BIT 3 -#define RT5659_PWR_RM2_R (0x1 << 2) -#define RT5659_PWR_RM2_R_BIT 2 - -/* Power Management for Volume (0x0067) */ -#define RT5659_PWR_SV_L (0x1 << 15) -#define RT5659_PWR_SV_L_BIT 15 -#define RT5659_PWR_SV_R (0x1 << 14) -#define RT5659_PWR_SV_R_BIT 14 -#define RT5659_PWR_OV_L (0x1 << 13) -#define RT5659_PWR_OV_L_BIT 13 -#define RT5659_PWR_OV_R (0x1 << 12) -#define RT5659_PWR_OV_R_BIT 12 -#define RT5659_PWR_IN_L (0x1 << 9) -#define RT5659_PWR_IN_L_BIT 9 -#define RT5659_PWR_IN_R (0x1 << 8) -#define RT5659_PWR_IN_R_BIT 8 -#define RT5659_PWR_MV (0x1 << 7) -#define RT5659_PWR_MV_BIT 7 -#define RT5659_PWR_MIC_DET (0x1 << 5) -#define RT5659_PWR_MIC_DET_BIT 5 - -/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */ -#define RT5659_I2S_MS_MASK (0x1 << 15) -#define RT5659_I2S_MS_SFT 15 -#define RT5659_I2S_MS_M (0x0 << 15) -#define RT5659_I2S_MS_S (0x1 << 15) -#define RT5659_I2S_O_CP_MASK (0x3 << 12) -#define RT5659_I2S_O_CP_SFT 12 -#define RT5659_I2S_O_CP_OFF (0x0 << 12) -#define RT5659_I2S_O_CP_U_LAW (0x1 << 12) -#define RT5659_I2S_O_CP_A_LAW (0x2 << 12) -#define RT5659_I2S_I_CP_MASK (0x3 << 10) -#define RT5659_I2S_I_CP_SFT 10 -#define RT5659_I2S_I_CP_OFF (0x0 << 10) -#define RT5659_I2S_I_CP_U_LAW (0x1 << 10) -#define RT5659_I2S_I_CP_A_LAW (0x2 << 10) -#define RT5659_I2S_BP_MASK (0x1 << 8) -#define RT5659_I2S_BP_SFT 8 -#define RT5659_I2S_BP_NOR (0x0 << 8) -#define RT5659_I2S_BP_INV (0x1 << 8) -#define RT5659_I2S_DL_MASK (0x3 << 4) -#define RT5659_I2S_DL_SFT 4 -#define RT5659_I2S_DL_16 (0x0 << 4) -#define RT5659_I2S_DL_20 (0x1 << 4) -#define RT5659_I2S_DL_24 (0x2 << 4) -#define RT5659_I2S_DL_8 (0x3 << 4) -#define RT5659_I2S_DF_MASK (0x7) -#define RT5659_I2S_DF_SFT 0 -#define RT5659_I2S_DF_I2S (0x0) -#define RT5659_I2S_DF_LEFT (0x1) -#define RT5659_I2S_DF_PCM_A (0x2) -#define RT5659_I2S_DF_PCM_B (0x3) -#define RT5659_I2S_DF_PCM_A_N (0x6) -#define RT5659_I2S_DF_PCM_B_N (0x7) - -/* ADC/DAC Clock Control 1 (0x0073) */ -#define RT5659_I2S_PD1_MASK (0x7 << 12) -#define RT5659_I2S_PD1_SFT 12 -#define RT5659_I2S_PD1_1 (0x0 << 12) -#define RT5659_I2S_PD1_2 (0x1 << 12) -#define RT5659_I2S_PD1_3 (0x2 << 12) -#define RT5659_I2S_PD1_4 (0x3 << 12) -#define RT5659_I2S_PD1_6 (0x4 << 12) -#define RT5659_I2S_PD1_8 (0x5 << 12) -#define RT5659_I2S_PD1_12 (0x6 << 12) -#define RT5659_I2S_PD1_16 (0x7 << 12) -#define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11) -#define RT5659_I2S_BCLK_MS2_SFT 11 -#define RT5659_I2S_BCLK_MS2_32 (0x0 << 11) -#define RT5659_I2S_BCLK_MS2_64 (0x1 << 11) -#define RT5659_I2S_PD2_MASK (0x7 << 8) -#define RT5659_I2S_PD2_SFT 8 -#define RT5659_I2S_PD2_1 (0x0 << 8) -#define RT5659_I2S_PD2_2 (0x1 << 8) -#define RT5659_I2S_PD2_3 (0x2 << 8) -#define RT5659_I2S_PD2_4 (0x3 << 8) -#define RT5659_I2S_PD2_6 (0x4 << 8) -#define RT5659_I2S_PD2_8 (0x5 << 8) -#define RT5659_I2S_PD2_12 (0x6 << 8) -#define RT5659_I2S_PD2_16 (0x7 << 8) -#define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7) -#define RT5659_I2S_BCLK_MS3_SFT 7 -#define RT5659_I2S_BCLK_MS3_32 (0x0 << 7) -#define RT5659_I2S_BCLK_MS3_64 (0x1 << 7) -#define RT5659_I2S_PD3_MASK (0x7 << 4) -#define RT5659_I2S_PD3_SFT 4 -#define RT5659_I2S_PD3_1 (0x0 << 4) -#define RT5659_I2S_PD3_2 (0x1 << 4) -#define RT5659_I2S_PD3_3 (0x2 << 4) -#define RT5659_I2S_PD3_4 (0x3 << 4) -#define RT5659_I2S_PD3_6 (0x4 << 4) -#define RT5659_I2S_PD3_8 (0x5 << 4) -#define RT5659_I2S_PD3_12 (0x6 << 4) -#define RT5659_I2S_PD3_16 (0x7 << 4) -#define RT5659_DAC_OSR_MASK (0x3 << 2) -#define RT5659_DAC_OSR_SFT 2 -#define RT5659_DAC_OSR_128 (0x0 << 2) -#define RT5659_DAC_OSR_64 (0x1 << 2) -#define RT5659_DAC_OSR_32 (0x2 << 2) -#define RT5659_DAC_OSR_16 (0x3 << 2) -#define RT5659_ADC_OSR_MASK (0x3) -#define RT5659_ADC_OSR_SFT 0 -#define RT5659_ADC_OSR_128 (0x0) -#define RT5659_ADC_OSR_64 (0x1) -#define RT5659_ADC_OSR_32 (0x2) -#define RT5659_ADC_OSR_16 (0x3) - -/* Digital Microphone Control (0x0075) */ -#define RT5659_DMIC_1_EN_MASK (0x1 << 15) -#define RT5659_DMIC_1_EN_SFT 15 -#define RT5659_DMIC_1_DIS (0x0 << 15) -#define RT5659_DMIC_1_EN (0x1 << 15) -#define RT5659_DMIC_2_EN_MASK (0x1 << 14) -#define RT5659_DMIC_2_EN_SFT 14 -#define RT5659_DMIC_2_DIS (0x0 << 14) -#define RT5659_DMIC_2_EN (0x1 << 14) -#define RT5659_DMIC_1L_LH_MASK (0x1 << 13) -#define RT5659_DMIC_1L_LH_SFT 13 -#define RT5659_DMIC_1L_LH_RISING (0x0 << 13) -#define RT5659_DMIC_1L_LH_FALLING (0x1 << 13) -#define RT5659_DMIC_1R_LH_MASK (0x1 << 12) -#define RT5659_DMIC_1R_LH_SFT 12 -#define RT5659_DMIC_1R_LH_RISING (0x0 << 12) -#define RT5659_DMIC_1R_LH_FALLING (0x1 << 12) -#define RT5659_DMIC_2_DP_MASK (0x3 << 10) -#define RT5659_DMIC_2_DP_SFT 10 -#define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10) -#define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10) -#define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10) -#define RT5659_DMIC_2_DP_IN2P (0x3 << 10) -#define RT5659_DMIC_CLK_MASK (0x7 << 5) -#define RT5659_DMIC_CLK_SFT 5 -#define RT5659_DMIC_1_DP_MASK (0x3 << 0) -#define RT5659_DMIC_1_DP_SFT 0 -#define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0) -#define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0) -#define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0) -#define RT5659_DMIC_1_DP_IN2N (0x3 << 0) - -/* TDM control 1 (0x0078)*/ -#define RT5659_DS_ADC_SLOT01_SFT 14 -#define RT5659_DS_ADC_SLOT23_SFT 12 -#define RT5659_DS_ADC_SLOT45_SFT 10 -#define RT5659_DS_ADC_SLOT67_SFT 8 -#define RT5659_ADCDAT_SRC_MASK 0x1f -#define RT5659_ADCDAT_SRC_SFT 0 - -/* Global Clock Control (0x0080) */ -#define RT5659_SCLK_SRC_MASK (0x3 << 14) -#define RT5659_SCLK_SRC_SFT 14 -#define RT5659_SCLK_SRC_MCLK (0x0 << 14) -#define RT5659_SCLK_SRC_PLL1 (0x1 << 14) -#define RT5659_SCLK_SRC_RCCLK (0x2 << 14) -#define RT5659_PLL1_SRC_MASK (0x7 << 11) -#define RT5659_PLL1_SRC_SFT 11 -#define RT5659_PLL1_SRC_MCLK (0x0 << 11) -#define RT5659_PLL1_SRC_BCLK1 (0x1 << 11) -#define RT5659_PLL1_SRC_BCLK2 (0x2 << 11) -#define RT5659_PLL1_SRC_BCLK3 (0x3 << 11) -#define RT5659_PLL1_PD_MASK (0x1 << 3) -#define RT5659_PLL1_PD_SFT 3 -#define RT5659_PLL1_PD_1 (0x0 << 3) -#define RT5659_PLL1_PD_2 (0x1 << 3) - -#define RT5659_PLL_INP_MAX 40000000 -#define RT5659_PLL_INP_MIN 256000 -/* PLL M/N/K Code Control 1 (0x0081) */ -#define RT5659_PLL_N_MAX 0x001ff -#define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7) -#define RT5659_PLL_N_SFT 7 -#define RT5659_PLL_K_MAX 0x001f -#define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX) -#define RT5659_PLL_K_SFT 0 - -/* PLL M/N/K Code Control 2 (0x0082) */ -#define RT5659_PLL_M_MAX 0x00f -#define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12) -#define RT5659_PLL_M_SFT 12 -#define RT5659_PLL_M_BP (0x1 << 11) -#define RT5659_PLL_M_BP_SFT 11 - -/* PLL tracking mode 1 (0x0083) */ -#define RT5659_I2S3_ASRC_MASK (0x1 << 13) -#define RT5659_I2S3_ASRC_SFT 13 -#define RT5659_I2S2_ASRC_MASK (0x1 << 12) -#define RT5659_I2S2_ASRC_SFT 12 -#define RT5659_I2S1_ASRC_MASK (0x1 << 11) -#define RT5659_I2S1_ASRC_SFT 11 -#define RT5659_DAC_STO_ASRC_MASK (0x1 << 10) -#define RT5659_DAC_STO_ASRC_SFT 10 -#define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9) -#define RT5659_DAC_MONO_L_ASRC_SFT 9 -#define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8) -#define RT5659_DAC_MONO_R_ASRC_SFT 8 -#define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7) -#define RT5659_DMIC_STO1_ASRC_SFT 7 -#define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5) -#define RT5659_DMIC_MONO_L_ASRC_SFT 5 -#define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4) -#define RT5659_DMIC_MONO_R_ASRC_SFT 4 -#define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3) -#define RT5659_ADC_STO1_ASRC_SFT 3 -#define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1) -#define RT5659_ADC_MONO_L_ASRC_SFT 1 -#define RT5659_ADC_MONO_R_ASRC_MASK (0x1) -#define RT5659_ADC_MONO_R_ASRC_SFT 0 - -/* PLL tracking mode 2 (0x0084)*/ -#define RT5659_DA_STO_T_MASK (0x7 << 12) -#define RT5659_DA_STO_T_SFT 12 -#define RT5659_DA_MONO_L_T_MASK (0x7 << 8) -#define RT5659_DA_MONO_L_T_SFT 8 -#define RT5659_DA_MONO_R_T_MASK (0x7 << 4) -#define RT5659_DA_MONO_R_T_SFT 4 -#define RT5659_AD_STO1_T_MASK (0x7) -#define RT5659_AD_STO1_T_SFT 0 - -/* PLL tracking mode 3 (0x0085)*/ -#define RT5659_AD_STO2_T_MASK (0x7 << 8) -#define RT5659_AD_STO2_T_SFT 8 -#define RT5659_AD_MONO_L_T_MASK (0x7 << 4) -#define RT5659_AD_MONO_L_T_SFT 4 -#define RT5659_AD_MONO_R_T_MASK (0x7) -#define RT5659_AD_MONO_R_T_SFT 0 - -/* ASRC Control 4 (0x0086) */ -#define RT5659_I2S1_RATE_MASK (0xf << 12) -#define RT5659_I2S1_RATE_SFT 12 -#define RT5659_I2S2_RATE_MASK (0xf << 8) -#define RT5659_I2S2_RATE_SFT 8 -#define RT5659_I2S3_RATE_MASK (0xf << 4) -#define RT5659_I2S3_RATE_SFT 4 - -/* Depop Mode Control 1 (0x8e) */ -#define RT5659_SMT_TRIG_MASK (0x1 << 15) -#define RT5659_SMT_TRIG_SFT 15 -#define RT5659_SMT_TRIG_DIS (0x0 << 15) -#define RT5659_SMT_TRIG_EN (0x1 << 15) -#define RT5659_HP_L_SMT_MASK (0x1 << 9) -#define RT5659_HP_L_SMT_SFT 9 -#define RT5659_HP_L_SMT_DIS (0x0 << 9) -#define RT5659_HP_L_SMT_EN (0x1 << 9) -#define RT5659_HP_R_SMT_MASK (0x1 << 8) -#define RT5659_HP_R_SMT_SFT 8 -#define RT5659_HP_R_SMT_DIS (0x0 << 8) -#define RT5659_HP_R_SMT_EN (0x1 << 8) -#define RT5659_HP_CD_PD_MASK (0x1 << 7) -#define RT5659_HP_CD_PD_SFT 7 -#define RT5659_HP_CD_PD_DIS (0x0 << 7) -#define RT5659_HP_CD_PD_EN (0x1 << 7) -#define RT5659_RSTN_MASK (0x1 << 6) -#define RT5659_RSTN_SFT 6 -#define RT5659_RSTN_DIS (0x0 << 6) -#define RT5659_RSTN_EN (0x1 << 6) -#define RT5659_RSTP_MASK (0x1 << 5) -#define RT5659_RSTP_SFT 5 -#define RT5659_RSTP_DIS (0x0 << 5) -#define RT5659_RSTP_EN (0x1 << 5) -#define RT5659_HP_CO_MASK (0x1 << 4) -#define RT5659_HP_CO_SFT 4 -#define RT5659_HP_CO_DIS (0x0 << 4) -#define RT5659_HP_CO_EN (0x1 << 4) -#define RT5659_HP_CP_MASK (0x1 << 3) -#define RT5659_HP_CP_SFT 3 -#define RT5659_HP_CP_PD (0x0 << 3) -#define RT5659_HP_CP_PU (0x1 << 3) -#define RT5659_HP_SG_MASK (0x1 << 2) -#define RT5659_HP_SG_SFT 2 -#define RT5659_HP_SG_DIS (0x0 << 2) -#define RT5659_HP_SG_EN (0x1 << 2) -#define RT5659_HP_DP_MASK (0x1 << 1) -#define RT5659_HP_DP_SFT 1 -#define RT5659_HP_DP_PD (0x0 << 1) -#define RT5659_HP_DP_PU (0x1 << 1) -#define RT5659_HP_CB_MASK (0x1) -#define RT5659_HP_CB_SFT 0 -#define RT5659_HP_CB_PD (0x0) -#define RT5659_HP_CB_PU (0x1) - -/* Depop Mode Control 2 (0x8f) */ -#define RT5659_DEPOP_MASK (0x1 << 13) -#define RT5659_DEPOP_SFT 13 -#define RT5659_DEPOP_AUTO (0x0 << 13) -#define RT5659_DEPOP_MAN (0x1 << 13) -#define RT5659_RAMP_MASK (0x1 << 12) -#define RT5659_RAMP_SFT 12 -#define RT5659_RAMP_DIS (0x0 << 12) -#define RT5659_RAMP_EN (0x1 << 12) -#define RT5659_BPS_MASK (0x1 << 11) -#define RT5659_BPS_SFT 11 -#define RT5659_BPS_DIS (0x0 << 11) -#define RT5659_BPS_EN (0x1 << 11) -#define RT5659_FAST_UPDN_MASK (0x1 << 10) -#define RT5659_FAST_UPDN_SFT 10 -#define RT5659_FAST_UPDN_DIS (0x0 << 10) -#define RT5659_FAST_UPDN_EN (0x1 << 10) -#define RT5659_MRES_MASK (0x3 << 8) -#define RT5659_MRES_SFT 8 -#define RT5659_MRES_15MO (0x0 << 8) -#define RT5659_MRES_25MO (0x1 << 8) -#define RT5659_MRES_35MO (0x2 << 8) -#define RT5659_MRES_45MO (0x3 << 8) -#define RT5659_VLO_MASK (0x1 << 7) -#define RT5659_VLO_SFT 7 -#define RT5659_VLO_3V (0x0 << 7) -#define RT5659_VLO_32V (0x1 << 7) -#define RT5659_DIG_DP_MASK (0x1 << 6) -#define RT5659_DIG_DP_SFT 6 -#define RT5659_DIG_DP_DIS (0x0 << 6) -#define RT5659_DIG_DP_EN (0x1 << 6) -#define RT5659_DP_TH_MASK (0x3 << 4) -#define RT5659_DP_TH_SFT 4 - -/* Depop Mode Control 3 (0x90) */ -#define RT5659_CP_SYS_MASK (0x7 << 12) -#define RT5659_CP_SYS_SFT 12 -#define RT5659_CP_FQ1_MASK (0x7 << 8) -#define RT5659_CP_FQ1_SFT 8 -#define RT5659_CP_FQ2_MASK (0x7 << 4) -#define RT5659_CP_FQ2_SFT 4 -#define RT5659_CP_FQ3_MASK (0x7) -#define RT5659_CP_FQ3_SFT 0 -#define RT5659_CP_FQ_1_5_KHZ 0 -#define RT5659_CP_FQ_3_KHZ 1 -#define RT5659_CP_FQ_6_KHZ 2 -#define RT5659_CP_FQ_12_KHZ 3 -#define RT5659_CP_FQ_24_KHZ 4 -#define RT5659_CP_FQ_48_KHZ 5 -#define RT5659_CP_FQ_96_KHZ 6 -#define RT5659_CP_FQ_192_KHZ 7 - -/* HPOUT charge pump 1 (0x0091) */ -#define RT5659_OSW_L_MASK (0x1 << 11) -#define RT5659_OSW_L_SFT 11 -#define RT5659_OSW_L_DIS (0x0 << 11) -#define RT5659_OSW_L_EN (0x1 << 11) -#define RT5659_OSW_R_MASK (0x1 << 10) -#define RT5659_OSW_R_SFT 10 -#define RT5659_OSW_R_DIS (0x0 << 10) -#define RT5659_OSW_R_EN (0x1 << 10) -#define RT5659_PM_HP_MASK (0x3 << 8) -#define RT5659_PM_HP_SFT 8 -#define RT5659_PM_HP_LV (0x0 << 8) -#define RT5659_PM_HP_MV (0x1 << 8) -#define RT5659_PM_HP_HV (0x2 << 8) -#define RT5659_IB_HP_MASK (0x3 << 6) -#define RT5659_IB_HP_SFT 6 -#define RT5659_IB_HP_125IL (0x0 << 6) -#define RT5659_IB_HP_25IL (0x1 << 6) -#define RT5659_IB_HP_5IL (0x2 << 6) -#define RT5659_IB_HP_1IL (0x3 << 6) - -/* PV detection and SPK gain control (0x92) */ -#define RT5659_PVDD_DET_MASK (0x1 << 15) -#define RT5659_PVDD_DET_SFT 15 -#define RT5659_PVDD_DET_DIS (0x0 << 15) -#define RT5659_PVDD_DET_EN (0x1 << 15) -#define RT5659_SPK_AG_MASK (0x1 << 14) -#define RT5659_SPK_AG_SFT 14 -#define RT5659_SPK_AG_DIS (0x0 << 14) -#define RT5659_SPK_AG_EN (0x1 << 14) - -/* Micbias Control (0x93) */ -#define RT5659_MIC1_BS_MASK (0x1 << 15) -#define RT5659_MIC1_BS_SFT 15 -#define RT5659_MIC1_BS_9AV (0x0 << 15) -#define RT5659_MIC1_BS_75AV (0x1 << 15) -#define RT5659_MIC2_BS_MASK (0x1 << 14) -#define RT5659_MIC2_BS_SFT 14 -#define RT5659_MIC2_BS_9AV (0x0 << 14) -#define RT5659_MIC2_BS_75AV (0x1 << 14) -#define RT5659_MIC1_CLK_MASK (0x1 << 13) -#define RT5659_MIC1_CLK_SFT 13 -#define RT5659_MIC1_CLK_DIS (0x0 << 13) -#define RT5659_MIC1_CLK_EN (0x1 << 13) -#define RT5659_MIC2_CLK_MASK (0x1 << 12) -#define RT5659_MIC2_CLK_SFT 12 -#define RT5659_MIC2_CLK_DIS (0x0 << 12) -#define RT5659_MIC2_CLK_EN (0x1 << 12) -#define RT5659_MIC1_OVCD_MASK (0x1 << 11) -#define RT5659_MIC1_OVCD_SFT 11 -#define RT5659_MIC1_OVCD_DIS (0x0 << 11) -#define RT5659_MIC1_OVCD_EN (0x1 << 11) -#define RT5659_MIC1_OVTH_MASK (0x3 << 9) -#define RT5659_MIC1_OVTH_SFT 9 -#define RT5659_MIC1_OVTH_600UA (0x0 << 9) -#define RT5659_MIC1_OVTH_1500UA (0x1 << 9) -#define RT5659_MIC1_OVTH_2000UA (0x2 << 9) -#define RT5659_MIC2_OVCD_MASK (0x1 << 8) -#define RT5659_MIC2_OVCD_SFT 8 -#define RT5659_MIC2_OVCD_DIS (0x0 << 8) -#define RT5659_MIC2_OVCD_EN (0x1 << 8) -#define RT5659_MIC2_OVTH_MASK (0x3 << 6) -#define RT5659_MIC2_OVTH_SFT 6 -#define RT5659_MIC2_OVTH_600UA (0x0 << 6) -#define RT5659_MIC2_OVTH_1500UA (0x1 << 6) -#define RT5659_MIC2_OVTH_2000UA (0x2 << 6) -#define RT5659_PWR_MB_MASK (0x1 << 5) -#define RT5659_PWR_MB_SFT 5 -#define RT5659_PWR_MB_PD (0x0 << 5) -#define RT5659_PWR_MB_PU (0x1 << 5) -#define RT5659_PWR_CLK25M_MASK (0x1 << 4) -#define RT5659_PWR_CLK25M_SFT 4 -#define RT5659_PWR_CLK25M_PD (0x0 << 4) -#define RT5659_PWR_CLK25M_PU (0x1 << 4) - -/* REC Mixer 2 Left Control 2 (0x009c) */ -#define RT5659_M_BST1_RM2_L (0x1 << 5) -#define RT5659_M_BST1_RM2_L_SFT 5 -#define RT5659_M_BST2_RM2_L (0x1 << 4) -#define RT5659_M_BST2_RM2_L_SFT 4 -#define RT5659_M_BST3_RM2_L (0x1 << 3) -#define RT5659_M_BST3_RM2_L_SFT 3 -#define RT5659_M_BST4_RM2_L (0x1 << 2) -#define RT5659_M_BST4_RM2_L_SFT 2 -#define RT5659_M_OUTVOLL_RM2_L (0x1 << 1) -#define RT5659_M_OUTVOLL_RM2_L_SFT 1 -#define RT5659_M_SPKVOL_RM2_L (0x1) -#define RT5659_M_SPKVOL_RM2_L_SFT 0 - -/* REC Mixer 2 Right Control 2 (0x009e) */ -#define RT5659_M_BST1_RM2_R (0x1 << 5) -#define RT5659_M_BST1_RM2_R_SFT 5 -#define RT5659_M_BST2_RM2_R (0x1 << 4) -#define RT5659_M_BST2_RM2_R_SFT 4 -#define RT5659_M_BST3_RM2_R (0x1 << 3) -#define RT5659_M_BST3_RM2_R_SFT 3 -#define RT5659_M_BST4_RM2_R (0x1 << 2) -#define RT5659_M_BST4_RM2_R_SFT 2 -#define RT5659_M_OUTVOLR_RM2_R (0x1 << 1) -#define RT5659_M_OUTVOLR_RM2_R_SFT 1 -#define RT5659_M_MONOVOL_RM2_R (0x1) -#define RT5659_M_MONOVOL_RM2_R_SFT 0 - -/* Class D Output Control (0x00a0) */ -#define RT5659_POW_CLSD_DB_MASK (0x1 << 9) -#define RT5659_POW_CLSD_DB_EN (0x1 << 9) -#define RT5659_POW_CLSD_DB_DIS (0x0 << 9) - -/* EQ Control 1 (0x00b0) */ -#define RT5659_EQ_SRC_DAC (0x0 << 15) -#define RT5659_EQ_SRC_ADC (0x1 << 15) -#define RT5659_EQ_UPD (0x1 << 14) -#define RT5659_EQ_UPD_BIT 14 -#define RT5659_EQ_CD_MASK (0x1 << 13) -#define RT5659_EQ_CD_SFT 13 -#define RT5659_EQ_CD_DIS (0x0 << 13) -#define RT5659_EQ_CD_EN (0x1 << 13) -#define RT5659_EQ_DITH_MASK (0x3 << 8) -#define RT5659_EQ_DITH_SFT 8 -#define RT5659_EQ_DITH_NOR (0x0 << 8) -#define RT5659_EQ_DITH_LSB (0x1 << 8) -#define RT5659_EQ_DITH_LSB_1 (0x2 << 8) -#define RT5659_EQ_DITH_LSB_2 (0x3 << 8) - -/* IRQ Control 1 (0x00b7) */ -#define RT5659_JD1_1_EN_MASK (0x1 << 15) -#define RT5659_JD1_1_EN_SFT 15 -#define RT5659_JD1_1_DIS (0x0 << 15) -#define RT5659_JD1_1_EN (0x1 << 15) -#define RT5659_JD1_2_EN_MASK (0x1 << 12) -#define RT5659_JD1_2_EN_SFT 12 -#define RT5659_JD1_2_DIS (0x0 << 12) -#define RT5659_JD1_2_EN (0x1 << 12) -#define RT5659_IL_IRQ_MASK (0x1 << 3) -#define RT5659_IL_IRQ_DIS (0x0 << 3) -#define RT5659_IL_IRQ_EN (0x1 << 3) - -/* IRQ Control 5 (0x00ba) */ -#define RT5659_IRQ_JD_EN (0x1 << 3) -#define RT5659_IRQ_JD_EN_SFT 3 - -/* GPIO Control 1 (0x00c0) */ -#define RT5659_GP1_PIN_MASK (0x1 << 15) -#define RT5659_GP1_PIN_SFT 15 -#define RT5659_GP1_PIN_GPIO1 (0x0 << 15) -#define RT5659_GP1_PIN_IRQ (0x1 << 15) -#define RT5659_GP2_PIN_MASK (0x1 << 14) -#define RT5659_GP2_PIN_SFT 14 -#define RT5659_GP2_PIN_GPIO2 (0x0 << 14) -#define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14) -#define RT5659_GP3_PIN_MASK (0x1 << 13) -#define RT5659_GP3_PIN_SFT 13 -#define RT5659_GP3_PIN_GPIO3 (0x0 << 13) -#define RT5659_GP3_PIN_PDM_SCL (0x1 << 13) -#define RT5659_GP4_PIN_MASK (0x1 << 12) -#define RT5659_GP4_PIN_SFT 12 -#define RT5659_GP4_PIN_GPIO4 (0x0 << 12) -#define RT5659_GP4_PIN_PDM_SDA (0x1 << 12) -#define RT5659_GP5_PIN_MASK (0x1 << 11) -#define RT5659_GP5_PIN_SFT 11 -#define RT5659_GP5_PIN_GPIO5 (0x0 << 11) -#define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11) -#define RT5659_GP6_PIN_MASK (0x1 << 10) -#define RT5659_GP6_PIN_SFT 10 -#define RT5659_GP6_PIN_GPIO6 (0x0 << 10) -#define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10) -#define RT5659_GP7_PIN_MASK (0x1 << 9) -#define RT5659_GP7_PIN_SFT 9 -#define RT5659_GP7_PIN_GPIO7 (0x0 << 9) -#define RT5659_GP7_PIN_PDM_SCL (0x1 << 9) -#define RT5659_GP8_PIN_MASK (0x1 << 8) -#define RT5659_GP8_PIN_SFT 8 -#define RT5659_GP8_PIN_GPIO8 (0x0 << 8) -#define RT5659_GP8_PIN_PDM_SDA (0x1 << 8) -#define RT5659_GP9_PIN_MASK (0x1 << 7) -#define RT5659_GP9_PIN_SFT 7 -#define RT5659_GP9_PIN_GPIO9 (0x0 << 7) -#define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7) -#define RT5659_GP10_PIN_MASK (0x1 << 6) -#define RT5659_GP10_PIN_SFT 6 -#define RT5659_GP10_PIN_GPIO10 (0x0 << 6) -#define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6) -#define RT5659_GP11_PIN_MASK (0x1 << 5) -#define RT5659_GP11_PIN_SFT 5 -#define RT5659_GP11_PIN_GPIO11 (0x0 << 5) -#define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5) -#define RT5659_GP12_PIN_MASK (0x1 << 4) -#define RT5659_GP12_PIN_SFT 4 -#define RT5659_GP12_PIN_GPIO12 (0x0 << 4) -#define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4) -#define RT5659_GP13_PIN_MASK (0x3 << 2) -#define RT5659_GP13_PIN_SFT 2 -#define RT5659_GP13_PIN_GPIO13 (0x0 << 2) -#define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2) -#define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2) -#define RT5659_GP13_PIN_PDM_SCL (0x3 << 2) -#define RT5659_GP15_PIN_MASK (0x3) -#define RT5659_GP15_PIN_SFT 0 -#define RT5659_GP15_PIN_GPIO15 (0x0) -#define RT5659_GP15_PIN_DMIC3_SCL (0x1) -#define RT5659_GP15_PIN_PDM_SDA (0x2) - -/* GPIO Control 2 (0x00c1)*/ -#define RT5659_GP1_PF_IN (0x0 << 2) -#define RT5659_GP1_PF_OUT (0x1 << 2) -#define RT5659_GP1_PF_MASK (0x1 << 2) -#define RT5659_GP1_PF_SFT 2 - -/* GPIO Control 3 (0x00c2) */ -#define RT5659_I2S2_PIN_MASK (0x1 << 15) -#define RT5659_I2S2_PIN_SFT 15 -#define RT5659_I2S2_PIN_I2S (0x0 << 15) -#define RT5659_I2S2_PIN_GPIO (0x1 << 15) - -/* Soft volume and zero cross control 1 (0x00d9) */ -#define RT5659_SV_MASK (0x1 << 15) -#define RT5659_SV_SFT 15 -#define RT5659_SV_DIS (0x0 << 15) -#define RT5659_SV_EN (0x1 << 15) -#define RT5659_OUT_SV_MASK (0x1 << 13) -#define RT5659_OUT_SV_SFT 13 -#define RT5659_OUT_SV_DIS (0x0 << 13) -#define RT5659_OUT_SV_EN (0x1 << 13) -#define RT5659_HP_SV_MASK (0x1 << 12) -#define RT5659_HP_SV_SFT 12 -#define RT5659_HP_SV_DIS (0x0 << 12) -#define RT5659_HP_SV_EN (0x1 << 12) -#define RT5659_ZCD_DIG_MASK (0x1 << 11) -#define RT5659_ZCD_DIG_SFT 11 -#define RT5659_ZCD_DIG_DIS (0x0 << 11) -#define RT5659_ZCD_DIG_EN (0x1 << 11) -#define RT5659_ZCD_MASK (0x1 << 10) -#define RT5659_ZCD_SFT 10 -#define RT5659_ZCD_PD (0x0 << 10) -#define RT5659_ZCD_PU (0x1 << 10) -#define RT5659_SV_DLY_MASK (0xf) -#define RT5659_SV_DLY_SFT 0 - -/* Soft volume and zero cross control 2 (0x00da) */ -#define RT5659_ZCD_HP_MASK (0x1 << 15) -#define RT5659_ZCD_HP_SFT 15 -#define RT5659_ZCD_HP_DIS (0x0 << 15) -#define RT5659_ZCD_HP_EN (0x1 << 15) - -/* 4 Button Inline Command Control 2 (0x00e0) */ -#define RT5659_4BTN_IL_MASK (0x1 << 15) -#define RT5659_4BTN_IL_EN (0x1 << 15) -#define RT5659_4BTN_IL_DIS (0x0 << 15) - -/* Analog JD Control 1 (0x00f0) */ -#define RT5659_JD1_MODE_MASK (0x3 << 0) -#define RT5659_JD1_MODE_0 (0x0 << 0) -#define RT5659_JD1_MODE_1 (0x1 << 0) -#define RT5659_JD1_MODE_2 (0x2 << 0) - -/* Jack Detect Control 3 (0x00f8) */ -#define RT5659_JD_TRI_HPO_SEL_MASK (0x7) -#define RT5659_JD_TRI_HPO_SEL_SFT (0) -#define RT5659_JD_HPO_GPIO_JD1 (0x0) -#define RT5659_JD_HPO_JD1_1 (0x1) -#define RT5659_JD_HPO_JD1_2 (0x2) -#define RT5659_JD_HPO_JD2 (0x3) -#define RT5659_JD_HPO_GPIO_JD2 (0x4) -#define RT5659_JD_HPO_JD3 (0x5) -#define RT5659_JD_HPO_JD_D (0x6) - -/* Digital Misc Control (0x00fa) */ -#define RT5659_AM_MASK (0x1 << 7) -#define RT5659_AM_EN (0x1 << 7) -#define RT5659_AM_DIS (0x1 << 7) -#define RT5659_DIG_GATE_CTRL 0x1 -#define RT5659_DIG_GATE_CTRL_SFT (0) - -/* Chopper and Clock control for ADC (0x011c)*/ -#define RT5659_M_RF_DIG_MASK (0x1 << 12) -#define RT5659_M_RF_DIG_SFT 12 -#define RT5659_M_RI_DIG (0x1 << 11) - -/* Chopper and Clock control for DAC (0x013a)*/ -#define RT5659_CKXEN_DAC1_MASK (0x1 << 13) -#define RT5659_CKXEN_DAC1_SFT 13 -#define RT5659_CKGEN_DAC1_MASK (0x1 << 12) -#define RT5659_CKGEN_DAC1_SFT 12 -#define RT5659_CKXEN_DAC2_MASK (0x1 << 5) -#define RT5659_CKXEN_DAC2_SFT 5 -#define RT5659_CKGEN_DAC2_MASK (0x1 << 4) -#define RT5659_CKGEN_DAC2_SFT 4 - -/* Chopper and Clock control for ADC (0x013b)*/ -#define RT5659_CKXEN_ADC1_MASK (0x1 << 13) -#define RT5659_CKXEN_ADC1_SFT 13 -#define RT5659_CKGEN_ADC1_MASK (0x1 << 12) -#define RT5659_CKGEN_ADC1_SFT 12 -#define RT5659_CKXEN_ADC2_MASK (0x1 << 5) -#define RT5659_CKXEN_ADC2_SFT 5 -#define RT5659_CKGEN_ADC2_MASK (0x1 << 4) -#define RT5659_CKGEN_ADC2_SFT 4 - -/* Test Mode Control 1 (0x0145) */ -#define RT5659_AD2DA_LB_MASK (0x1 << 9) -#define RT5659_AD2DA_LB_SFT 9 - -/* Stereo Noise Gate Control 1 (0x0160) */ -#define RT5659_NG2_EN_MASK (0x1 << 15) -#define RT5659_NG2_EN (0x1 << 15) -#define RT5659_NG2_DIS (0x0 << 15) - -/* System Clock Source */ -enum { - RT5659_SCLK_S_MCLK, - RT5659_SCLK_S_PLL1, - RT5659_SCLK_S_RCCLK, -}; - -/* PLL1 Source */ -enum { - RT5659_PLL1_S_MCLK, - RT5659_PLL1_S_BCLK1, - RT5659_PLL1_S_BCLK2, - RT5659_PLL1_S_BCLK3, - RT5659_PLL1_S_BCLK4, -}; - -enum { - RT5659_AIF1, - RT5659_AIF2, - RT5659_AIF3, - RT5659_AIF4, - RT5659_AIFS, -}; - -struct rt5659_pll_code { - bool m_bp; - int m_code; - int n_code; - int k_code; -}; - -struct rt5659_priv { - struct snd_soc_component *component; - struct rt5659_platform_data pdata; - struct regmap *regmap; - struct gpio_desc *gpiod_ldo1_en; - struct gpio_desc *gpiod_reset; - struct snd_soc_jack *hs_jack; - struct delayed_work jack_detect_work; - struct clk *mclk; - - int sysclk; - int sysclk_src; - int lrck[RT5659_AIFS]; - int bclk[RT5659_AIFS]; - int master[RT5659_AIFS]; - int v_id; - - int pll_src; - int pll_in; - int pll_out; - - int jack_type; - bool hda_hp_plugged; - bool hda_mic_plugged; -}; - -int rt5659_set_jack_detect(struct snd_soc_component *component, - struct snd_soc_jack *hs_jack); - -#endif /* __RT5659_H__ */ diff --git a/include/drivers-private/sound/soc/codecs/sgtl5000.h b/include/drivers-private/sound/soc/codecs/sgtl5000.h deleted file mode 100644 index 56ec5863..00000000 --- a/include/drivers-private/sound/soc/codecs/sgtl5000.h +++ /dev/null @@ -1,407 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * sgtl5000.h - SGTL5000 audio codec interface - * - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#ifndef _SGTL5000_H -#define _SGTL5000_H - -/* - * Registers addresses - */ -#define SGTL5000_CHIP_ID 0x0000 -#define SGTL5000_CHIP_DIG_POWER 0x0002 -#define SGTL5000_CHIP_CLK_CTRL 0x0004 -#define SGTL5000_CHIP_I2S_CTRL 0x0006 -#define SGTL5000_CHIP_SSS_CTRL 0x000a -#define SGTL5000_CHIP_ADCDAC_CTRL 0x000e -#define SGTL5000_CHIP_DAC_VOL 0x0010 -#define SGTL5000_CHIP_PAD_STRENGTH 0x0014 -#define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020 -#define SGTL5000_CHIP_ANA_HP_CTRL 0x0022 -#define SGTL5000_CHIP_ANA_CTRL 0x0024 -#define SGTL5000_CHIP_LINREG_CTRL 0x0026 -#define SGTL5000_CHIP_REF_CTRL 0x0028 -#define SGTL5000_CHIP_MIC_CTRL 0x002a -#define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c -#define SGTL5000_CHIP_LINE_OUT_VOL 0x002e -#define SGTL5000_CHIP_ANA_POWER 0x0030 -#define SGTL5000_CHIP_PLL_CTRL 0x0032 -#define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034 -#define SGTL5000_CHIP_ANA_STATUS 0x0036 -#define SGTL5000_CHIP_SHORT_CTRL 0x003c -#define SGTL5000_CHIP_ANA_TEST2 0x003a -#define SGTL5000_DAP_CTRL 0x0100 -#define SGTL5000_DAP_PEQ 0x0102 -#define SGTL5000_DAP_BASS_ENHANCE 0x0104 -#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106 -#define SGTL5000_DAP_AUDIO_EQ 0x0108 -#define SGTL5000_DAP_SURROUND 0x010a -#define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c -#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e -#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110 -#define SGTL5000_DAP_EQ_BASS_BAND0 0x0116 -#define SGTL5000_DAP_EQ_BASS_BAND1 0x0118 -#define SGTL5000_DAP_EQ_BASS_BAND2 0x011a -#define SGTL5000_DAP_EQ_BASS_BAND3 0x011c -#define SGTL5000_DAP_EQ_BASS_BAND4 0x011e -#define SGTL5000_DAP_MAIN_CHAN 0x0120 -#define SGTL5000_DAP_MIX_CHAN 0x0122 -#define SGTL5000_DAP_AVC_CTRL 0x0124 -#define SGTL5000_DAP_AVC_THRESHOLD 0x0126 -#define SGTL5000_DAP_AVC_ATTACK 0x0128 -#define SGTL5000_DAP_AVC_DECAY 0x012a -#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c -#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e -#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130 -#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132 -#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134 -#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136 -#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138 -#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a - -/* - * Field Definitions. - */ - -/* - * SGTL5000_CHIP_ID - */ -#define SGTL5000_PARTID_MASK 0xff00 -#define SGTL5000_PARTID_SHIFT 8 -#define SGTL5000_PARTID_WIDTH 8 -#define SGTL5000_PARTID_PART_ID 0xa0 -#define SGTL5000_REVID_MASK 0x00ff -#define SGTL5000_REVID_SHIFT 0 -#define SGTL5000_REVID_WIDTH 8 - -/* - * SGTL5000_CHIP_DIG_POWER - */ -#define SGTL5000_ADC_EN 0x0040 -#define SGTL5000_DAC_EN 0x0020 -#define SGTL5000_DAP_POWERUP 0x0010 -#define SGTL5000_I2S_OUT_POWERUP 0x0002 -#define SGTL5000_I2S_IN_POWERUP 0x0001 - -/* - * SGTL5000_CHIP_CLK_CTRL - */ -#define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x0008 -#define SGTL5000_RATE_MODE_MASK 0x0030 -#define SGTL5000_RATE_MODE_SHIFT 4 -#define SGTL5000_RATE_MODE_WIDTH 2 -#define SGTL5000_RATE_MODE_DIV_1 0 -#define SGTL5000_RATE_MODE_DIV_2 1 -#define SGTL5000_RATE_MODE_DIV_4 2 -#define SGTL5000_RATE_MODE_DIV_6 3 -#define SGTL5000_SYS_FS_MASK 0x000c -#define SGTL5000_SYS_FS_SHIFT 2 -#define SGTL5000_SYS_FS_WIDTH 2 -#define SGTL5000_SYS_FS_32k 0x0 -#define SGTL5000_SYS_FS_44_1k 0x1 -#define SGTL5000_SYS_FS_48k 0x2 -#define SGTL5000_SYS_FS_96k 0x3 -#define SGTL5000_MCLK_FREQ_MASK 0x0003 -#define SGTL5000_MCLK_FREQ_SHIFT 0 -#define SGTL5000_MCLK_FREQ_WIDTH 2 -#define SGTL5000_MCLK_FREQ_256FS 0x0 -#define SGTL5000_MCLK_FREQ_384FS 0x1 -#define SGTL5000_MCLK_FREQ_512FS 0x2 -#define SGTL5000_MCLK_FREQ_PLL 0x3 - -/* - * SGTL5000_CHIP_I2S_CTRL - */ -#define SGTL5000_I2S_SCLKFREQ_MASK 0x0100 -#define SGTL5000_I2S_SCLKFREQ_SHIFT 8 -#define SGTL5000_I2S_SCLKFREQ_WIDTH 1 -#define SGTL5000_I2S_SCLKFREQ_64FS 0x0 -#define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */ -#define SGTL5000_I2S_MASTER 0x0080 -#define SGTL5000_I2S_SCLK_INV 0x0040 -#define SGTL5000_I2S_DLEN_MASK 0x0030 -#define SGTL5000_I2S_DLEN_SHIFT 4 -#define SGTL5000_I2S_DLEN_WIDTH 2 -#define SGTL5000_I2S_DLEN_32 0x0 -#define SGTL5000_I2S_DLEN_24 0x1 -#define SGTL5000_I2S_DLEN_20 0x2 -#define SGTL5000_I2S_DLEN_16 0x3 -#define SGTL5000_I2S_MODE_MASK 0x000c -#define SGTL5000_I2S_MODE_SHIFT 2 -#define SGTL5000_I2S_MODE_WIDTH 2 -#define SGTL5000_I2S_MODE_I2S_LJ 0x0 -#define SGTL5000_I2S_MODE_RJ 0x1 -#define SGTL5000_I2S_MODE_PCM 0x2 -#define SGTL5000_I2S_LRALIGN 0x0002 -#define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */ - -/* - * SGTL5000_CHIP_SSS_CTRL - */ -#define SGTL5000_DAP_MIX_LRSWAP 0x4000 -#define SGTL5000_DAP_LRSWAP 0x2000 -#define SGTL5000_DAC_LRSWAP 0x1000 -#define SGTL5000_I2S_OUT_LRSWAP 0x0400 -#define SGTL5000_DAP_MIX_SEL_MASK 0x0300 -#define SGTL5000_DAP_MIX_SEL_SHIFT 8 -#define SGTL5000_DAP_MIX_SEL_WIDTH 2 -#define SGTL5000_DAP_MIX_SEL_ADC 0x0 -#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1 -#define SGTL5000_DAP_SEL_MASK 0x00c0 -#define SGTL5000_DAP_SEL_SHIFT 6 -#define SGTL5000_DAP_SEL_WIDTH 2 -#define SGTL5000_DAP_SEL_ADC 0x0 -#define SGTL5000_DAP_SEL_I2S_IN 0x1 -#define SGTL5000_DAC_SEL_MASK 0x0030 -#define SGTL5000_DAC_SEL_SHIFT 4 -#define SGTL5000_DAC_SEL_WIDTH 2 -#define SGTL5000_DAC_SEL_ADC 0x0 -#define SGTL5000_DAC_SEL_I2S_IN 0x1 -#define SGTL5000_DAC_SEL_DAP 0x3 -#define SGTL5000_I2S_OUT_SEL_MASK 0x0003 -#define SGTL5000_I2S_OUT_SEL_SHIFT 0 -#define SGTL5000_I2S_OUT_SEL_WIDTH 2 -#define SGTL5000_I2S_OUT_SEL_ADC 0x0 -#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1 -#define SGTL5000_I2S_OUT_SEL_DAP 0x3 - -/* - * SGTL5000_CHIP_ADCDAC_CTRL - */ -#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000 -#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000 -#define SGTL5000_DAC_VOL_RAMP_EN 0x0200 -#define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100 -#define SGTL5000_DAC_MUTE_RIGHT 0x0008 -#define SGTL5000_DAC_MUTE_LEFT 0x0004 -#define SGTL5000_ADC_HPF_FREEZE 0x0002 -#define SGTL5000_ADC_HPF_BYPASS 0x0001 - -/* - * SGTL5000_CHIP_DAC_VOL - */ -#define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00 -#define SGTL5000_DAC_VOL_RIGHT_SHIFT 8 -#define SGTL5000_DAC_VOL_RIGHT_WIDTH 8 -#define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff -#define SGTL5000_DAC_VOL_LEFT_SHIFT 0 -#define SGTL5000_DAC_VOL_LEFT_WIDTH 8 - -/* - * SGTL5000_CHIP_PAD_STRENGTH - */ -#define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300 -#define SGTL5000_PAD_I2S_LRCLK_SHIFT 8 -#define SGTL5000_PAD_I2S_LRCLK_WIDTH 2 -#define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0 -#define SGTL5000_PAD_I2S_SCLK_SHIFT 6 -#define SGTL5000_PAD_I2S_SCLK_WIDTH 2 -#define SGTL5000_PAD_I2S_DOUT_MASK 0x0030 -#define SGTL5000_PAD_I2S_DOUT_SHIFT 4 -#define SGTL5000_PAD_I2S_DOUT_WIDTH 2 -#define SGTL5000_PAD_I2C_SDA_MASK 0x000c -#define SGTL5000_PAD_I2C_SDA_SHIFT 2 -#define SGTL5000_PAD_I2C_SDA_WIDTH 2 -#define SGTL5000_PAD_I2C_SCL_MASK 0x0003 -#define SGTL5000_PAD_I2C_SCL_SHIFT 0 -#define SGTL5000_PAD_I2C_SCL_WIDTH 2 - -/* - * SGTL5000_CHIP_ANA_ADC_CTRL - */ -#define SGTL5000_ADC_VOL_M6DB 0x0100 -#define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0 -#define SGTL5000_ADC_VOL_RIGHT_SHIFT 4 -#define SGTL5000_ADC_VOL_RIGHT_WIDTH 4 -#define SGTL5000_ADC_VOL_LEFT_MASK 0x000f -#define SGTL5000_ADC_VOL_LEFT_SHIFT 0 -#define SGTL5000_ADC_VOL_LEFT_WIDTH 4 - -/* - * SGTL5000_CHIP_ANA_HP_CTRL - */ -#define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00 -#define SGTL5000_HP_VOL_RIGHT_SHIFT 8 -#define SGTL5000_HP_VOL_RIGHT_WIDTH 7 -#define SGTL5000_HP_VOL_LEFT_MASK 0x007f -#define SGTL5000_HP_VOL_LEFT_SHIFT 0 -#define SGTL5000_HP_VOL_LEFT_WIDTH 7 - -/* - * SGTL5000_CHIP_ANA_CTRL - */ -#define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133 -#define SGTL5000_LINE_OUT_MUTE 0x0100 -#define SGTL5000_HP_SEL_MASK 0x0040 -#define SGTL5000_HP_SEL_SHIFT 6 -#define SGTL5000_HP_SEL_WIDTH 1 -#define SGTL5000_HP_SEL_DAC 0x0 -#define SGTL5000_HP_SEL_LINE_IN 0x1 -#define SGTL5000_HP_ZCD_EN 0x0020 -#define SGTL5000_HP_MUTE 0x0010 -#define SGTL5000_ADC_SEL_MASK 0x0004 -#define SGTL5000_ADC_SEL_SHIFT 2 -#define SGTL5000_ADC_SEL_WIDTH 1 -#define SGTL5000_ADC_SEL_MIC 0x0 -#define SGTL5000_ADC_SEL_LINE_IN 0x1 -#define SGTL5000_ADC_ZCD_EN 0x0002 -#define SGTL5000_ADC_MUTE 0x0001 - -/* - * SGTL5000_CHIP_LINREG_CTRL - */ -#define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040 -#define SGTL5000_VDDC_MAN_ASSN_SHIFT 6 -#define SGTL5000_VDDC_MAN_ASSN_WIDTH 1 -#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0 -#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1 -#define SGTL5000_VDDC_ASSN_OVRD 0x0020 -#define SGTL5000_LINREG_VDDD_MASK 0x000f -#define SGTL5000_LINREG_VDDD_SHIFT 0 -#define SGTL5000_LINREG_VDDD_WIDTH 4 - -/* - * SGTL5000_CHIP_REF_CTRL - */ -#define SGTL5000_ANA_GND_MASK 0x01f0 -#define SGTL5000_ANA_GND_SHIFT 4 -#define SGTL5000_ANA_GND_WIDTH 5 -#define SGTL5000_ANA_GND_BASE 800 /* mv */ -#define SGTL5000_ANA_GND_STP 25 /*mv */ -#define SGTL5000_BIAS_CTRL_MASK 0x000e -#define SGTL5000_BIAS_CTRL_SHIFT 1 -#define SGTL5000_BIAS_CTRL_WIDTH 3 -#define SGTL5000_SMALL_POP 0x0001 - -/* - * SGTL5000_CHIP_MIC_CTRL - */ -#define SGTL5000_BIAS_R_MASK 0x0300 -#define SGTL5000_BIAS_R_SHIFT 8 -#define SGTL5000_BIAS_R_WIDTH 2 -#define SGTL5000_BIAS_R_off 0x0 -#define SGTL5000_BIAS_R_2K 0x1 -#define SGTL5000_BIAS_R_4k 0x2 -#define SGTL5000_BIAS_R_8k 0x3 -#define SGTL5000_BIAS_VOLT_MASK 0x0070 -#define SGTL5000_BIAS_VOLT_SHIFT 4 -#define SGTL5000_BIAS_VOLT_WIDTH 3 -#define SGTL5000_MIC_GAIN_MASK 0x0003 -#define SGTL5000_MIC_GAIN_SHIFT 0 -#define SGTL5000_MIC_GAIN_WIDTH 2 - -/* - * SGTL5000_CHIP_LINE_OUT_CTRL - */ -#define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00 -#define SGTL5000_LINE_OUT_CURRENT_SHIFT 8 -#define SGTL5000_LINE_OUT_CURRENT_WIDTH 4 -#define SGTL5000_LINE_OUT_CURRENT_180u 0x0 -#define SGTL5000_LINE_OUT_CURRENT_270u 0x1 -#define SGTL5000_LINE_OUT_CURRENT_360u 0x3 -#define SGTL5000_LINE_OUT_CURRENT_450u 0x7 -#define SGTL5000_LINE_OUT_CURRENT_540u 0xf -#define SGTL5000_LINE_OUT_GND_MASK 0x003f -#define SGTL5000_LINE_OUT_GND_SHIFT 0 -#define SGTL5000_LINE_OUT_GND_WIDTH 6 -#define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */ -#define SGTL5000_LINE_OUT_GND_STP 25 -#define SGTL5000_LINE_OUT_GND_MAX 0x23 - -/* - * SGTL5000_CHIP_LINE_OUT_VOL - */ -#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00 -#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8 -#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5 -#define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f -#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0 -#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5 - -/* - * SGTL5000_CHIP_ANA_POWER - */ -#define SGTL5000_ANA_POWER_DEFAULT 0x7060 -#define SGTL5000_DAC_STEREO 0x4000 -#define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000 -#define SGTL5000_STARTUP_POWERUP 0x1000 -#define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800 -#define SGTL5000_PLL_POWERUP 0x0400 -#define SGTL5000_LINEREG_D_POWERUP 0x0200 -#define SGTL5000_VCOAMP_POWERUP 0x0100 -#define SGTL5000_VAG_POWERUP 0x0080 -#define SGTL5000_ADC_STEREO 0x0040 -#define SGTL5000_REFTOP_POWERUP 0x0020 -#define SGTL5000_HP_POWERUP 0x0010 -#define SGTL5000_DAC_POWERUP 0x0008 -#define SGTL5000_CAPLESS_HP_POWERUP 0x0004 -#define SGTL5000_ADC_POWERUP 0x0002 -#define SGTL5000_LINE_OUT_POWERUP 0x0001 - -/* - * SGTL5000_CHIP_PLL_CTRL - */ -#define SGTL5000_PLL_INT_DIV_MASK 0xf800 -#define SGTL5000_PLL_INT_DIV_SHIFT 11 -#define SGTL5000_PLL_INT_DIV_WIDTH 5 -#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff -#define SGTL5000_PLL_FRAC_DIV_SHIFT 0 -#define SGTL5000_PLL_FRAC_DIV_WIDTH 11 - -/* - * SGTL5000_CHIP_CLK_TOP_CTRL - */ -#define SGTL5000_INT_OSC_EN 0x0800 -#define SGTL5000_INPUT_FREQ_DIV2 0x0008 - -/* - * SGTL5000_CHIP_ANA_STATUS - */ -#define SGTL5000_HP_LRSHORT 0x0200 -#define SGTL5000_CAPLESS_SHORT 0x0100 -#define SGTL5000_PLL_LOCKED 0x0010 - -/* - * SGTL5000_CHIP_SHORT_CTRL - */ -#define SGTL5000_LVLADJR_MASK 0x7000 -#define SGTL5000_LVLADJR_SHIFT 12 -#define SGTL5000_LVLADJR_WIDTH 3 -#define SGTL5000_LVLADJL_MASK 0x0700 -#define SGTL5000_LVLADJL_SHIFT 8 -#define SGTL5000_LVLADJL_WIDTH 3 -#define SGTL5000_LVLADJC_MASK 0x0070 -#define SGTL5000_LVLADJC_SHIFT 4 -#define SGTL5000_LVLADJC_WIDTH 3 -#define SGTL5000_LR_SHORT_MOD_MASK 0x000c -#define SGTL5000_LR_SHORT_MOD_SHIFT 2 -#define SGTL5000_LR_SHORT_MOD_WIDTH 2 -#define SGTL5000_CM_SHORT_MOD_MASK 0x0003 -#define SGTL5000_CM_SHORT_MOD_SHIFT 0 -#define SGTL5000_CM_SHORT_MOD_WIDTH 2 - -/* - *SGTL5000_CHIP_ANA_TEST2 - */ -#define SGTL5000_MONO_DAC 0x1000 - -/* - * SGTL5000_DAP_CTRL - */ -#define SGTL5000_DAP_MIX_EN 0x0010 -#define SGTL5000_DAP_EN 0x0001 - -#define SGTL5000_SYSCLK 0x00 -#define SGTL5000_LRCLK 0x01 - -/* - * SGTL5000_DAP_AUDIO_EQ - */ -#define SGTL5000_DAP_SEL_PEQ 1 -#define SGTL5000_DAP_SEL_TONE_CTRL 2 -#define SGTL5000_DAP_SEL_GEQ 3 - -#endif diff --git a/include/drivers-private/sound/soc/tegra/tegra_pcm.h b/include/drivers-private/sound/soc/tegra/tegra_pcm.h deleted file mode 100644 index b986c12b..00000000 --- a/include/drivers-private/sound/soc/tegra/tegra_pcm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * tegra_pcm.h - Definitions for Tegra PCM driver - * - * Author: Stephen Warren - * Copyright (C) 2010-2022 - NVIDIA, Inc. - * - * Based on code copyright/by: - * - * Copyright (c) 2009-2010, NVIDIA Corporation. - * Scott Peterson - * - * Copyright (C) 2010 Google, Inc. - * Iliyan Malchev - */ - -#ifndef __TEGRA_PCM_H__ -#define __TEGRA_PCM_H__ - -#include -#include - -int tegra_pcm_construct(struct snd_soc_component *component, - struct snd_soc_pcm_runtime *rtd); -int tegra_pcm_open(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -int tegra_pcm_close(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -int tegra_pcm_hw_params(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -snd_pcm_uframes_t tegra_pcm_pointer(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -int tegra_pcm_platform_register(struct device *dev); -int tegra_pcm_platform_register_with_chan_names(struct device *dev, - struct snd_dmaengine_pcm_config *config, - char *txdmachan, char *rxdmachan); -void tegra_pcm_platform_unregister(struct device *dev); - -#endif