diff --git a/drivers/video/tegra/host/pva/pva.c b/drivers/video/tegra/host/pva/pva.c
index f6723f28..3e04a7d0 100644
--- a/drivers/video/tegra/host/pva/pva.c
+++ b/drivers/video/tegra/host/pva/pva.c
@@ -381,6 +381,19 @@ static int pva_init_fw(struct platform_device *pdev)
 		host1x_writel(pdev,
 			      cfg_priv_ar1_usegreg_r(pva->version),
 			      PVA_EXTRACT64((useg_addr), 39, 32, u32));
+
+		if (pdata->version != PVA_HW_GEN1) {
+			host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL | PVA_LOCK_SCR);
+			host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL | PVA_LOCK_SCR);
+			host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL | PVA_LOCK_SCR);
+		}
+
+		/* WAR: Bypass configuring status strl reg due to failure in gen 3 sim test */
+		if (pdata->version == PVA_HW_GEN2) {
+			host1x_writel(pdev, cfg_scr_status_ctrl_r(),
+					PVA_STATUS_CTL_SCR_VAL | PVA_LOCK_SCR);
+		}
+
 	}
 
 	/* Indicate the OS is waiting for PVA ready Interrupt */
diff --git a/drivers/video/tegra/host/pva/pva_regs.h b/drivers/video/tegra/host/pva/pva_regs.h
index e9ea712d..4293b3d1 100644
--- a/drivers/video/tegra/host/pva/pva_regs.h
+++ b/drivers/video/tegra/host/pva/pva_regs.h
@@ -38,6 +38,11 @@
 #define PVA_PROC_SCR_PROC_0_VAL             (0x39000282U)
 /** @} */
 
+/**
+ * @brief Macro to set lock bit of SCR firewall register.
+ */
+#define PVA_LOCK_SCR (0x20000000U)
+
 /* Definition for LIC_INTR_ENABLE bits */
 #define SEC_LIC_INTR_HSP1	0x1
 #define SEC_LIC_INTR_HSP2	0x2