From b79129381b3fbf0be013fbed36aed0772913b139 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Thu, 22 May 2025 18:17:22 +0000 Subject: [PATCH] platform: tegra: Check if MC channel is enabled In MC-HWPM driver, check if MC channel is enabled before accessing its registers. Bug 5279654 Change-Id: I41e3d277a75d0a1045e47f148e2b9eb63f29b279 Signed-off-by: Ashish Mhetre Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3369527 Reviewed-by: svcacv GVS: buildbot_gerritrpt Reviewed-by: Sachin Nikam (cherry picked from commit e2b9c86688cc76fdb87b97b67f4ddb6c280cd10a) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3370768 --- drivers/platform/tegra/mc-hwpm.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/platform/tegra/mc-hwpm.c b/drivers/platform/tegra/mc-hwpm.c index 35cf9f69..8dec9694 100644 --- a/drivers/platform/tegra/mc-hwpm.c +++ b/drivers/platform/tegra/mc-hwpm.c @@ -16,8 +16,11 @@ #include +#include + /* Broadcast Channel + 16 MC Channels */ #define MAX_MC_CHANNELS 17 +#define FUSE_EMC_DISABLE_OFFSET 0x8c0 static struct tegra_soc_hwpm_ip_ops hwpm_ip_ops; @@ -46,6 +49,23 @@ static void mc_writel(struct tegra_mc_hwpm *mc, u32 ch_no, u32 val, u32 reg) writel(val, mc->ch_regs[ch_no] + reg); } +static bool is_channel_enabled(u32 ch) +{ + u32 fuse_val = 0U; + int err = 0; + + err = tegra_fuse_readl(FUSE_EMC_DISABLE_OFFSET, &fuse_val); + if (err != 0) { + pr_err("Failed to read EMC FUSE\n"); + return false; + } + + if ((fuse_val & BIT(ch)) == 0) + return true; + + return false; +} + static int tegra_mc_hwpm_reg_op(void *ip_dev, enum tegra_soc_hwpm_ip_reg_op reg_op, u32 inst_element_index, u64 reg_offset, u32 *reg_data) @@ -64,6 +84,12 @@ static int tegra_mc_hwpm_reg_op(void *ip_dev, return -EINVAL; } + if (inst_element_index > 0) { + if (!is_channel_enabled(inst_element_index - 1)) { + dev_err(mc->dev, "MC Channel %u is not enabled\n", inst_element_index); + return -ENODEV; + } + } if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_READ) { *reg_data = mc_readl(mc, inst_element_index, (u32)reg_offset); } else if (reg_op == TEGRA_SOC_HWPM_IP_REG_OP_WRITE) {