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drivers:pva: support up to 96 descriptors for MISR

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Jira PVAAS-15361

Change-Id: Ic1c7b0396304a858c478292533ff3d1d05871741
Signed-off-by: omar <onemri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3158078
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Omar Nemri
2024-06-06 10:31:36 -07:00
committed by mobile promotions
parent d86f5508cd
commit baee98bcb9
2 changed files with 6 additions and 3 deletions
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8
drivers/video/tegra/host/pva/pva_dma.c
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@@ -844,8 +844,11 @@ static int32_t nvpva_task_dma_desc_mapping(struct pva_submit_task *task,
const uint8_t resv_desc_end_idx = (NVPVA_RESERVED_DESCRIPTORS_START_IDX
+ NVPVA_NUM_RESERVED_DESCRIPTORS - 1);
bool dim3_check_relaxed = false;
u64 descriptor_mask[2];
nvpva_dbg_fn(task->pva, "");
descriptor_mask[0] = task->dma_misr_config.descriptor_mask;
descriptor_mask[1] = (u64) task->dma_misr_config.descriptor_mask_high;
desc_num = *did;
for (i = 0; (i < num_descs)
@@ -863,9 +866,8 @@ static int32_t nvpva_task_dma_desc_mapping(struct pva_submit_task *task,
umd_dma_desc = &task->dma_descriptors[desc_num];
dma_desc = &hw_task->dma_desc[desc_num];
is_misr = !((task->dma_misr_config.descriptor_mask
& PVA_BIT64(desc_num)) == 0U);
is_misr = is_misr && (task->dma_misr_config.enable != 0U);
is_misr = (descriptor_mask[desc_num/64] & PVA_BIT64(desc_num%64))
&& (task->dma_misr_config.enable != 0U);
dim3_check_relaxed = is_hwseq_mode_frm(task, desc_num)
|| is_hwseq_mode_t26x(task, desc_num);

1
include/uapi/linux/nvpva_ioctl.h
View File

@@ -464,6 +464,7 @@ struct nvpva_dma_misr {
* number of AXI clock cycles.
*/
uint32_t misr_timeout;
uint32_t descriptor_mask_high;
};
/**