diff --git a/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c b/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c index c4a1ea4f..ec2eaa95 100644 --- a/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c +++ b/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c @@ -2,7 +2,7 @@ /* * Tegra CSI5 device common APIs * - * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. */ #include #include @@ -516,4 +516,4 @@ struct tegra_csi_fops csi5_fops = { .hw_init = csi5_hw_init, .tpg_set_gain = csi5_tpg_set_gain, }; -EXPORT_SYMBOL(csi5_fops); \ No newline at end of file +EXPORT_SYMBOL(csi5_fops); diff --git a/drivers/platform/tegra/rtcpu/camchar.c b/drivers/platform/tegra/rtcpu/camchar.c index 00491207..2944b18f 100644 --- a/drivers/platform/tegra/rtcpu/camchar.c +++ b/drivers/platform/tegra/rtcpu/camchar.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. #include #include @@ -398,7 +398,7 @@ static struct tegra_ivc_driver camchar_driver = { .ops.channel = &tegra_ivc_channel_chardev_ops, }; -tegra_ivc_subsys_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit); +module_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit); MODULE_AUTHOR("Jan Solanti "); MODULE_DESCRIPTION("The character device for ivc-bus"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/platform/tegra/rtcpu/ivc-bus.c b/drivers/platform/tegra/rtcpu/ivc-bus.c index 5602bd52..344d46ec 100644 --- a/drivers/platform/tegra/rtcpu/ivc-bus.c +++ b/drivers/platform/tegra/rtcpu/ivc-bus.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. #include #include @@ -78,7 +78,6 @@ static struct tegra_ivc_channel *tegra_ivc_channel_create( struct tegra_ivc_region *region, struct camrtc_hsp *camhsp) { - struct device *peer_device = bus->dev.parent; struct camrtc_tlv_ivc_setup *tlv; struct { u32 rx; diff --git a/drivers/platform/tegra/tegra-camera-rtcpu-base.c b/drivers/platform/tegra/tegra-camera-rtcpu-base.c index 1c24ffbe..d3a55ca0 100644 --- a/drivers/platform/tegra/tegra-camera-rtcpu-base.c +++ b/drivers/platform/tegra/tegra-camera-rtcpu-base.c @@ -71,18 +71,6 @@ static int tegra_rce_cam_wait_for_idle(struct device *dev); static void tegra_rce_cam_assert_resets(struct device *dev); static int tegra_rce_cam_deassert_resets(struct device *dev); -static const char * const sce_reset_names[] = { - "nvidia,reset-group-1", - "nvidia,reset-group-2", - NULL, -}; - -static const char * const sce_reg_names[] = { - "sce-pm", - "sce-cfg", - NULL -}; - static const char * const rce_reset_names[] = { "reset-names", /* all named resets */ NULL, @@ -353,79 +341,6 @@ static void tegra_camrtc_set_fwloaddone(struct device *dev, bool fwloaddone) } } -static int tegra_sce_cam_deassert_resets(struct device *dev) -{ - struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev); - int err; - - err = camrtc_reset_group_deassert(rtcpu->resets[0]); - if (err) - return err; - - /* Configure R5 core */ - if (rtcpu->cfg_base != NULL) { - u32 val = readl(rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0); - - if (val != TEGRA_R5R_SC_DISABLE) { - /* Disable R5R and smartcomp in camera mode */ - writel(TEGRA_R5R_SC_DISABLE, - rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0); - - /* Enable JTAG/Coresight */ - writel(TEGRA_FN_MODEIN, - rtcpu->cfg_base + TEGRA_APS_FRSC_SC_MODEIN_0); - } - } - - /* Group 2 */ - err = camrtc_reset_group_deassert(rtcpu->resets[1]); - if (err) - return err; - - /* Group 3: nCPUHALT controlled by PM, not by CAR. */ - tegra_camrtc_set_fwloaddone(dev, true); - - return 0; -} - -static void tegra_sce_cam_assert_resets(struct device *dev) -{ - struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev); - - tegra_camrtc_set_fwloaddone(dev, false); - - camrtc_reset_group_assert(rtcpu->resets[1]); - camrtc_reset_group_assert(rtcpu->resets[0]); -} - -static int tegra_sce_cam_wait_for_idle(struct device *dev) -{ - struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev); - long timeout = rtcpu->cmd_timeout; - long delay_stride = HZ / 50; - - if (rtcpu->pm_base == NULL) - return 0; - - /* Poll for WFI assert.*/ - for (;;) { - u32 val = readl(rtcpu->pm_base + TEGRA_PM_PWR_STATUS_0); - - if ((val & TEGRA_PM_WFIPIPESTOPPED) == 0) - break; - - if (timeout < 0) { - dev_warn(dev, "timeout waiting for WFI\n"); - return -EBUSY; - } - - msleep(delay_stride); - timeout -= delay_stride; - } - - return 0; -} - static int tegra_rce_cam_wait_for_idle(struct device *dev) { struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev); diff --git a/drivers/video/tegra/camera/tegra_camera_platform.c b/drivers/video/tegra/camera/tegra_camera_platform.c index 151651d9..79c24e39 100644 --- a/drivers/video/tegra/camera/tegra_camera_platform.c +++ b/drivers/video/tegra/camera/tegra_camera_platform.c @@ -225,13 +225,16 @@ static int tegra_camera_isomgr_unregister(struct tegra_camera_info *info) static int tegra_camera_isomgr_request( struct tegra_camera_info *info, uint iso_bw, uint lt) { +#if defined(CONFIG_TEGRA_ISOMGR) int ret = 0; +#endif dev_dbg(info->dev, "%s++ bw=%u, lt=%u\n", __func__, iso_bw, lt); #if IS_ENABLED(CONFIG_INTERCONNECT) && IS_ENABLED(CONFIG_TEGRA_T23X_GRHOST) if (tegra_get_chip_id() == TEGRA234) { + int ret = 0; /* VI6 does not tolerate DVFS, so we need to request max DRAM floor */ ret = icc_set_bw(info->icc_iso_path_handle, iso_bw, UINT_MAX); @@ -426,7 +429,7 @@ int tegra_camera_update_isobw(void) struct tegra_camera_info *info; unsigned long total_khz; unsigned long bw; -#ifdef CONFIG_TEGRA_MC +#ifdef CONFIG_NV_TEGRA_MC unsigned long bw_mbps; #endif int ret = 0; @@ -576,8 +579,6 @@ static long tegra_camera_ioctl(struct file *file, case _IOC_NR(TEGRA_CAMERA_IOCTL_GET_BW): { - unsigned long mc_hz = 0; - u64 bw = 0; #if IS_ENABLED(CONFIG_INTERCONNECT) && IS_ENABLED(CONFIG_TEGRA_T23X_GRHOST) if (tegra_get_chip_id() == TEGRA234) { dev_err(info->dev, @@ -587,7 +588,6 @@ static long tegra_camera_ioctl(struct file *file, } #endif - return -EFAULT; break; } diff --git a/drivers/video/tegra/host/vi/vi5.c b/drivers/video/tegra/host/vi/vi5.c index 05426baf..a59ad06f 100644 --- a/drivers/video/tegra/host/vi/vi5.c +++ b/drivers/video/tegra/host/vi/vi5.c @@ -2,7 +2,7 @@ /* * VI5 driver * - * Copyright (c) 2017-2022, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA Corporation. All rights reserved. */ #include @@ -284,7 +284,7 @@ static int vi5_remove(struct platform_device *pdev) return 0; } -struct nvhost_device_data t19_vi5_info = { +static struct nvhost_device_data t19_vi5_info = { .devfs_name = "vi", .moduleid = 2, //NVHOST_MODULE_VI, .clocks = { @@ -300,7 +300,7 @@ struct nvhost_device_data t19_vi5_info = { .bwmgr_client_id = TEGRA_BWMGR_CLIENT_VI, }; -struct nvhost_device_data t23x_vi0_info = { +static struct nvhost_device_data t23x_vi0_info = { .devfs_name = "vi0", .moduleid = 2, //NVHOST_MODULE_VI, .clocks = { @@ -312,7 +312,7 @@ struct nvhost_device_data t23x_vi0_info = { .post_virt_init = vi5_priv_late_probe, }; -struct nvhost_device_data t23x_vi1_info = { +static struct nvhost_device_data t23x_vi1_info = { .devfs_name = "vi1", .moduleid = 3, //NVHOST_MODULE_VI2, .clocks = {