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ASoC: tegra-alt: Add ape clock support

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'ape' clock must be enabled when AHUB is getting used. So adding
'ape' clock enable/disable support as part of t210 xbar runtime PM.

Change-Id: I55b5d89923c6bfb959d5f1e2b279ea5326e2a660
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/457397
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
This commit is contained in:
Sumit Bhattacharya
2014-08-16 15:26:12 +05:30
committed by Sameer Pujar
parent f33ec6b80b
commit bfbe01c566
1 changed files with 23 additions and 6 deletions
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29
sound/soc/tegra-alt/tegra210_xbar_alt.c
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@@ -49,6 +49,7 @@ static int tegra210_xbar_runtime_suspend(struct device *dev)
regcache_cache_only(xbar->regmap, true); regcache_cache_only(xbar->regmap, true);
clk_disable(xbar->clk); clk_disable(xbar->clk);
clk_disable(xbar->clk_ape);
return 0; return 0;
} }
@@ -57,6 +58,12 @@ static int tegra210_xbar_runtime_resume(struct device *dev)
{ {
int ret; int ret;
ret = clk_enable(xbar->clk_ape);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
ret = clk_enable(xbar->clk); ret = clk_enable(xbar->clk);
if (ret) { if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret); dev_err(dev, "clk_enable failed: %d\n", ret);
@@ -834,23 +841,30 @@ static int tegra210_xbar_probe(struct platform_device *pdev)
goto err_clk_put; goto err_clk_put;
} }
xbar->clk_ape = clk_get_sys(NULL, "ape");
if (IS_ERR(xbar->clk_ape)) {
dev_err(&pdev->dev, "Can't retrieve ape clock\n");
ret = PTR_ERR(xbar->clk_ape);
goto err_clk_put_parent;
}
parent_clk = clk_get_parent(xbar->clk); parent_clk = clk_get_parent(xbar->clk);
if (IS_ERR(parent_clk)) { if (IS_ERR(parent_clk)) {
dev_err(&pdev->dev, "Can't get parent clock for xbar\n"); dev_err(&pdev->dev, "Can't get parent clock for xbar\n");
ret = PTR_ERR(parent_clk); ret = PTR_ERR(parent_clk);
goto err_clk_put; goto err_clk_put_ape;
} }
ret = clk_set_rate(xbar->clk_parent, 24560000); ret = clk_set_rate(xbar->clk_parent, 24560000);
if (ret) { if (ret) {
dev_err(&pdev->dev, "Failed to set clock rate of pll_a_out0\n"); dev_err(&pdev->dev, "Failed to set clock rate of pll_a_out0\n");
goto err_clk_put; goto err_clk_put_ape;
} }
ret = clk_set_parent(xbar->clk, xbar->clk_parent); ret = clk_set_parent(xbar->clk, xbar->clk_parent);
if (ret) { if (ret) {
dev_err(&pdev->dev, "Failed to set parent clock with pll_a_out0\n"); dev_err(&pdev->dev, "Failed to set parent clock with pll_a_out0\n");
goto err_clk_put; goto err_clk_put_ape;
} }
regs = devm_request_and_ioremap(&pdev->dev, pdev->resource); regs = devm_request_and_ioremap(&pdev->dev, pdev->resource);
@@ -865,7 +879,7 @@ static int tegra210_xbar_probe(struct platform_device *pdev)
if (IS_ERR(xbar->regmap)) { if (IS_ERR(xbar->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n"); dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(xbar->regmap); ret = PTR_ERR(xbar->regmap);
goto err_clk_put_parent; goto err_clk_set_parent;
} }
regcache_cache_only(xbar->regmap, true); regcache_cache_only(xbar->regmap, true);
@@ -892,10 +906,12 @@ err_suspend:
tegra210_xbar_runtime_suspend(&pdev->dev); tegra210_xbar_runtime_suspend(&pdev->dev);
err_pm_disable: err_pm_disable:
pm_runtime_disable(&pdev->dev); pm_runtime_disable(&pdev->dev);
err_clk_put_parent:
clk_put(xbar->clk_parent);
err_clk_set_parent: err_clk_set_parent:
clk_set_parent(xbar->clk, parent_clk); clk_set_parent(xbar->clk, parent_clk);
err_clk_put_ape:
clk_put(xbar->clk_ape);
err_clk_put_parent:
clk_put(xbar->clk_parent);
err_clk_put: err_clk_put:
devm_clk_put(&pdev->dev, xbar->clk); devm_clk_put(&pdev->dev, xbar->clk);
err: err:
@@ -912,6 +928,7 @@ static int tegra210_xbar_remove(struct platform_device *pdev)
devm_clk_put(&pdev->dev, xbar->clk); devm_clk_put(&pdev->dev, xbar->clk);
clk_put(xbar->clk_parent); clk_put(xbar->clk_parent);
clk_put(xbar->clk_ape);
return 0; return 0;
} }