mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
tegra: cec: Driver rework
Change write() to work per frame.
Change write() to return -1 on error and set up errno
write() API:
-Userspace is responsible for re-transmission.
-Read from user-space byte by byte, each byte representing
a block, up to 16 bytes as specified by HDMI standard.
-Return 0 on success transmission, -1 otherwise, with errno
setup as follows:
EIO - TX_REGISTER_UNDERRUN, should not happen, otherwise
driver is have serious timing issue.
ECOMM - BUS arbitration failure or anomaly BUS activity.
Transmission is abandoned.
ECONNRESET - For broadcast message only, someone on the BUS
asserted NAK during transmission.
EHOSTUNREACH - For direct message only, message was not ACK'd.
(Required by logical address allocation)
EMSGSIZE - Message size > 16 bit.
EFAULT - Page fault accessing message buffer.
EINTR - call interrupted by singal.
read() API is unchanged, works per packet with no error report.
Change-Id: Iabdd92b5658dd63c7b500a7ec88d79a64c8c0a43
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-on: http://git-master/r/304664
(cherry picked from commit 6ab7a446c4a3e8e4970ceec5a3c715453a24e4a5)
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-on: http://git-master/r/347779
Reviewed-on: http://git-master/r/1164143
(cherry picked from commit 67a6c2d3cfbeeca5cb5ed57aae53f34d07decd4f)
This commit is contained in:
Xia Yang
@@ -1,7 +1,7 @@
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/*
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* drivers/misc/tegra-cec/tegra_cec.c
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*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -53,13 +53,17 @@ int tegra_cec_open(struct inode *inode, struct file *file)
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struct miscdevice *miscdev = file->private_data;
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struct tegra_cec *cec = container_of(miscdev,
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struct tegra_cec, misc_dev);
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int ret = 0;
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dev_dbg(cec->dev, "%s\n", __func__);
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wait_event_interruptible(cec->init_waitq,
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ret = wait_event_interruptible(cec->init_waitq,
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atomic_read(&cec->init_done) == 1);
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if (ret)
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return ret;
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file->private_data = cec;
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return 0;
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return ret;
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}
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int tegra_cec_release(struct inode *inode, struct file *file)
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@@ -71,59 +75,102 @@ int tegra_cec_release(struct inode *inode, struct file *file)
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return 0;
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}
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ssize_t tegra_cec_write(struct file *file, const char __user *buffer,
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static inline void tegra_cec_native_tx(const struct tegra_cec *cec, u32 block)
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{
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writel(block, cec->cec_base + TEGRA_CEC_TX_REGISTER);
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writel(TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY,
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cec->cec_base + TEGRA_CEC_INT_STAT);
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}
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static
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int tegra_cec_native_write_l(struct tegra_cec *cec, const u8 *buf, size_t cnt)
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{
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int ret;
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size_t i;
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u32 start, mode, eom;
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u32 mask;
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/*
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* In case previous transmission was interrupted by signal,
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* driver will try to complete the frame anyway. However,
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* this means we have to wait for it to finish before beginning
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* subsequent transmission.
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*/
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ret = wait_event_interruptible(cec->tx_waitq, cec->tx_wake == 1);
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if (ret)
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return ret;
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mode = TEGRA_CEC_LADDR_MODE(buf[0]) << TEGRA_CEC_TX_REG_ADDR_MODE_SHIFT;
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cec->tx_wake = 0;
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cec->tx_error = 0;
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cec->tx_buf_cur = 0;
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cec->tx_buf_cnt = cnt;
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for (i = 0; i < cnt; i++) {
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start = i == 0 ? (1 << TEGRA_CEC_TX_REG_START_BIT_SHIFT) : 0;
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eom = i == cnt-1 ? (1 << TEGRA_CEC_TX_REG_EOM_SHIFT) : 0;
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cec->tx_buf[i] = start | mode | eom | buf[i];
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}
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mask = readl(cec->cec_base + TEGRA_CEC_INT_MASK);
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writel(mask | TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY,
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cec->cec_base + TEGRA_CEC_INT_MASK);
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ret = wait_event_interruptible(cec->tx_waitq, cec->tx_wake == 1);
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if (!ret)
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ret = cec->tx_error;
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return ret;
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}
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ssize_t tegra_cec_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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u8 tx_buf[TEGRA_CEC_FRAME_MAX_LENGTH];
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struct tegra_cec *cec = file->private_data;
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unsigned long write_buff;
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ssize_t ret;
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count = 4;
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if (count == 0 || count > TEGRA_CEC_FRAME_MAX_LENGTH)
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return -EMSGSIZE;
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wait_event_interruptible(cec->init_waitq,
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ret = wait_event_interruptible(cec->init_waitq,
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atomic_read(&cec->init_done) == 1);
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if (ret)
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return ret;
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if (copy_from_user(&write_buff, buffer, count))
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if (copy_from_user(tx_buf, buf, count))
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return -EFAULT;
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY |
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TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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wait_event_interruptible(cec->tx_waitq, cec->tx_wake == 1);
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writel(write_buff, cec->cec_base + TEGRA_CEC_TX_REGISTER);
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cec->tx_wake = 0;
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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write_buff = 0x00;
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return count;
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mutex_lock(&cec->tx_lock);
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ret = tegra_cec_native_write_l(cec, tx_buf, count);
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mutex_unlock(&cec->tx_lock);
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if (ret)
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return ret;
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else
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return count;
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}
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ssize_t tegra_cec_read(struct file *file, char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct tegra_cec *cec = file->private_data;
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count = 2;
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ssize_t ret;
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wait_event_interruptible(cec->init_waitq,
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count = sizeof(cec->rx_buffer);
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ret = wait_event_interruptible(cec->init_waitq,
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atomic_read(&cec->init_done) == 1);
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if (ret)
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return ret;
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if (cec->rx_wake == 0)
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if (file->f_flags & O_NONBLOCK)
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return -EAGAIN;
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wait_event_interruptible(cec->rx_waitq, cec->rx_wake == 1);
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ret = wait_event_interruptible(cec->rx_waitq, cec->rx_wake == 1);
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if (ret)
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return ret;
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if (copy_to_user(buffer, &(cec->rx_buffer), count))
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return -EFAULT;
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@@ -133,52 +180,100 @@ ssize_t tegra_cec_read(struct file *file, char __user *buffer,
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return count;
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}
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static inline void tegra_cec_error_recovery(struct tegra_cec *cec)
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{
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u32 hw_ctrl;
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hw_ctrl = readl(cec->cec_base + TEGRA_CEC_HW_CONTROL);
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writel(0x0, cec->cec_base + TEGRA_CEC_HW_CONTROL);
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writel(0xFFFFFFFF, cec->cec_base + TEGRA_CEC_INT_STAT);
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writel(hw_ctrl, cec->cec_base + TEGRA_CEC_HW_CONTROL);
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}
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static irqreturn_t tegra_cec_irq_handler(int irq, void *data)
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{
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struct device *dev = data;
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struct tegra_cec *cec = dev_get_drvdata(dev);
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unsigned long status;
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u32 status, mask;
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status = readl(cec->cec_base + TEGRA_CEC_INT_STAT);
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mask = readl(cec->cec_base + TEGRA_CEC_INT_MASK);
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status &= mask;
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if (!status)
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return IRQ_HANDLED;
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goto out;
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if ((status & TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN) ||
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(status & TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED) ||
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(status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) ||
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(status & TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED)) {
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if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) {
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dev_err(dev, "tegra_cec: TX underrun, interrupt timing issue!\n");
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tegra_cec_error_recovery(cec);
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writel(mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY,
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cec->cec_base + TEGRA_CEC_INT_MASK);
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cec->tx_error = -EIO;
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cec->tx_wake = 1;
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wake_up_interruptible(&cec->tx_waitq);
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goto out;
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} else if ((status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) ||
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(status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) {
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tegra_cec_error_recovery(cec);
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writel(mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY,
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cec->cec_base + TEGRA_CEC_INT_MASK);
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cec->tx_error = -ECOMM;
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cec->tx_wake = 1;
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wake_up_interruptible(&cec->tx_waitq);
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goto out;
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} else if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) {
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writel((TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) {
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tegra_cec_error_recovery(cec);
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cec->tx_error = TEGRA_CEC_LADDR_MODE(cec->tx_buf[0]) ?
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-ECONNRESET : -EHOSTUNREACH;
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}
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cec->tx_wake = 1;
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wake_up_interruptible(&cec->tx_waitq);
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goto out;
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} else if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD)
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dev_warn(dev, "tegra_cec: TX NAKed on the fly!\n");
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if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) {
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if (cec->tx_buf_cur == cec->tx_buf_cnt)
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writel(mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY,
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cec->cec_base + TEGRA_CEC_INT_MASK);
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else
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tegra_cec_native_tx(cec,
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cec->tx_buf[cec->tx_buf_cur++]);
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}
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if (status & (TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN |
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TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED |
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TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED)) {
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writel((TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN |
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TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED |
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TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
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writel((TEGRA_CEC_INT_STAT_RX_REGISTER_FULL),
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writel(TEGRA_CEC_INT_STAT_RX_REGISTER_FULL,
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cec->cec_base + TEGRA_CEC_INT_STAT);
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cec->rx_buffer = readw(cec->cec_base + TEGRA_CEC_RX_REGISTER);
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cec->rx_wake = 1;
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wake_up_interruptible(&cec->rx_waitq);
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} else if ((status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) ||
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(status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) ||
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(status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) ||
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(status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) {
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writel((TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY |
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TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) {
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cec->tx_wake = 1;
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wake_up_interruptible(&cec->tx_waitq);
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writel((TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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} else if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) {
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writel((TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED),
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cec->cec_base + TEGRA_CEC_INT_STAT);
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}
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out:
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return IRQ_HANDLED;
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}
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@@ -192,6 +287,11 @@ static const struct file_operations tegra_cec_fops = {
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static void tegra_cec_init(struct tegra_cec *cec)
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{
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cec->rx_wake = 0;
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cec->tx_wake = 1;
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cec->tx_buf_cnt = 0;
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cec->tx_buf_cur = 0;
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cec->tx_error = 0;
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dev_notice(cec->dev, "%s started\n", __func__);
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@@ -202,14 +302,11 @@ static void tegra_cec_init(struct tegra_cec *cec)
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writel(0x00, cec->cec_base + TEGRA_CEC_SW_CONTROL);
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writel((
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(cec->logical_addr << TEGRA_CEC_HW_CONTROL_RX_LOGICAL_ADDRS_MASK) &
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(~TEGRA_CEC_HW_CONTROL_RX_SNOOP) &
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(~TEGRA_CEC_HW_CONTROL_RX_NAK_MODE) &
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(~TEGRA_CEC_HW_CONTROL_TX_NAK_MODE) &
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(~TEGRA_CEC_HW_CONTROL_FAST_SIM_MODE)) |
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(TEGRA_CEC_HW_CONTROL_TX_RX_MODE),
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cec->cec_base + TEGRA_CEC_HW_CONTROL);
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cec->logical_addr = TEGRA_CEC_HWCTRL_RX_LADDR_UNREG;
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writel(TEGRA_CEC_HWCTRL_RX_LADDR(cec->logical_addr) |
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TEGRA_CEC_HWCTRL_TX_NAK_MODE |
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TEGRA_CEC_HWCTRL_TX_RX_MODE,
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cec->cec_base + TEGRA_CEC_HW_CONTROL);
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writel(0x00, cec->cec_base + TEGRA_CEC_INPUT_FILTER);
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@@ -241,17 +338,18 @@ static void tegra_cec_init(struct tegra_cec *cec)
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cec->cec_base + TEGRA_CEC_TX_TIMING_1);
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writel((0x07 << TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_ADDITIONAL_FRAME_MASK) |
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(0x05 << TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_NEW_FRAME_MASK) |
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(0x03 << TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_RETRY_FRAME_MASK),
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(0x05 << TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_NEW_FRAME_MASK) |
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(0x03 << TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_RETRY_FRAME_MASK),
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cec->cec_base + TEGRA_CEC_TX_TIMING_2);
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writel((TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN),
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cec->cec_base + TEGRA_CEC_INT_MASK);
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writel(TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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||||
TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN,
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cec->cec_base + TEGRA_CEC_INT_MASK);
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atomic_set(&cec->init_done, 1);
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wake_up_interruptible(&cec->init_waitq);
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@@ -271,6 +369,9 @@ static ssize_t cec_logical_addr_show(struct device *dev,
|
||||
{
|
||||
struct tegra_cec *cec = dev_get_drvdata(dev);
|
||||
|
||||
if (!atomic_read(&cec->init_done))
|
||||
return -EAGAIN;
|
||||
|
||||
if (buf)
|
||||
return sprintf(buf, "0x%x\n", (u32)cec->logical_addr);
|
||||
return 1;
|
||||
@@ -351,7 +452,7 @@ static int tegra_cec_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
atomic_set(&cec->init_done, 0);
|
||||
cec->logical_addr = TEGRA_CEC_LOGICAL_ADDR;
|
||||
mutex_init(&cec->tx_lock);
|
||||
|
||||
cec->clk = clk_get(&pdev->dev, "cec");
|
||||
|
||||
@@ -365,8 +466,6 @@ static int tegra_cec_probe(struct platform_device *pdev)
|
||||
|
||||
/* set context info. */
|
||||
cec->dev = &pdev->dev;
|
||||
cec->rx_wake = 0;
|
||||
cec->tx_wake = 0;
|
||||
init_waitqueue_head(&cec->rx_waitq);
|
||||
init_waitqueue_head(&cec->tx_waitq);
|
||||
init_waitqueue_head(&cec->init_waitq);
|
||||
@@ -390,7 +489,7 @@ static int tegra_cec_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, cec->tegra_cec_irq,
|
||||
tegra_cec_irq_handler, IRQF_DISABLED, "cec_irq", &pdev->dev);
|
||||
tegra_cec_irq_handler, 0x0, "cec_irq", &pdev->dev);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* drivers/misc/tegra-cec/tegra_cec.h
|
||||
*
|
||||
* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
@@ -16,28 +16,43 @@
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef TEGRA_CEC_H
|
||||
#define TEGRA_CEC_H
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <asm/atomic.h>
|
||||
|
||||
#define TEGRA_CEC_FRAME_MAX_LENGTH 16
|
||||
|
||||
struct tegra_cec {
|
||||
struct device *dev;
|
||||
struct miscdevice misc_dev;
|
||||
struct clk *clk;
|
||||
struct mutex tx_lock;
|
||||
void __iomem *cec_base;
|
||||
int tegra_cec_irq;
|
||||
wait_queue_head_t rx_waitq;
|
||||
wait_queue_head_t tx_waitq;
|
||||
wait_queue_head_t init_waitq;
|
||||
unsigned int rx_wake;
|
||||
unsigned int tx_wake;
|
||||
unsigned short rx_buffer;
|
||||
atomic_t init_done;
|
||||
atomic_t init_done;
|
||||
u16 logical_addr;
|
||||
struct work_struct work;
|
||||
unsigned int rx_wake;
|
||||
unsigned int tx_wake;
|
||||
u16 rx_buffer;
|
||||
long tx_error;
|
||||
u32 tx_buf[TEGRA_CEC_FRAME_MAX_LENGTH];
|
||||
u8 tx_buf_cur;
|
||||
u8 tx_buf_cnt;
|
||||
};
|
||||
static int tegra_cec_remove(struct platform_device *pdev);
|
||||
|
||||
#define TEGRA_CEC_LADDR_BROADCAST 0xF
|
||||
#define TEGRA_CEC_LADDR_MASK 0xF
|
||||
#define TEGRA_CEC_LADDR_WIDTH 4
|
||||
#define TEGRA_CEC_LADDR_MODE(blk) \
|
||||
((blk & TEGRA_CEC_LADDR_MASK) == TEGRA_CEC_LADDR_BROADCAST)
|
||||
|
||||
/*CEC Timing registers*/
|
||||
#define TEGRA_CEC_SW_CONTROL 0X000
|
||||
#define TEGRA_CEC_HW_CONTROL 0X004
|
||||
@@ -55,25 +70,25 @@ static int tegra_cec_remove(struct platform_device *pdev);
|
||||
#define TEGRA_CEC_HW_DEBUG_RX 0X038
|
||||
#define TEGRA_CEC_HW_DEBUG_TX 0X03C
|
||||
|
||||
#define TEGRA_CEC_LOGICAL_ADDR 0x10
|
||||
#define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0xFFFF
|
||||
#define TEGRA_CEC_HWCTRL_RX_LADDR(x) (x<<0)
|
||||
#define TEGRA_CEC_MAX_LOGICAL_ADDR 15
|
||||
#define TEGRA_CEC_HWCTRL_RX_LADDR_UNREG 0x0
|
||||
#define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7FFF
|
||||
#define TEGRA_CEC_HWCTRL_RX_LADDR(x) \
|
||||
((x<<0) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK)
|
||||
#define TEGRA_CEC_HWCTRL_RX_SNOOP (1<<15)
|
||||
#define TEGRA_CEC_HWCTRL_RX_NAK_MODE (1<<16)
|
||||
#define TEGRA_CEC_HWCTRL_TX_NAK_MODE (1<<24)
|
||||
#define TEGRA_CEC_HWCTRL_FAST_SIM_MODE (1<<30)
|
||||
#define TEGRA_CEC_HWCTRL_TX_RX_MODE (1<<31)
|
||||
|
||||
#define TEGRA_CEC_HW_CONTROL_RX_LOGICAL_ADDRS_MASK 0
|
||||
#define TEGRA_CEC_HW_CONTROL_RX_SNOOP (1<<15)
|
||||
#define TEGRA_CEC_HW_CONTROL_RX_NAK_MODE (1<<16)
|
||||
#define TEGRA_CEC_HW_CONTROL_TX_NAK_MODE (1<<24)
|
||||
#define TEGRA_CEC_HW_CONTROL_FAST_SIM_MODE (1<<30)
|
||||
#define TEGRA_CEC_HW_CONTROL_TX_RX_MODE (1<<31)
|
||||
|
||||
#define TEGRA_CEC_INPUT_FILTER_MODE (1<<31)
|
||||
#define TEGRA_CEC_INPUT_FILTER_MODE (1<<31)
|
||||
#define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_MASK 0
|
||||
|
||||
#define TEGRA_CEC_TX_REGISTER_DATA_MASK 0
|
||||
#define TEGRA_CEC_TX_REGISTER_EOM_MASK 8
|
||||
#define TEGRA_CEC_TX_REGISTER_ADDRESS_MODE_MASK 12
|
||||
#define TEGRA_CEC_TX_REGISTER_GENERATE_START_BIT_MASK 16
|
||||
#define TEGRA_CEC_TX_REGISTER_RETRY_FRAME_MASK 17
|
||||
#define TEGRA_CEC_TX_REG_DATA_SHIFT 0
|
||||
#define TEGRA_CEC_TX_REG_EOM_SHIFT 8
|
||||
#define TEGRA_CEC_TX_REG_ADDR_MODE_SHIFT 12
|
||||
#define TEGRA_CEC_TX_REG_START_BIT_SHIFT 16
|
||||
#define TEGRA_CEC_TX_REG_RETRY_BIT_SHIFT 17
|
||||
|
||||
#define TEGRA_CEC_RX_REGISTER_MASK 0
|
||||
#define TEGRA_CEC_RX_REGISTER_EOM (1<<8)
|
||||
@@ -102,8 +117,8 @@ static int tegra_cec_remove(struct platform_device *pdev);
|
||||
#define TEGRA_CEC_TX_TIMING_1_TX_ACK_NAK_BIT_SAMPLE_TIME_MASK 24
|
||||
|
||||
#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_ADDITIONAL_FRAME_MASK 0
|
||||
#define TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_NEW_FRAME_MASK 4
|
||||
#define TEGRA_CEC_TX_TIMING_2_TX_BUS_IDLE_TIME_RETRY_FRAME_MASK 8
|
||||
#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_NEW_FRAME_MASK 4
|
||||
#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_RETRY_FRAME_MASK 8
|
||||
|
||||
#define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY (1<<0)
|
||||
#define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (1<<1)
|
||||
@@ -140,3 +155,5 @@ static int tegra_cec_remove(struct platform_device *pdev);
|
||||
#define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER (1<<26)
|
||||
|
||||
#define TEGRA_CEC_NAME "tegra_cec"
|
||||
|
||||
#endif /* TEGRA_CEC_H */
|
||||
|
||||
Reference in New Issue
Block a user