nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 17:25:35 +03:00
Code Issues Packages Projects Releases Wiki Activity

Misc: pci-dma-test: Remove dead code

Browse Source 
tegra-pcie-dma-test is initially written with DMA programming part of
it. Now DMA driver is available separate and DMA programming part of
this driver conflicts with actual programming and results in unexpected
behaviour. Remove non DMA driver test interaction code.

Bug 4124875

Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2908378
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Change-Id: I0266899ef1a9394b73084191053b35163905617e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2910914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Nagarjuna Kristam
2023-05-22 17:44:59 +05:30
committed by mobile promotions
parent ffda313d72
commit c150e5bd00
1 changed files with 2 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

90
drivers/misc/tegra-pcie-dma-test.c
View File

@@ -22,8 +22,6 @@
#define MODULENAME "pcie_dma_host"
#define EDMA_LIB_TEST 1
struct ep_pvt {
struct pci_dev *pdev;
void __iomem *bar0_virt;
@@ -49,68 +47,21 @@ struct ep_pvt {
static irqreturn_t ep_isr(int irq, void *arg)
{
#ifndef EDMA_LIB_TEST
struct ep_pvt *ep = (struct ep_pvt *)arg;
struct pcie_epf_bar0 *epf_bar0 = (__force struct pcie_epf_bar0 *)ep->bar0_virt;
int bit = 0;
u32 val;
unsigned long wr = DMA_WR_CHNL_MASK, rd = DMA_RD_CHNL_MASK;
val = dma_common_rd(ep->dma_base, DMA_WRITE_INT_STATUS_OFF);
for_each_set_bit(bit, &wr, DMA_WR_CHNL_NUM) {
if (BIT(bit) & val) {
dma_common_wr(ep->dma_base, BIT(bit),
DMA_WRITE_INT_CLEAR_OFF);
epf_bar0->wr_data[bit].crc =
crc32_le(~0,
ep->dma_virt + BAR0_DMA_BUF_OFFSET,
epf_bar0->wr_data[bit].size);
/* Trigger interrupt to endpoint */
writel(epf_bar0->msi_data[bit],
ep->bar0_virt + BAR0_MSI_OFFSET);
}
}
val = dma_common_rd(ep->dma_base, DMA_READ_INT_STATUS_OFF);
for_each_set_bit(bit, &rd, DMA_RD_CHNL_NUM) {
if (BIT(bit) & val) {
dma_common_wr(ep->dma_base, BIT(bit),
DMA_READ_INT_CLEAR_OFF);
epf_bar0->rd_data[bit].crc =
crc32_le(~0,
ep->dma_virt + BAR0_DMA_BUF_OFFSET,
epf_bar0->rd_data[bit].size);
/* Trigger interrupt to endpoint */
writel(epf_bar0->msi_data[DMA_WR_CHNL_NUM + bit],
ep->bar0_virt + BAR0_MSI_OFFSET);
}
}
#else
struct ep_pvt *ep = (struct ep_pvt *)arg;
struct pcie_epf_bar0 *epf_bar0 = (__force struct pcie_epf_bar0 *)ep->bar0_virt;
epf_bar0->wr_data[0].crc = crc32_le(~0, ep->dma_virt + BAR0_DMA_BUF_OFFSET,
epf_bar0->wr_data[0].size);
#endif
return IRQ_HANDLED;
}
static void tegra_pcie_dma_raise_irq(void *p)
{
struct ep_pvt *ep = (struct ep_pvt *)p;
struct pcie_epf_bar0 *epf_bar0 = (__force struct pcie_epf_bar0 *)ep->bar0_virt;
writel(epf_bar0->msi_data[0], ep->bar0_virt + BAR0_MSI_OFFSET);
pr_err("%s: donot support raise IRQ from RP. CRC test if any started may fail.\n",
__func__);
}
extern struct device *naga_pci[];
struct edma_desc {
dma_addr_t src;
dma_addr_t dst;
size_t sz;
};
static struct device *tegra_pci_dma_get_host_bridge_device(struct pci_dev *dev)
{
struct pci_bus *bus = dev->bus;
@@ -259,43 +210,6 @@ static int ep_test_dma_probe(struct pci_dev *pdev,
goto fail_isr;
}
/* Set MSI address and data in DMA registers */
#ifndef EDMA_LIB_TEST
pci_read_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_LO, &val);
dma_common_wr(ep->dma_base, val, DMA_WRITE_DONE_IMWR_LOW_OFF);
dma_common_wr(ep->dma_base, val, DMA_WRITE_ABORT_IMWR_LOW_OFF);
dma_common_wr(ep->dma_base, val, DMA_READ_DONE_IMWR_LOW_OFF);
dma_common_wr(ep->dma_base, val, DMA_READ_ABORT_IMWR_LOW_OFF);
pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_FLAGS, &val_16);
if (val_16 & PCI_MSI_FLAGS_64BIT) {
pci_read_config_dword(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI,
&val);
dma_common_wr(ep->dma_base, val, DMA_WRITE_DONE_IMWR_HIGH_OFF);
dma_common_wr(ep->dma_base, val, DMA_WRITE_ABORT_IMWR_HIGH_OFF);
dma_common_wr(ep->dma_base, val, DMA_READ_DONE_IMWR_HIGH_OFF);
dma_common_wr(ep->dma_base, val, DMA_READ_ABORT_IMWR_HIGH_OFF);
pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_DATA_64,
&val_16);
val = val_16;
val = (val << 16) | val_16;
dma_common_wr(ep->dma_base, val, DMA_WRITE_IMWR_DATA_OFF_BASE);
dma_common_wr(ep->dma_base, val,
DMA_WRITE_IMWR_DATA_OFF_BASE + 0x4);
dma_common_wr(ep->dma_base, val, DMA_READ_IMWR_DATA_OFF_BASE);
} else {
pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_DATA_32,
&val_16);
val = val_16;
val = (val << 16) | val_16;
dma_common_wr(ep->dma_base, val, DMA_WRITE_IMWR_DATA_OFF_BASE);
dma_common_wr(ep->dma_base, val,
DMA_WRITE_IMWR_DATA_OFF_BASE + 0x4);
dma_common_wr(ep->dma_base, val, DMA_READ_IMWR_DATA_OFF_BASE);
}
#endif
ep->dma_virt = dma_alloc_coherent(&pdev->dev, BAR0_SIZE, &ep->dma_phy,
GFP_KERNEL);
if (!ep->dma_virt) {