From c2bf51b5fe558741617cc54d27e70f1deb857147 Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Thu, 28 Apr 2022 17:09:57 +0530
Subject: [PATCH] documentation: Add DT binding document for Tegra PEX pad
 controller

Add Device Tree binding document for the NVIDIA Tegra PEX pad
controller.

Bug 3621816

Change-Id: I6df186f88c5ea48242472a2c30288d9d0942e679
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2704360
GVS: Gerrit_Virtual_Submit
---
 .../pinctrl-tegra194-pexclk-padctrl.yaml      | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml
new file mode 100644
index 00000000..79ea4ae3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra PEX pad controller.
+
+maintainers:
+  - Laxman Dewangan <ldewangan@nvidia.com>
+
+description:
+  Bindings for NVIDIA Tegra PEX pad controller.
+
+properties:
+  compatible:
+    const: nvidia,tegra194-pexclk-padctl
+
+  reg:
+    items:
+      - description: Base address and size of the MISC controller.
+      - description: Base address and size of the PMC controller.
+
+required:
+  - compatible
+  - reg
+
+
+patternProperties:
+  'pinmux-[0-9]*$':
+    type: object
+    patternProperties:
+      '-pins*$':
+        type: object
+        description: |
+          A pinctrl node should contain at least one subnodes representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured either in display or i2c mode.
+        $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+        properties:
+          nvidia,pexclk-single-en:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description:
+              Enable/disable the pex clock in the pad or not. 1 for enable and 0 for disable.
+          pins:
+            enum: [ pexclk ]
+            description:
+              Name of pins.
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pinctrl@3790000 {
+           compatible = "nvidia,tegra194-pexclk-padctl";
+           reg = <0x0 0x03790000 0x0 0x1000>,
+                 <0x0 0x037a0000 0x0 0x1000>;
+
+           pexclk_default: pinmux-0 {
+              pexclk-pins {
+                  pins = "pexclk";
+                  nvidia,pexclk-single-en = <1>;
+              };
+           };
+        };
+     };
+...