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misc: mods: fix bugs and style issues

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* Fixed __user and __iomem pointer types.
* Added __poll_t for poll() return type if possible.
* Fixed error return from poll().
* Fixed init/shutdown in mods_dma.
* Declared internal unit functions as static.
* Assign NULL to init pointers instead of 0.

Bug 3528414

Change-Id: If39a14a429e2cda5d58edb6ffd60fd13693371e6
Signed-off-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2688314
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Chris Dragan
2022-03-28 02:20:25 -07:00
committed by Laxman Dewangan
parent 6fdf0401f7
commit c7fe179f62
19 changed files with 232 additions and 195 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/misc/mods/mods.dts
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods.dts - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

8
drivers/misc/mods/mods.h
View File

@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mods_internal.h - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,
@@ -18,8 +18,4 @@
* If not, see <http://www.gnu.org/licenses/>.
*/
/* Note: the original mods.h which contains ioctls is located in
* include/uapi/misc/mods.h.
*/
#include <uapi/misc/mods.h>

4
drivers/misc/mods/mods_acpi.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_acpi.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -579,7 +579,7 @@ static int mods_acpi_get_ddc(struct mods_client *client,
int esc_mods_eval_acpi_method(struct mods_client *client,
struct MODS_EVAL_ACPI_METHOD *p)
{
return mods_eval_acpi_method(client, p, 0, ACPI_MODS_IGNORE_ACPI_ID);
return mods_eval_acpi_method(client, p, NULL, ACPI_MODS_IGNORE_ACPI_ID);
}
int esc_mods_eval_dev_acpi_method_3(struct mods_client *client,

4
drivers/misc/mods/mods_adsp.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_adsp.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

56
drivers/misc/mods/mods_clock.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_clock.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -70,8 +70,8 @@ static struct device_node *find_clocks_node(const char *name)
void mods_init_clock_api(void)
{
const char *okay_value = "okay";
struct device_node *mods_np = 0;
struct property *pp = 0;
struct device_node *mods_np = NULL;
struct property *pp = NULL;
int size_value = 0;
mods_np = find_clocks_node("mods-clocks");
@@ -137,7 +137,7 @@ static u32 mods_get_clock_handle(struct clk *pclk)
{
struct list_head *head = &mods_clock_handles;
struct list_head *iter;
struct clock_entry *entry = 0;
struct clock_entry *entry = NULL;
u32 handle = 0;
spin_lock(&mods_clock_lock);
@@ -171,7 +171,7 @@ static struct clk *mods_get_clock(u32 handle)
{
struct list_head *head = &mods_clock_handles;
struct list_head *iter = NULL;
struct clk *pclk = 0;
struct clk *pclk = NULL;
spin_lock(&mods_clock_lock);
@@ -247,11 +247,11 @@ failed:
int esc_mods_get_clock_handle(struct mods_client *client,
struct MODS_GET_CLOCK_HANDLE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
struct device_node *mods_np = 0;
struct property *pp = 0;
struct device_node *mods_np = NULL;
struct property *pp = NULL;
LOG_ENT();
@@ -337,7 +337,7 @@ err:
int esc_mods_set_clock_rate(struct mods_client *client,
struct MODS_CLOCK_RATE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -367,7 +367,7 @@ int esc_mods_set_clock_rate(struct mods_client *client,
int esc_mods_get_clock_rate(struct mods_client *client,
struct MODS_CLOCK_RATE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -391,7 +391,7 @@ int esc_mods_get_clock_rate(struct mods_client *client,
int esc_mods_get_clock_max_rate(struct mods_client *client,
struct MODS_CLOCK_RATE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -417,7 +417,7 @@ int esc_mods_get_clock_max_rate(struct mods_client *client,
int esc_mods_set_clock_max_rate(struct mods_client *client,
struct MODS_CLOCK_RATE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -453,8 +453,8 @@ int esc_mods_set_clock_max_rate(struct mods_client *client,
int esc_mods_set_clock_parent(struct mods_client *client,
struct MODS_CLOCK_PARENT *p)
{
struct clk *pclk = 0;
struct clk *pparent = 0;
struct clk *pclk = NULL;
struct clk *pparent = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -487,7 +487,7 @@ int esc_mods_set_clock_parent(struct mods_client *client,
int esc_mods_get_clock_parent(struct mods_client *client,
struct MODS_CLOCK_PARENT *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -513,7 +513,7 @@ int esc_mods_get_clock_parent(struct mods_client *client,
int esc_mods_enable_clock(struct mods_client *client,
struct MODS_CLOCK_HANDLE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -546,7 +546,7 @@ int esc_mods_enable_clock(struct mods_client *client,
int esc_mods_disable_clock(struct mods_client *client,
struct MODS_CLOCK_HANDLE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -570,7 +570,7 @@ int esc_mods_disable_clock(struct mods_client *client,
int esc_mods_is_clock_enabled(struct mods_client *client,
struct MODS_CLOCK_ENABLED *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -632,7 +632,7 @@ error:
int esc_mods_clock_reset_assert(struct mods_client *client,
struct MODS_CLOCK_HANDLE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -642,10 +642,10 @@ int esc_mods_clock_reset_assert(struct mods_client *client,
if (!pclk) {
cl_error("unrecognized clock handle: 0x%x\n", p->clock_handle);
} else {
const char *clk_name = 0;
struct reset_control *prst = 0;
struct device_node *mods_np = 0;
struct property *pp = 0;
const char *clk_name = NULL;
struct reset_control *prst = NULL;
struct device_node *mods_np = NULL;
struct property *pp = NULL;
mods_np = find_clocks_node("mods-clocks");
if (!mods_np || !of_device_is_available(mods_np)) {
@@ -685,7 +685,7 @@ err:
int esc_mods_clock_reset_deassert(struct mods_client *client,
struct MODS_CLOCK_HANDLE *p)
{
struct clk *pclk = 0;
struct clk *pclk = NULL;
int ret = -EINVAL;
LOG_ENT();
@@ -695,10 +695,10 @@ int esc_mods_clock_reset_deassert(struct mods_client *client,
if (!pclk) {
cl_error("unrecognized clock handle: 0x%x\n", p->clock_handle);
} else {
const char *clk_name = 0;
struct reset_control *prst = 0;
struct device_node *mods_np = 0;
struct property *pp = 0;
const char *clk_name = NULL;
struct reset_control *prst = NULL;
struct device_node *mods_np = NULL;
struct property *pp = NULL;
mods_np = find_clocks_node("mods-clocks");
if (!mods_np || !of_device_is_available(mods_np)) {

16
drivers/misc/mods/mods_config.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mods_config.h - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -24,8 +24,8 @@
#define MODS_KERNEL_VERSION LINUX_VERSION_CODE
#if KERNEL_VERSION(2, 6, 30) <= MODS_KERNEL_VERSION && \
KERNEL_VERSION(4, 16, 0) > MODS_KERNEL_VERSION && \
defined(CONFIG_X86)
KERNEL_VERSION(4, 16, 0) > MODS_KERNEL_VERSION && \
defined(CONFIG_X86)
# define MODS_HAS_DMA_OPS 1
#endif
@@ -65,7 +65,7 @@
#endif
#if KERNEL_VERSION(3, 16, 0) <= MODS_KERNEL_VERSION && \
defined(CONFIG_VT_HW_CONSOLE_BINDING)
defined(CONFIG_VT_HW_CONSOLE_BINDING)
# define MODS_HAS_CONSOLE_BINDING 1
#endif
@@ -74,8 +74,8 @@
#endif
#if KERNEL_VERSION(4, 12, 0) <= MODS_KERNEL_VERSION && \
KERNEL_VERSION(4, 13, 0) > MODS_KERNEL_VERSION && \
defined(CONFIG_X86)
KERNEL_VERSION(4, 13, 0) > MODS_KERNEL_VERSION && \
defined(CONFIG_X86)
# define MODS_HAS_ASM_SET_MEMORY_HEADER 1
#endif
@@ -88,6 +88,10 @@
# define MODS_HAS_KERNEL_WRITE
#endif
#if KERNEL_VERSION(4, 16, 0) <= MODS_KERNEL_VERSION
# define MODS_HAS_POLL_T 1
#endif
#if KERNEL_VERSION(4, 17, 0) <= MODS_KERNEL_VERSION
# define MODS_PCIE_FLR_HAS_ERR
#endif

8
drivers/misc/mods/mods_debugfs.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_debugfs.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -606,14 +606,14 @@ int mods_create_debugfs(struct miscdevice *modsdev)
#endif
retval = debugfs_create_file("debug", 0644,
mods_debugfs_dir, 0, &mods_debug_fops);
mods_debugfs_dir, NULL, &mods_debug_fops);
if (IS_ERR(retval)) {
err = -EIO;
goto remove_out;
}
retval = debugfs_create_file("multi_instance", 0644,
mods_debugfs_dir, 0, &mods_mi_fops);
mods_debugfs_dir, NULL, &mods_mi_fops);
if (IS_ERR(retval)) {
err = -EIO;
goto remove_out;
@@ -621,7 +621,7 @@ int mods_create_debugfs(struct miscdevice *modsdev)
#if defined(MODS_HAS_TEGRA) && defined(CONFIG_TEGRA_KFUSE)
retval = debugfs_create_file("kfuse_data", 0444,
mods_debugfs_dir, 0, &mods_kfuse_fops);
mods_debugfs_dir, NULL, &mods_kfuse_fops);
if (IS_ERR(retval)) {
err = -EIO;
goto remove_out;

40
drivers/misc/mods/mods_dma.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_dma.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,
@@ -35,7 +35,7 @@ static DECLARE_BITMAP(dma_info_mask, MODS_DMA_MAX_CHANNEL);
static struct mods_dma_chan_info dma_info_chan_list[MODS_DMA_MAX_CHANNEL];
static DEFINE_SPINLOCK(dma_info_lock);
int mods_get_dma_id(u32 *p_id)
static int mods_get_dma_id(u32 *p_id)
{
u32 id;
@@ -52,14 +52,14 @@ int mods_get_dma_id(u32 *p_id)
return OK;
}
void mods_release_dma_id(u32 id)
static void mods_release_dma_id(u32 id)
{
spin_lock(&dma_info_lock);
clear_bit(id, dma_info_mask);
spin_unlock(&dma_info_lock);
}
int mods_get_chan_by_id(u32 id, struct mods_dma_chan_info **p_dma_chan)
static int mods_get_chan_by_id(u32 id, struct mods_dma_chan_info **p_dma_chan)
{
if (id > MODS_DMA_MAX_CHANNEL)
return -ERANGE;
@@ -69,7 +69,7 @@ int mods_get_chan_by_id(u32 id, struct mods_dma_chan_info **p_dma_chan)
return OK;
}
int mods_init_dma(void)
void mods_init_dma(void)
{
struct mods_dma_chan_info *p_chan_info;
int i;
@@ -79,14 +79,12 @@ int mods_init_dma(void)
rwlock_init(&(p_chan_info->lock));
p_chan_info->in_use = false;
}
return OK;
}
void mods_release_channel(u32 id)
static void mods_release_channel(u32 id)
{
struct mods_dma_chan_info *p_mods_chan;
struct dma_chan *pch = 0;
struct dma_chan *pch = NULL;
if (mods_get_chan_by_id(id, &p_mods_chan) != OK) {
mods_error_printk("get dma channel failed, id %d\n", id);
@@ -117,7 +115,7 @@ void mods_exit_dma(void)
mods_release_channel(i);
}
bool mods_chan_is_inuse(struct mods_dma_chan_info *p_mods_chan)
static bool mods_chan_is_inuse(struct mods_dma_chan_info *p_mods_chan)
{
bool in_use = false;
@@ -129,8 +127,8 @@ bool mods_chan_is_inuse(struct mods_dma_chan_info *p_mods_chan)
return in_use;
}
int mods_get_inuse_chan_by_handle(struct MODS_DMA_HANDLE *p_handle,
struct mods_dma_chan_info **p_mods_chan)
static int mods_get_inuse_chan_by_handle(struct MODS_DMA_HANDLE *p_handle,
struct mods_dma_chan_info **p_mods_chan)
{
int ret;
bool in_use;
@@ -153,8 +151,8 @@ int mods_get_inuse_chan_by_handle(struct MODS_DMA_HANDLE *p_handle,
return OK;
}
int mods_dma_sync_wait(struct MODS_DMA_HANDLE *p_handle,
mods_dma_cookie_t cookie)
static int mods_dma_sync_wait(struct MODS_DMA_HANDLE *p_handle,
mods_dma_cookie_t cookie)
{
int ret = OK;
struct mods_dma_chan_info *p_mods_chan;
@@ -173,9 +171,9 @@ int mods_dma_sync_wait(struct MODS_DMA_HANDLE *p_handle,
return ret;
}
int mods_dma_async_is_tx_complete(struct MODS_DMA_HANDLE *p_handle,
mods_dma_cookie_t cookie,
__u32 *p_is_complete)
static int mods_dma_async_is_tx_complete(struct MODS_DMA_HANDLE *p_handle,
mods_dma_cookie_t cookie,
__u32 *p_is_complete)
{
int ret = OK;
struct mods_dma_chan_info *p_mods_chan;
@@ -486,9 +484,9 @@ int esc_mods_dma_copy_to_user(struct mods_client *client,
(void *)(p->memory_handle_src),
p->num_bytes);
retval = copy_to_user((void *)(p->memory_handle_dst),
(void *)(p->memory_handle_src),
p->num_bytes);
retval = copy_to_user((void __user *)p->memory_handle_dst,
(void *)p->memory_handle_src,
p->num_bytes);
LOG_EXT();

4
drivers/misc/mods/mods_dmabuf.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_dmabuf.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

42
drivers/misc/mods/mods_internal.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mods_internal.h - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -306,24 +306,24 @@ struct NVL_TRAINED {
pr_notice("mods [%u] warning: " fmt, client->client_id, ##args)
struct irq_mask_info {
u32 *dev_irq_mask_reg; /*IRQ mask register, read-only reg*/
u32 *dev_irq_state; /* IRQ status register*/
u32 *dev_irq_disable_reg; /* potentionally a write-only reg*/
u64 irq_and_mask;
u64 irq_or_mask;
u8 mask_type;
void __iomem *dev_irq_mask_reg; /*IRQ mask register, read-only reg*/
void __iomem *dev_irq_state; /* IRQ status register*/
void __iomem *dev_irq_disable_reg; /* potentionally a write-only reg*/
u64 irq_and_mask;
u64 irq_or_mask;
u8 mask_type;
};
struct dev_irq_map {
void *dev_irq_aperture;
u32 apic_irq;
u32 entry;
u8 type;
u8 client_id;
u8 mask_info_cnt;
struct irq_mask_info mask_info[MODS_IRQ_MAX_MASKS];
struct pci_dev *dev;
struct list_head list;
u8 __iomem *dev_irq_aperture;
u32 apic_irq;
u32 entry;
u8 type;
u8 client_id;
u8 mask_info_cnt;
struct irq_mask_info mask_info[MODS_IRQ_MAX_MASKS];
struct pci_dev *dev;
struct list_head list;
};
struct mods_priv {
@@ -337,6 +337,12 @@ struct mods_priv {
struct mutex mtx;
};
#ifdef MODS_HAS_POLL_T
# define POLL_TYPE __poll_t
#else
# define POLL_TYPE unsigned int
#endif
#if ((defined(CONFIG_ARM) || defined(CONFIG_ARM64)) && \
!defined(CONFIG_CPA)) || defined(CONFIG_PPC64)
# define MODS_SET_MEMORY_UC(addr, pages) 0
@@ -397,7 +403,7 @@ struct mutex *mods_get_irq_mutex(void);
struct mods_client *mods_alloc_client(void);
void mods_free_client_interrupts(struct mods_client *client);
void mods_free_client(u8 client_id);
int mods_irq_event_check(u8 client_id);
POLL_TYPE mods_irq_event_check(u8 client_id);
/* mem */
const char *mods_get_prot_str(u8 mem_type);
@@ -643,6 +649,8 @@ int esc_mods_oist_status(struct mods_client *client,
struct MODS_TEGRA_OIST_STATUS *p);
#ifdef CONFIG_DMA_ENGINE
void mods_init_dma(void);
void mods_exit_dma(void);
int esc_mods_dma_request_channel(struct mods_client *client,
struct MODS_DMA_HANDLE *p);
int esc_mods_dma_release_channel(struct mods_client *client,

142
drivers/misc/mods/mods_irq.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_irq.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -152,9 +152,42 @@ static unsigned int get_cur_time(void)
return jiffies_to_usecs(jiffies);
}
static inline int mods_check_interrupt(struct dev_irq_map *t)
static u64 irq_reg_read(const struct irq_mask_info *m, void __iomem *reg)
{
int ii = 0;
if (m->mask_type == MODS_MASK_TYPE_IRQ_DISABLE64)
return readq(reg);
else
return readl(reg);
}
static void irq_reg_write(const struct irq_mask_info *m,
u64 value,
void __iomem *reg)
{
if (m->mask_type == MODS_MASK_TYPE_IRQ_DISABLE64)
writeq(value, reg);
else
writel((u32)value, reg);
}
static u64 read_irq_state(const struct irq_mask_info *m)
{
return irq_reg_read(m, m->dev_irq_state);
}
static u64 read_irq_mask(const struct irq_mask_info *m)
{
return irq_reg_read(m, m->dev_irq_mask_reg);
}
static void write_irq_disable(u64 value, const struct irq_mask_info *m)
{
irq_reg_write(m, value, m->dev_irq_disable_reg);
}
static int mods_check_interrupt(struct dev_irq_map *t)
{
int ii = 0;
int valid = 0;
/* For MSI - we always treat it as pending (must rearm later). */
@@ -163,18 +196,15 @@ static inline int mods_check_interrupt(struct dev_irq_map *t)
return true;
for (ii = 0; ii < t->mask_info_cnt; ii++) {
if (!t->mask_info[ii].dev_irq_state ||
!t->mask_info[ii].dev_irq_mask_reg)
const struct irq_mask_info *const m = &t->mask_info[ii];
if (!m->dev_irq_state || !m->dev_irq_mask_reg)
continue;
/* GPU device */
if (t->mask_info[ii].mask_type == MODS_MASK_TYPE_IRQ_DISABLE64)
valid |= ((*(u64 *)t->mask_info[ii].dev_irq_state &&
*(u64 *)t->mask_info[ii].dev_irq_mask_reg) != 0);
else
valid |= ((*t->mask_info[ii].dev_irq_state &&
*t->mask_info[ii].dev_irq_mask_reg) != 0);
valid |= (read_irq_state(m) && read_irq_mask(m)) != 0;
}
return valid;
}
@@ -183,28 +213,23 @@ static void mods_disable_interrupts(struct dev_irq_map *t)
u32 ii = 0;
for (ii = 0; ii < t->mask_info_cnt; ii++) {
if (t->mask_info[ii].dev_irq_disable_reg &&
t->mask_info[ii].mask_type == MODS_MASK_TYPE_IRQ_DISABLE64) {
if (t->mask_info[ii].irq_and_mask == 0)
*(u64 *)t->mask_info[ii].dev_irq_disable_reg =
t->mask_info[ii].irq_or_mask;
else
*(u64 *)t->mask_info[ii].dev_irq_disable_reg =
(*(u64 *)t->mask_info[ii].dev_irq_mask_reg &
t->mask_info[ii].irq_and_mask) |
t->mask_info[ii].irq_or_mask;
} else if (t->mask_info[ii].dev_irq_disable_reg) {
if (t->mask_info[ii].irq_and_mask == 0) {
*t->mask_info[ii].dev_irq_disable_reg =
t->mask_info[ii].irq_or_mask;
} else {
*t->mask_info[ii].dev_irq_disable_reg =
(*t->mask_info[ii].dev_irq_mask_reg &
t->mask_info[ii].irq_and_mask) |
t->mask_info[ii].irq_or_mask;
}
const struct irq_mask_info *const m = &t->mask_info[ii];
u64 cur_mask = 0;
if (!m->dev_irq_disable_reg)
continue;
if (m->irq_and_mask == 0) {
write_irq_disable(m->irq_or_mask, m);
continue;
}
cur_mask = read_irq_mask(m);
cur_mask &= m->irq_and_mask;
cur_mask |= m->irq_or_mask;
write_irq_disable(cur_mask, m);
}
if ((ii == 0) && t->type == MODS_IRQ_TYPE_CPU) {
mods_debug_printk(DEBUG_ISR,
"disable_irq_nosync %u",
@@ -390,38 +415,43 @@ static int is_nvidia_gpu(struct pci_dev *dev)
}
return false;
}
#endif
#ifdef CONFIG_PCI
static void setup_mask_info(struct dev_irq_map *newmap,
struct MODS_REGISTER_IRQ_4 *p,
struct pci_dev *dev)
{
/* account for legacy adapters */
char *bar = newmap->dev_irq_aperture;
u32 ii = 0;
u8 __iomem *bar = newmap->dev_irq_aperture;
u32 ii = 0;
if ((p->mask_info_cnt == 0) && is_nvidia_gpu(dev)) {
struct irq_mask_info *const m = &newmap->mask_info[0];
newmap->mask_info_cnt = 1;
newmap->mask_info[0].dev_irq_mask_reg = (u32 *)(bar+0x140);
newmap->mask_info[0].dev_irq_disable_reg = (u32 *)(bar+0x140);
newmap->mask_info[0].dev_irq_state = (u32 *)(bar+0x100);
newmap->mask_info[0].irq_and_mask = 0;
newmap->mask_info[0].irq_or_mask = 0;
m->dev_irq_mask_reg = (void __iomem *)(bar + 0x140);
m->dev_irq_disable_reg = (void __iomem *)(bar + 0x140);
m->dev_irq_state = (void __iomem *)(bar + 0x100);
m->irq_and_mask = 0;
m->irq_or_mask = 0;
return;
}
/* setup for new adapters */
newmap->mask_info_cnt = p->mask_info_cnt;
for (ii = 0; ii < p->mask_info_cnt; ii++) {
newmap->mask_info[ii].dev_irq_state =
(u32 *)(bar + p->mask_info[ii].irq_pending_offset);
newmap->mask_info[ii].dev_irq_mask_reg =
(u32 *)(bar + p->mask_info[ii].irq_enabled_offset);
newmap->mask_info[ii].dev_irq_disable_reg =
(u32 *)(bar + p->mask_info[ii].irq_disable_offset);
newmap->mask_info[ii].irq_and_mask = p->mask_info[ii].and_mask;
newmap->mask_info[ii].irq_or_mask = p->mask_info[ii].or_mask;
newmap->mask_info[ii].mask_type = p->mask_info[ii].mask_type;
struct irq_mask_info *const m = &newmap->mask_info[ii];
const struct mods_mask_info2 *const in_m = &p->mask_info[ii];
const u32 pend_offs = in_m->irq_pending_offset;
const u32 stat_offs = in_m->irq_enabled_offset;
const u32 dis_offs = in_m->irq_disable_offset;
m->dev_irq_state = (void __iomem *)(bar + pend_offs);
m->dev_irq_mask_reg = (void __iomem *)(bar + stat_offs);
m->dev_irq_disable_reg = (void __iomem *)(bar + dis_offs);
m->irq_and_mask = in_m->and_mask;
m->irq_or_mask = in_m->or_mask;
m->mask_type = in_m->mask_type;
}
}
#endif
@@ -475,7 +505,7 @@ static int add_irq_map(struct mods_client *client,
newmap->apic_irq = irq;
newmap->dev = dev;
newmap->client_id = client->client_id;
newmap->dev_irq_aperture = 0;
newmap->dev_irq_aperture = NULL;
newmap->mask_info_cnt = 0;
newmap->type = irq_type;
newmap->entry = entry;
@@ -503,7 +533,7 @@ static int add_irq_map(struct mods_client *client,
if ((irq_type == MODS_IRQ_TYPE_INT) &&
(p->aperture_addr != 0) &&
(p->aperture_size != 0)) {
char *bar = ioremap(p->aperture_addr, p->aperture_size);
u8 __iomem *bar = ioremap(p->aperture_addr, p->aperture_size);
if (!bar) {
cl_debug(DEBUG_ISR,
@@ -635,7 +665,7 @@ void mods_cleanup_irq(void)
LOG_EXT();
}
int mods_irq_event_check(u8 client_id)
POLL_TYPE mods_irq_event_check(u8 client_id)
{
struct irq_q_info *q = &client_from_id(client_id)->irq_queue;
unsigned int pos = (1 << (client_id - 1));
@@ -772,7 +802,7 @@ static int mods_free_irqs(struct mods_client *client,
kfree(dpriv->msix_entries);
if (dpriv->msix_entries)
atomic_dec(&client->num_allocs);
dpriv->msix_entries = 0;
dpriv->msix_entries = NULL;
} else if (irq_type == MODS_IRQ_TYPE_MSI) {
pci_disable_msi(dev);
}
@@ -1125,7 +1155,7 @@ static int mods_register_cpu_irq(struct mods_client *client,
}
/* Register interrupt */
err = add_irq_map(client, 0, p, irq, 0);
err = add_irq_map(client, NULL, p, irq, 0);
mutex_unlock(&mp.mtx);
LOG_EXT();
@@ -1182,7 +1212,7 @@ static int mods_unregister_cpu_irq(struct mods_client *client,
/* Delete device interrupt from the list */
list_for_each_entry_safe(del, next, &client->irq_list, list) {
if ((irq == del->apic_irq) && (del->dev == 0)) {
if ((irq == del->apic_irq) && (del->dev == NULL)) {
if (del->type != p->type) {
cl_error("wrong IRQ type passed\n");
mutex_unlock(&mp.mtx);
@@ -1539,7 +1569,7 @@ int esc_mods_map_irq(struct mods_client *client,
void __iomem *wdt_tke = NULL;
int wdt_index;
if (res_tke && res_src) {
if (res_tke && res_src) {
wdt_tke = devm_ioremap(&pdev->dev, res_tke->start,
resource_size(res_tke));
wdt_index = ((res_src->start >> 16) & 0xF) - 0xc;

27
drivers/misc/mods/mods_krnl.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_krnl.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -46,7 +46,7 @@
***********************************************************************/
static int mods_krnl_open(struct inode *, struct file *);
static int mods_krnl_close(struct inode *, struct file *);
static unsigned int mods_krnl_poll(struct file *, poll_table *);
static POLL_TYPE mods_krnl_poll(struct file *, poll_table *);
static int mods_krnl_mmap(struct file *, struct vm_area_struct *);
static long mods_krnl_ioctl(struct file *, unsigned int, unsigned long);
@@ -65,7 +65,7 @@ static const struct file_operations mods_fops = {
#define DEVICE_NAME "mods"
struct miscdevice mods_dev = {
static struct miscdevice mods_dev = {
.minor = MISC_DYNAMIC_MINOR,
.name = DEVICE_NAME,
.fops = &mods_fops
@@ -77,7 +77,7 @@ static pci_ers_result_t mods_pci_error_detected(struct pci_dev *,
static pci_ers_result_t mods_pci_mmio_enabled(struct pci_dev *);
static void mods_pci_resume(struct pci_dev *);
struct pci_error_handlers mods_pci_error_handlers = {
static struct pci_error_handlers mods_pci_error_handlers = {
.error_detected = mods_pci_error_detected,
.mmio_enabled = mods_pci_mmio_enabled,
.resume = mods_pci_resume,
@@ -128,7 +128,7 @@ static int mods_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
static int mods_pci_sriov_configure(struct pci_dev *dev, int numvfs);
#endif
struct pci_driver mods_pci_driver = {
static struct pci_driver mods_pci_driver = {
.name = DEVICE_NAME,
.id_table = mods_pci_table,
.probe = mods_pci_probe,
@@ -467,6 +467,10 @@ static int __init mods_init_module(void)
/* tegra prod */
mods_tegra_prod_init(&mods_dev);
#if defined(CONFIG_DMA_ENGINE)
mods_init_dma();
#endif
#endif
mods_info_printk("*** WARNING: DIAGNOSTIC DRIVER LOADED ***\n");
@@ -492,6 +496,9 @@ static void __exit mods_exit_module(void)
mods_cleanup_irq();
#if defined(MODS_HAS_TEGRA)
#if defined(CONFIG_DMA_ENGINE)
mods_exit_dma();
#endif
smmu_driver_exit();
#endif
@@ -1053,18 +1060,18 @@ static int mods_krnl_close(struct inode *ip, struct file *fp)
return final_err;
}
static unsigned int mods_krnl_poll(struct file *fp, poll_table *wait)
static POLL_TYPE mods_krnl_poll(struct file *fp, poll_table *wait)
{
unsigned int mask = 0;
struct mods_client *client = fp->private_data;
int err;
POLL_TYPE mask = 0;
int err;
if (!validate_client(client))
return -EINVAL;
return POLLERR;
err = mods_check_access_token(client);
if (err < 0)
return err;
return POLLERR;
if (!(fp->f_flags & O_NONBLOCK)) {
cl_debug(DEBUG_ISR_DETAILED, "poll wait\n");

30
drivers/misc/mods/mods_mem.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_mem.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -562,7 +562,7 @@ static void mods_free_pages(struct mods_client *client,
__free_pages(chunk->p_page, chunk->order);
atomic_sub(1u << chunk->order, &client->num_pages);
chunk->p_page = 0;
chunk->p_page = NULL;
}
}
@@ -1017,9 +1017,9 @@ static int get_addr_range(struct mods_client *client,
/* Returns an offset within an allocation deduced from physical address.
* If dma address doesn't belong to the allocation, returns non-zero.
*/
int mods_get_alloc_offset(struct MODS_MEM_INFO *p_mem_info,
u64 dma_addr,
u64 *ret_offs)
static int get_alloc_offset(struct MODS_MEM_INFO *p_mem_info,
u64 dma_addr,
u64 *ret_offs)
{
u32 i;
u64 offset = 0;
@@ -1053,7 +1053,7 @@ struct MODS_MEM_INFO *mods_find_alloc(struct mods_client *client, u64 phys_addr)
p_mem_info = list_entry(plist_iter,
struct MODS_MEM_INFO,
list);
if (!mods_get_alloc_offset(p_mem_info, phys_addr, &offset))
if (!get_alloc_offset(p_mem_info, phys_addr, &offset))
return p_mem_info;
}
@@ -1835,9 +1835,9 @@ int esc_mods_virtual_to_phys(struct mods_client *client,
return OK;
}
if (mods_get_alloc_offset(p_map_mem->p_mem_info,
p_map_mem->dma_addr,
&phys_offs) != OK)
if (get_alloc_offset(p_map_mem->p_mem_info,
p_map_mem->dma_addr,
&phys_offs) != OK)
break;
get_phys_addr.memory_handle =
@@ -1920,15 +1920,15 @@ int esc_mods_phys_to_virtual(struct mods_client *client,
}
/* offset from the beginning of the allocation */
if (mods_get_alloc_offset(p_map_mem->p_mem_info,
p->physical_address,
&offset))
if (get_alloc_offset(p_map_mem->p_mem_info,
p->physical_address,
&offset))
continue;
/* offset from the beginning of the mapping */
if (mods_get_alloc_offset(p_map_mem->p_mem_info,
p_map_mem->dma_addr,
&map_offset))
if (get_alloc_offset(p_map_mem->p_mem_info,
p_map_mem->dma_addr,
&map_offset))
continue;
if ((offset >= map_offset) &&

4
drivers/misc/mods/mods_netdevice.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_net.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

4
drivers/misc/mods/mods_pci.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_pci.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2008-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2008-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

4
drivers/misc/mods/mods_ras.h
View File

@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mods_ras.h - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,

10
drivers/misc/mods/mods_smmu_drv.c
View File

@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_dma_mapping.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,
@@ -72,12 +73,11 @@ static int mods_smmu_driver_probe(struct platform_device *pdev)
err = of_property_read_string(node, "dev-names", &dev_name);
if (err < 0) {
mods_error_printk(
"mods_smmu_driver_probe failed to read dev-names, ret=%d\n",
err);
"smmu probe failed to read dev-names, ret=%d\n", err);
LOG_EXT();
return err;
}
mods_debug_printk(DEBUG_MEM, "mods_smmu_driver_probe: dev-names=%s, dev_idx=%d\n",
mods_debug_printk(DEBUG_MEM, "smmu probe: dev-names=%s, dev_idx=%d\n",
dev_name,
mods_smmu_dev_num);
if (mods_smmu_dev_num < MODS_MAX_SMMU_DEVICES) {

10
drivers/misc/mods/mods_tegradc.c
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_tegradc.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA MODS kernel driver is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License,
@@ -144,9 +144,3 @@ int esc_mods_tegra_dc_config_possible(struct mods_client *client,
LOG_EXT();
return 0;
}
int mods_init_tegradc(void)
{
return 0;
}

10
drivers/misc/mods/mods_tegraprod.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mods_tegraprod.c - This file is part of NVIDIA MODS kernel driver.
* This file is part of NVIDIA MODS kernel driver.
*
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
@@ -663,7 +663,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct mods_smmu_dev *pcie_dev,
return tegra_bpmp_transfer(pcie_dev->bpmp, &msg);
}
int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
static int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
{
#define MAX_DEV_NAME_LEN 32
char dev_name[MAX_DEV_NAME_LEN];
@@ -686,7 +686,7 @@ int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
}
#else
int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
static int uphy_bpmp_pcie_controller_state_set(int controller, int enable)
{
mods_error_printk("bpmp mrq api is not supported\n");
return -ENODEV;
@@ -731,7 +731,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct mods_smmu_dev *pcie_dev,
return tegra_bpmp_transfer(pcie_dev->bpmp, &msg);
}
int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
static int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
{
#define MAX_DEV_NAME_LEN 32
char dev_name[MAX_DEV_NAME_LEN];
@@ -754,7 +754,7 @@ int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
}
#else
int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
static int uphy_bpmp_pcie_set_pll_state(int controller, int enable)
{
mods_error_printk("bpmp mrq api is not supported\n");
return -ENODEV;