diff --git a/sound/soc/tegra-alt/tegra210_dmic_alt.c b/sound/soc/tegra-alt/tegra210_dmic_alt.c
index f733d126..9d3aca61 100644
--- a/sound/soc/tegra-alt/tegra210_dmic_alt.c
+++ b/sound/soc/tegra-alt/tegra210_dmic_alt.c
@@ -520,11 +520,8 @@ static int tegra210_dmic_platform_probe(struct platform_device *pdev)
 			ret = PTR_ERR(dmic->clk_dmic);
 			goto err;
 		}
-#if defined(CONFIG_ARCH_TEGRA_210_SOC)
-		dmic->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
-#else
+
 		dmic->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0");
-#endif
 		if (IS_ERR_OR_NULL(dmic->clk_pll_a_out0)) {
 			dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
 			ret = -ENOENT;
diff --git a/sound/soc/tegra-alt/tegra210_i2s_alt.c b/sound/soc/tegra-alt/tegra210_i2s_alt.c
index 68bb3b94..14e25aa8 100644
--- a/sound/soc/tegra-alt/tegra210_i2s_alt.c
+++ b/sound/soc/tegra-alt/tegra210_i2s_alt.c
@@ -93,7 +93,7 @@ static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
 				dev_err(dev, "Can't set I2S sync clock rate\n");
 				return ret;
 			}
-#if !defined(CONFIG_ARCH_TEGRA_210_SOC)
+
 			ret = clk_set_parent(i2s->clk_audio_sync,
 					i2s->clk_i2s_sync);
 			if (ret) {
@@ -101,7 +101,7 @@ static int tegra210_i2s_set_clock_rate(struct device *dev, int clock_rate)
 					"Can't set parent of i2s audio sync clock\n");
 				return ret;
 			}
-#endif
+
 			ret = clk_set_parent(i2s->clk_i2s, i2s->clk_i2s_source);
 			if (ret) {
 				dev_err(dev, "Can't set parent of I2S clock\n");
@@ -1054,11 +1054,7 @@ static int tegra210_i2s_platform_probe(struct platform_device *pdev)
 			goto err_i2s_sync_clk_put;
 		}
 
-#if defined(CONFIG_ARCH_TEGRA_210_SOC)
-		i2s->clk_i2s_source = clk_get_sys(NULL, "pll_a_out0");
-#else
 		i2s->clk_i2s_source = devm_clk_get(&pdev->dev, "pll_a_out0");
-#endif
 		if (IS_ERR(i2s->clk_i2s_source)) {
 			dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
 			ret = PTR_ERR(i2s->clk_i2s_source);
@@ -1209,11 +1205,7 @@ err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
 err_pll_a_out0_clk_put:
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
-#if defined(CONFIG_ARCH_TEGRA_210_SOC)
-		clk_put(i2s->clk_i2s_source);
-#else
 		devm_clk_put(&pdev->dev, i2s->clk_i2s_source);
-#endif
 err_audio_sync_clk_put:
 	devm_clk_put(&pdev->dev, i2s->clk_audio_sync);
 err_i2s_sync_clk_put:
diff --git a/sound/soc/tegra-alt/tegra210_spdif_alt.c b/sound/soc/tegra-alt/tegra210_spdif_alt.c
index 2324d64e..d6d3b1ed 100644
--- a/sound/soc/tegra-alt/tegra210_spdif_alt.c
+++ b/sound/soc/tegra-alt/tegra210_spdif_alt.c
@@ -171,14 +171,13 @@ static int tegra210_spdif_set_dai_sysclk(struct snd_soc_dai *dai,
 
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
 		if (dir == SND_SOC_CLOCK_OUT) {
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
 			ret = clk_set_parent(spdif->clk_spdif_out,
 						spdif->clk_pll_a_out0);
 			if (ret) {
 				dev_err(dev, "Can't set parent of SPDIF OUT clock\n");
 				return ret;
 			}
-#endif
+
 			ret = clk_set_rate(
 				spdif->clk_spdif_out, spdif_out_clock_rate);
 			if (ret) {
@@ -187,14 +186,13 @@ static int tegra210_spdif_set_dai_sysclk(struct snd_soc_dai *dai,
 				return ret;
 			}
 		} else {
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
 			ret = clk_set_parent(spdif->clk_spdif_in,
 						spdif->clk_pll_p_out0);
 			if (ret) {
 				dev_err(dev, "Can't set parent of SPDIF IN clock\n");
 				return ret;
 			}
-#endif
+
 			ret = clk_set_rate(
 				spdif->clk_spdif_in, spdif_in_clock_rate);
 			if (ret) {
@@ -474,7 +472,6 @@ static int tegra210_spdif_platform_probe(struct platform_device *pdev)
 
 	spdif->soc_data = soc_data;
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) {
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
 		spdif->clk_pll_a_out0 = devm_clk_get(&pdev->dev, "pll_a_out0");
 		if (IS_ERR(spdif->clk_pll_a_out0)) {
 			dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
@@ -488,7 +485,7 @@ static int tegra210_spdif_platform_probe(struct platform_device *pdev)
 			ret = PTR_ERR(spdif->clk_pll_p_out0);
 			goto err_spdif_plla_clk_put;
 		}
-#endif
+
 		spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out");
 		if (IS_ERR(spdif->clk_spdif_out)) {
 			dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
@@ -615,13 +612,11 @@ err_spdif_out_clk_put:
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
 		devm_clk_put(&pdev->dev, spdif->clk_spdif_out);
 err_spdif_pllp_clk_put:
-#if defined(CONFIG_ARCH_TEGRA_18x_SOC)
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
 		devm_clk_put(&pdev->dev, spdif->clk_pll_p_out0);
 err_spdif_plla_clk_put:
 	if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()))
 		devm_clk_put(&pdev->dev, spdif->clk_pll_a_out0);
-#endif
 err:
 	return ret;
 }