nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 17:25:35 +03:00
Code Issues Packages Projects Releases Wiki Activity

SerDes: BHSI-16, BHSI-10: Add Read after write opcode

Browse Source 
Bug 5218749

Change-Id: Iaca83d0c201b746d5e70a4e3717781d0273c55ab
Signed-off-by: Hitesh Khode <hkhode@nvidia.com>
(cherry picked from commit 6ac5c42e80f80f1defb9e8d3f2803f143da4f506)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3341500
Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Hitesh Khode
2025-04-16 00:18:18 +05:30
committed by Jon Hunter
parent 1d5c9f1143
commit cb4010130d
1 changed files with 40 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/video/tegra/dc/bridge/nvdisp_serdes.c
View File

@@ -99,6 +99,7 @@ typedef struct {
} opcode_descriptor_t; } opcode_descriptor_t;
static int32_t op_i2c_write_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload); static int32_t op_i2c_write_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload);
static int32_t op_i2c_read_after_write_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload);
static int32_t op_i2c_read_byte_and_poll(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload); static int32_t op_i2c_read_byte_and_poll(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload);
static int32_t op_i2c_read_byte_compare_print(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload); static int32_t op_i2c_read_byte_compare_print(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload);
static int32_t op_i2c_update_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload); static int32_t op_i2c_update_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload);
@@ -114,6 +115,12 @@ opcode_descriptor_t opcode_desc_table[] = {
.payload_size = SIZE_PAYLOAD_I2C_WRITE_8_SINGLE, .payload_size = SIZE_PAYLOAD_I2C_WRITE_8_SINGLE,
.dispatcher = op_i2c_write_byte, .dispatcher = op_i2c_write_byte,
}, },
{
.description = "i2c read after write single byte",
.opcode = 0x11,
.payload_size = SIZE_PAYLOAD_I2C_WRITE_8_SINGLE,
.dispatcher = op_i2c_read_after_write_byte,
},
{ {
.description = "i2c read single byte", .description = "i2c read single byte",
.opcode = 0x30, .opcode = 0x30,
@@ -221,6 +228,39 @@ static int32_t op_i2c_write_byte(struct i2c_client *client, struct nvdisp_serdes
return nvdisp_serdes_write(priv, slave_addr, reg_addr, payload[OPCODE_OFFSET_I2C_REG_DATA]); return nvdisp_serdes_write(priv, slave_addr, reg_addr, payload[OPCODE_OFFSET_I2C_REG_DATA]);
} }
static int32_t op_i2c_read_after_write_byte(struct i2c_client *client, struct nvdisp_serdes_priv *priv, u8 *payload)
{
u8 slave_addr = payload[OPCODE_OFFSET_I2C_SLAVE_ADDR_LOW];
u32 reg_addr = (payload[OPCODE_OFFSET_I2C_REG_ADDR_LOW]) | (payload[OPCODE_OFFSET_I2C_REG_ADDR_HIGH] << 0x8);
u8 reg_val;
int32_t ret;
ret = nvdisp_serdes_write(priv, slave_addr, reg_addr, payload[OPCODE_OFFSET_I2C_REG_DATA]);
if (ret < 0) {
dev_err(&priv->client->dev,
"%s: nvdisp_serdes_write 0x%02x failed (%d)\n",
__func__, reg_addr, ret);
return ret;
}
/* Read back the value to verify write operation */
ret = nvdisp_serdes_read(priv, slave_addr, reg_addr, &reg_val);
if (ret < 0) {
dev_err(&priv->client->dev,
"%s: nvdisp_serdes_read 0x%02x failed (%d)\n",
__func__, reg_addr, ret);
return ret;
}
if (reg_val != payload[OPCODE_OFFSET_I2C_REG_DATA]) {
dev_err(&priv->client->dev,
"%s: readback verification failed. Expected 0x%02x, got 0x%02x\n",
__func__, payload[OPCODE_OFFSET_I2C_REG_DATA], reg_val);
}
return 0;
}
#define OPCODE_90_OFFSET_POLL_COUNT 5 #define OPCODE_90_OFFSET_POLL_COUNT 5
#define OPCODE_90_OFFSET_PADDING 6 #define OPCODE_90_OFFSET_PADDING 6
#define OPCODE_90_OFFSET_POLL_DELAY_0 7 #define OPCODE_90_OFFSET_POLL_DELAY_0 7