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r8168: Fix -20C 10mbps failure in Mods test

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Issue:
Ethernet mplan stability tests at -20C for 10Mbps fails with rate 15%
Basically the GPHY 10M power saving includes the below parameters,
clock speed down, pll off and reference voltage off.
During debugging it was found that enable/disable pll circuit
frequently when in 10M low data traffic (such as idle mode) may have
a corner case and plays a part in this issue repro.

Fix:
So plloff saving function should be disable (do not have to open it) for nvidia -20C mplan test case.

Bug 3946623

Change-Id: I87ab9b487fe5924ee9ee16bbb14d7f8c19f3a4e7
Signed-off-by: Sushil Kumar Singh <sushilkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2939046
Tested-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
(cherry picked from commit 80f6470d40821bfbad8f8166d22442e949b47173)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2942039
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
This commit is contained in:
Sushil Kumar Singh
2023-07-19 13:01:38 +05:30
committed by mobile promotions
parent 3b116f7c1a
commit cec663aa8d
1 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/net/ethernet/realtek/r8168_n.c
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@@ -24195,7 +24195,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
} }
rtl8168_mdio_write(tp, 0x1F, 0x0A44); rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit( tp, 0x11, BIT_11 ); rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000); rtl8168_mdio_write(tp, 0x1F, 0x0000);
@@ -24248,7 +24251,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
} }
rtl8168_mdio_write(tp, 0x1F, 0x0A44); rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit( tp, 0x11, BIT_11 ); rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000); rtl8168_mdio_write(tp, 0x1F, 0x0000);
if (tp->RequireAdcBiasPatch) { if (tp->RequireAdcBiasPatch) {
@@ -24463,7 +24469,10 @@ rtl8168_hw_phy_config(struct net_device *dev)
} }
} else if (tp->mcfg == CFG_METHOD_35) { } else if (tp->mcfg == CFG_METHOD_35) {
rtl8168_mdio_write(tp, 0x1F, 0x0A44); rtl8168_mdio_write(tp, 0x1F, 0x0A44);
rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11); rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_11 | BIT_7));
rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_11));
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
rtl8168_clear_eth_phy_bit(tp, 0x10, (BIT_0));
rtl8168_mdio_write(tp, 0x1F, 0x0000); rtl8168_mdio_write(tp, 0x1F, 0x0000);