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ufs: Do not use mphy_force_ls_mode clock

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mphy_force_ls_mode clock is only T23x chips.
Kept condition accordingly to use mphy_force_ls_mode
clocks in T23x chips only.

Bug 4199271

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I9b176ec6b1a9fd0ea0d52e857eb011197ef9234e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3145424
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mallikarjun Kasoju
2024-05-22 10:30:10 +00:00
committed by mobile promotions
parent 0475230ef4
commit d260c69c83
1 changed files with 15 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/scsi/ufs/ufs-tegra-common.c
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@@ -579,10 +579,12 @@ static int ufs_tegra_init_mphy_lane_clks(struct ufs_tegra_host *host)
if (err) if (err)
goto out; goto out;
err = ufs_tegra_host_clk_get(dev, "mphy_force_ls_mode", if (host->soc->chip_id != TEGRA264) {
&host->mphy_force_ls_mode); err = ufs_tegra_host_clk_get(dev, "mphy_force_ls_mode",
if (err) &host->mphy_force_ls_mode);
goto out; if (err)
goto out;
}
err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_hs_symb_div", err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_hs_symb_div",
&host->mphy_tx_hs_symb_div); &host->mphy_tx_hs_symb_div);
@@ -1473,7 +1475,7 @@ static int ufs_tegra_hce_enable_notify(struct ufs_hba *hba,
switch (status) { switch (status) {
case PRE_CHANGE: case PRE_CHANGE:
if (tegra_sku_info.platform != TEGRA_PLATFORM_SYSTEM_FPGA) { if (ufs_tegra->soc->chip_id != TEGRA264) {
err = ufs_tegra_host_clk_enable(dev, err = ufs_tegra_host_clk_enable(dev,
"mphy_force_ls_mode", "mphy_force_ls_mode",
ufs_tegra->mphy_force_ls_mode); ufs_tegra->mphy_force_ls_mode);
@@ -1491,7 +1493,7 @@ static int ufs_tegra_hce_enable_notify(struct ufs_hba *hba,
UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0); UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0);
ufs_tegra_ufs_aux_prog(ufs_tegra); ufs_tegra_ufs_aux_prog(ufs_tegra);
ufs_tegra_set_clk_div(hba); ufs_tegra_set_clk_div(hba);
if (tegra_sku_info.platform != TEGRA_PLATFORM_SYSTEM_FPGA) if (ufs_tegra->soc->chip_id != TEGRA264)
clk_disable_unprepare(ufs_tegra->mphy_force_ls_mode); clk_disable_unprepare(ufs_tegra->mphy_force_ls_mode);
if (ufs_tegra->soc->chip_id >= TEGRA234) if (ufs_tegra->soc->chip_id >= TEGRA234)
ufs_tegra_ufs_mmio_axi(hba); ufs_tegra_ufs_mmio_axi(hba);
@@ -2039,12 +2041,14 @@ static int ufs_tegra_init(struct ufs_hba *hba)
err = ufs_tegra_init_uphy_pll3(ufs_tegra); err = ufs_tegra_init_uphy_pll3(ufs_tegra);
if (err) if (err)
goto out_host_free; goto out_host_free;
err = ufs_tegra_host_clk_enable(dev, "mphy_force_ls_mode", if (ufs_tegra->soc->chip_id != TEGRA264) {
err = ufs_tegra_host_clk_enable(dev, "mphy_force_ls_mode",
ufs_tegra->mphy_force_ls_mode); ufs_tegra->mphy_force_ls_mode);
if (err) if (err)
goto out_host_free; goto out_host_free;
usleep_range(1000, 2000); usleep_range(1000, 2000);
clk_disable_unprepare(ufs_tegra->mphy_force_ls_mode); clk_disable_unprepare(ufs_tegra->mphy_force_ls_mode);
}
usleep_range(1000, 2000); usleep_range(1000, 2000);
enable_ufs_clk: enable_ufs_clk: