nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-23 01:31:30 +03:00
Code Issues Packages Projects Releases Wiki Activity

drm/tegra: Update to UAPI v5

Browse Source 
Update the tegra-drm driver to the 'Host1x/Tegra UAPI v5' series [0].
This fixes a few minor bugs found in the previous series.

[0] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=223684

Bug 200687525

Change-Id: I270016756b6b689c1fada208896cee81223e7042
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2469984
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Jon Hunter
2021-01-12 10:49:02 +00:00
committed by Laxman Dewangan
parent d088bfa37d
commit d3ea27d381
5 changed files with 48 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/drm/tegra/uapi/firewall.c
View File

@@ -12,6 +12,7 @@ struct tegra_drm_firewall {
u32 *data;
u32 pos;
u32 end;
u32 class;
};
static int fw_next(struct tegra_drm_firewall *fw, u32 *word)
@@ -51,8 +52,8 @@ static int fw_check_reg(struct tegra_drm_firewall *fw, u32 offset)
if (!fw->client->ops->is_addr_reg)
return 0;
is_addr = fw->client->ops->is_addr_reg(
fw->client->base.dev, fw->client->base.class, offset);
is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
offset);
if (!is_addr)
return 0;
@@ -97,14 +98,25 @@ static int fw_check_regs_imm(struct tegra_drm_firewall *fw, u32 offset)
{
bool is_addr;
is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev,
fw->client->base.class, offset);
is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
offset);
if (is_addr)
return -EINVAL;
return 0;
}
static int fw_check_class(struct tegra_drm_firewall *fw, u32 class)
{
if (!fw->client->ops->is_valid_class)
return -EINVAL;
if (!fw->client->ops->is_valid_class(class))
return -EINVAL;
return 0;
}
enum {
HOST1X_OPCODE_SETCLASS = 0x00,
HOST1X_OPCODE_INCR = 0x01,
@@ -124,7 +136,8 @@ enum {
};
int tegra_drm_fw_validate(struct tegra_drm_client *client, u32 *data, u32 start,
u32 words, struct tegra_drm_submit_data *submit)
u32 words, struct tegra_drm_submit_data *submit,
u32 *job_class)
{
struct tegra_drm_firewall fw = {
.submit = submit,
@@ -132,13 +145,14 @@ int tegra_drm_fw_validate(struct tegra_drm_client *client, u32 *data, u32 start,
.data = data,
.pos = start,
.end = start+words,
.class = *job_class,
};
bool payload_valid = false;
u32 payload;
int err;
while (fw.pos != fw.end) {
u32 word, opcode, offset, count, mask;
u32 word, opcode, offset, count, mask, class;
err = fw_next(&fw, &word);
if (err)
@@ -147,6 +161,16 @@ int tegra_drm_fw_validate(struct tegra_drm_client *client, u32 *data, u32 start,
opcode = (word & 0xf0000000) >> 28;
switch (opcode) {
case HOST1X_OPCODE_SETCLASS:
offset = word >> 16 & 0xfff;
mask = word & 0x3f;
class = (word >> 6) & 0x3ff;
err = fw_check_class(&fw, class);
fw.class = class;
*job_class = class;
if (!err)
err = fw_check_regs_mask(&fw, offset, mask);
break;
case HOST1X_OPCODE_INCR:
offset = (word >> 16) & 0xfff;
count = word & 0xffff;