diff --git a/drivers/video/tegra/host/pva/fw_include/pva-fw-address-map.h b/drivers/video/tegra/host/pva/fw_include/pva-fw-address-map.h
index a5243409..4964479c 100644
--- a/drivers/video/tegra/host/pva/fw_include/pva-fw-address-map.h
+++ b/drivers/video/tegra/host/pva/fw_include/pva-fw-address-map.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022-2023, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2022-2024, NVIDIA Corporation.  All rights reserved.
  */
 
 #ifndef PVA_FW_ADDRESS_MAP_H
@@ -114,4 +114,31 @@
  */
 #define FW_SHARED_MEMORY_START                 2147483648 //0x80000000
 
+/**
+ * @defgroup PVA_HYP_SCR_VALUES
+ *
+ * @brief Following macros specify SCR firewall values that are expected to be
+ * programmed by Hypervisor.
+ * @{
+ */
+/**
+ * @brief EVP SCR firewall to enable only CCPLEX read/write access.
+ */
+#define PVA_EVP_SCR_VAL 0x19000202
+
+/**
+ * @brief PRIV SCR firewall to enable only CCPLEX and R5 read/write access.
+ */
+#define PVA_PRIV_SCR_VAL 0x1F008282
+
+/**
+ * @brief CCQ SCR firewall to enable only CCPLEX write access and R5 read access.
+ */
+#define PVA_CCQ_SCR_VAL 0x19000280
+
+/**
+ * @brief CCQ SCR firewall to enable only CCPLEX read access and R5 read/write access.
+ */
+#define PVA_STATUS_CTL_SCR_VAL 0x1F008082
+/** @} */
 #endif
diff --git a/drivers/video/tegra/host/pva/hw_cfg_pva_v2.h b/drivers/video/tegra/host/pva/hw_cfg_pva_v2.h
index c6ffde85..a864faeb 100644
--- a/drivers/video/tegra/host/pva/hw_cfg_pva_v2.h
+++ b/drivers/video/tegra/host/pva/hw_cfg_pva_v2.h
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
- *
+ * Copyright (c) 2019-2024, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
  * Function naming determines intended use:
  *
  *     <x>_r(void) : Returns the offset for register <x>.
@@ -107,6 +109,21 @@ static inline u32 v2_cfg_priv_ar2_end_r(void)
 	return V2_ADDRESS_CONTROL_BASE + 0x34U;
 }
 
+static inline u32 cfg_scr_status_ctrl_r(void)
+{
+	return (V2_ADDRESS_CONTROL_BASE + 0x8000U);
+}
+
+static inline u32 cfg_scr_priv_0_r(void)
+{
+	return (V2_ADDRESS_CONTROL_BASE + 0x8008U);
+}
+
+static inline u32 cfg_scr_ccq_ctrl_r(void)
+{
+	return (V2_ADDRESS_CONTROL_BASE + 0x8010U);
+}
+
 #define V2_CFG_CCQ_BASE 0x260000U
 #define V2_CFG_CCQ_SIZE 0x010000U
 
diff --git a/drivers/video/tegra/host/pva/hw_evp_pva.h b/drivers/video/tegra/host/pva/hw_evp_pva.h
index 97b6b5b7..1d12b25d 100644
--- a/drivers/video/tegra/host/pva/hw_evp_pva.h
+++ b/drivers/video/tegra/host/pva/hw_evp_pva.h
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
- *
+ * Copyright (c) 2016-2024, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/*
  * Function naming determines intended use:
  *
  *     <x>_r(void) : Returns the offset for register <x>.
@@ -70,4 +72,8 @@ static inline u32 evp_fiq_addr_r(void)
 {
 	return 0x3c;
 }
+static inline u32 evp_scr_r(void)
+{
+	return 0x40U;
+}
 #endif
diff --git a/drivers/video/tegra/host/pva/pva.c b/drivers/video/tegra/host/pva/pva.c
index 1a61856c..347910ac 100644
--- a/drivers/video/tegra/host/pva/pva.c
+++ b/drivers/video/tegra/host/pva/pva.c
@@ -366,6 +366,11 @@ static int pva_init_fw(struct platform_device *pdev)
 		host1x_writel(pdev,
 			      cfg_priv_ar1_usegreg_r(pva->version),
 			      0xFFFFFFFF);
+
+		host1x_writel(pdev, evp_scr_r(), PVA_EVP_SCR_VAL);
+		host1x_writel(pdev, cfg_scr_status_ctrl_r(), PVA_STATUS_CTL_SCR_VAL);
+		host1x_writel(pdev, cfg_scr_priv_0_r(), PVA_PRIV_SCR_VAL);
+		host1x_writel(pdev, cfg_scr_ccq_ctrl_r(), PVA_CCQ_SCR_VAL);
 	} else {
 		host1x_writel(pdev,
 			      cfg_priv_ar1_lsegreg_r(pva->version),