mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 17:25:35 +03:00
nvadsp: Fix build issues and enable
Fix build issues for nvadsp in OOT kernel and enable the build.
- Below files copied from kernel/nvidia/include/linux/
- tegra_nvadsp.h (72af3e78a6aff0fa250e9fd36b8414264d0e4c9a)
- tegra-firmwares.h (700223e52f49f300664dd91335fa11111af733aa)
- tegra-hsp.h (988be8f05033e1d728e046e918b506d829106082)
- Below file copied from kernel/nvidia/include/uapi/misc/
- adsp_console_ioctl.h (72af3e78a6aff0fa250e9fd36b8414264d0e4c9a)
- Functions that needs additional AGIC APIs not supported in upstream
are pushed under macro CONFIG_AGIC_EXT_APIS
- T210 chip_data and references removed
Bug 4164138
Bug 3682950
Change-Id: I5dfb570e578ca3631896de7350cea66698612568
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2971924
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Viswanath L
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101
include/linux/tegra-firmwares.h
Normal file
101
include/linux/tegra-firmwares.h
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@@ -0,0 +1,101 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA_FIRMWARES_H
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#define __TEGRA_FIRMWARES_H
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/*
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* max size of version string
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*/
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#define TFW_VERSION_MAX_SIZE 256
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#if IS_ENABLED(CONFIG_TEGRA_FIRMWARES_CLASS)
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struct device *tegrafw_register(const char *name,
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const u32 flags,
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ssize_t (*reader)(struct device *dev, char *, size_t),
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const char *string);
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void tegrafw_unregister(struct device *fwdev);
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struct device *devm_tegrafw_register(struct device *dev,
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const char *name,
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const u32 flags,
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ssize_t (*reader)(struct device *dev, char *, size_t),
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const char *string);
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void devm_tegrafw_unregister(struct device *dev, struct device *fwdev);
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void tegrafw_invalidate(struct device *fwdev);
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struct device *devm_tegrafw_register_dt_string(struct device *dev,
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const char *name,
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const char *path,
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const char *property);
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#else
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static inline struct device *tegrafw_register(const char *name,
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const u32 flags,
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ssize_t (*reader)(struct device *, char *, size_t),
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const char *string)
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{
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return ERR_PTR(-ENOTSUPP);
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}
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static inline void tegrafw_unregister(struct device *fwdev)
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{
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}
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static inline void tegrafw_invalidate(struct device *fwdev)
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{
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}
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static inline struct device *devm_tegrafw_register(struct device *dev,
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const char *name,
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const u32 flags,
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ssize_t (*reader)(struct device *dev, char *, size_t),
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const char *string)
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{
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return ERR_PTR(-ENOTSUPP);
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}
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static inline void devm_tegrafw_unregister(struct device *dev,
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struct device *fwdev)
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{
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}
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static inline
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struct device *devm_tegrafw_register_dt_string(struct device *dev,
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const char *name,
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const char *path,
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const char *property)
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{
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return ERR_PTR(-ENOTSUPP);
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}
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#endif /* IS_ENABLED(...) */
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enum {
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TFW_NORMAL = 0x0000,
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TFW_DONT_CACHE = 0x0001,
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TFW_MAX = 0xFFFF,
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};
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static inline struct device *tegrafw_register_string(const char *name,
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const char *string)
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{
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return tegrafw_register(name, TFW_NORMAL, NULL, string);
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}
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static inline struct device *devm_tegrafw_register_string(struct device *dev,
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const char *name,
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const char *string)
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{
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return devm_tegrafw_register(dev, name, TFW_NORMAL, NULL, string);
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}
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static inline struct device *tegrafw_register_dt_string(const char *name,
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const char *path,
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const char *property)
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{
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return devm_tegrafw_register_dt_string(NULL, name, path, property);
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}
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#endif /* __TEGRA_FIRMWARES_CLASS */
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121
include/linux/tegra-hsp.h
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121
include/linux/tegra-hsp.h
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@@ -0,0 +1,121 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _LINUX_TEGRA_HSP_H
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#define _LINUX_TEGRA_HSP_H
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#include <linux/types.h>
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enum tegra_hsp_master {
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HSP_FIRST_MASTER = 1,
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/* secure */
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HSP_MASTER_SECURE_CCPLEX = HSP_FIRST_MASTER,
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HSP_MASTER_SECURE_DPMU,
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HSP_MASTER_SECURE_BPMP,
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HSP_MASTER_SECURE_SPE,
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HSP_MASTER_SECURE_SCE,
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HSP_MASTER_SECURE_DMA,
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HSP_MASTER_SECURE_TSECA,
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HSP_MASTER_SECURE_TSECB,
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HSP_MASTER_SECURE_JTAGM,
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HSP_MASTER_SECURE_CSITE,
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HSP_MASTER_SECURE_APE,
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/* non-secure */
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HSP_MASTER_CCPLEX = HSP_FIRST_MASTER + 16,
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HSP_MASTER_DPMU,
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HSP_MASTER_BPMP,
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HSP_MASTER_SPE,
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HSP_MASTER_SCE,
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HSP_MASTER_DMA,
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HSP_MASTER_TSECA,
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HSP_MASTER_TSECB,
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HSP_MASTER_JTAGM,
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HSP_MASTER_CSITE,
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HSP_MASTER_APE,
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HSP_LAST_MASTER = HSP_MASTER_APE,
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};
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enum tegra_hsp_doorbell {
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HSP_FIRST_DB = 0,
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HSP_DB_DPMU = HSP_FIRST_DB,
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HSP_DB_CCPLEX,
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HSP_DB_CCPLEX_TZ,
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HSP_DB_BPMP,
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HSP_DB_SPE,
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HSP_DB_SCE,
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HSP_DB_APE,
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HSP_LAST_DB = HSP_DB_APE,
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HSP_NR_DBS,
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};
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typedef void (*db_handler_t)(void *data);
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int tegra_hsp_init(void);
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int tegra_hsp_db_enable_master(enum tegra_hsp_master master);
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int tegra_hsp_db_disable_master(enum tegra_hsp_master master);
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int tegra_hsp_db_ring(enum tegra_hsp_doorbell dbell);
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int tegra_hsp_db_can_ring(enum tegra_hsp_doorbell dbell);
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int tegra_hsp_db_add_handler(int master, db_handler_t handler, void *data);
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int tegra_hsp_db_del_handler(int master);
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#define tegra_hsp_find_master(mask, master) ((mask) & (1 << (master)))
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typedef void (*tegra_hsp_sm_notify)(void *, u32);
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struct tegra_hsp_sm_tx;
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struct tegra_hsp_sm_rx;
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struct tegra_hsp_ss;
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struct tegra_hsp_sm_pair {
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struct tegra_hsp_sm_rx *rx;
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struct tegra_hsp_sm_tx *tx;
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};
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struct tegra_hsp_sm_pair *of_tegra_hsp_sm_pair_request(
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const struct device_node *np, u32 index,
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tegra_hsp_sm_notify full_notify,
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tegra_hsp_sm_notify empty_notify,
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void *data);
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struct tegra_hsp_sm_pair *of_tegra_hsp_sm_pair_by_name(
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struct device_node *np, char const *name,
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tegra_hsp_sm_notify full_notify,
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tegra_hsp_sm_notify empty_notify,
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void *data);
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void tegra_hsp_sm_pair_free(struct tegra_hsp_sm_pair *pair);
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void tegra_hsp_sm_pair_write(const struct tegra_hsp_sm_pair *pair, u32 value);
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bool tegra_hsp_sm_pair_is_empty(const struct tegra_hsp_sm_pair *pair);
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void tegra_hsp_sm_pair_enable_empty_notify(struct tegra_hsp_sm_pair *pair);
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struct tegra_hsp_sm_tx *of_tegra_hsp_sm_tx_by_name(
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struct device_node *np, char const *name,
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tegra_hsp_sm_notify notify, void *data);
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void tegra_hsp_sm_tx_free(struct tegra_hsp_sm_tx *tx);
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bool tegra_hsp_sm_tx_is_empty(const struct tegra_hsp_sm_tx *tx);
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void tegra_hsp_sm_tx_write(const struct tegra_hsp_sm_tx *tx, u32 value);
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void tegra_hsp_sm_tx_enable_notify(struct tegra_hsp_sm_tx *tx);
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struct tegra_hsp_sm_rx *of_tegra_hsp_sm_rx_by_name(
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struct device_node *np, char const *name,
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tegra_hsp_sm_notify notify, void *data);
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void tegra_hsp_sm_rx_free(struct tegra_hsp_sm_rx *rx);
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bool tegra_hsp_sm_rx_is_empty(const struct tegra_hsp_sm_rx *rx);
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struct tegra_hsp_ss *of_tegra_hsp_ss_by_name(
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struct device_node *np, char const *name);
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void tegra_hsp_ss_free(struct tegra_hsp_ss *ss);
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u32 tegra_hsp_ss_status(const struct tegra_hsp_ss *ss);
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void tegra_hsp_ss_set(const struct tegra_hsp_ss *ss, u32 bits);
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void tegra_hsp_ss_clr(const struct tegra_hsp_ss *ss, u32 bits);
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#endif
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393
include/linux/tegra_nvadsp.h
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393
include/linux/tegra_nvadsp.h
Normal file
@@ -0,0 +1,393 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __LINUX_TEGRA_NVADSP_H
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#define __LINUX_TEGRA_NVADSP_H
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#include <linux/types.h>
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#include <linux/timer.h>
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#include <linux/device.h>
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#include <linux/wait.h>
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/list.h>
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#include <linux/completion.h>
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struct nvadsp_platform_data {
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phys_addr_t co_pa;
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unsigned long co_size;
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};
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typedef int status_t;
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/*
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* Shared Semaphores
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*/
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typedef struct {
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int magic; /* 'ssem' */
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uint8_t id;
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wait_queue_head_t wait;
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struct timer_list timer;
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} nvadsp_shared_sema_t;
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nvadsp_shared_sema_t *
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nvadsp_shared_sema_init(uint8_t nvadsp_shared_sema_id);
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status_t nvadsp_shared_sema_destroy(nvadsp_shared_sema_t *);
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status_t nvadsp_shared_sema_acquire(nvadsp_shared_sema_t *);
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status_t nvadsp_shared_sema_release(nvadsp_shared_sema_t *);
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/*
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* Arbitrated Semaphores
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*/
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typedef struct {
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int magic; /* 'asem' */
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uint8_t id;
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wait_queue_head_t wait;
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struct completion comp;
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} nvadsp_arb_sema_t;
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nvadsp_arb_sema_t *nvadsp_arb_sema_init(uint8_t nvadsp_arb_sema_id);
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status_t nvadsp_arb_sema_destroy(nvadsp_arb_sema_t *);
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status_t nvadsp_arb_sema_acquire(nvadsp_arb_sema_t *);
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status_t nvadsp_arb_sema_release(nvadsp_arb_sema_t *);
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/*
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* Mailbox Queue
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*/
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#define NVADSP_MBOX_QUEUE_SIZE 32
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#define NVADSP_MBOX_QUEUE_SIZE_MASK (NVADSP_MBOX_QUEUE_SIZE - 1)
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struct nvadsp_mbox_queue {
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uint32_t array[NVADSP_MBOX_QUEUE_SIZE];
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uint16_t head;
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uint16_t tail;
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uint16_t count;
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struct completion comp;
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spinlock_t lock;
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};
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status_t nvadsp_mboxq_enqueue(struct nvadsp_mbox_queue *, uint32_t);
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/*
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* Mailbox
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*/
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#define NVADSP_MBOX_NAME_MAX 16
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#define NVADSP_MBOX_NAME_MAX_STR (NVADSP_MBOX_NAME_MAX + 1)
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typedef status_t (*nvadsp_mbox_handler_t)(uint32_t, void *);
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struct nvadsp_mbox {
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uint16_t id;
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char name[NVADSP_MBOX_NAME_MAX_STR];
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struct nvadsp_mbox_queue recv_queue;
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nvadsp_mbox_handler_t handler;
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#ifdef CONFIG_MBOX_ACK_HANDLER
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nvadsp_mbox_handler_t ack_handler;
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#endif
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void *hdata;
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};
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#define NVADSP_MBOX_SMSG 0x1
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#define NVADSP_MBOX_LMSG 0x2
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status_t nvadsp_mbox_open(struct nvadsp_mbox *mbox, uint16_t *mid,
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const char *name, nvadsp_mbox_handler_t handler,
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void *hdata);
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status_t nvadsp_mbox_send(struct nvadsp_mbox *mbox, uint32_t data,
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uint32_t flags, bool block, unsigned int timeout);
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status_t nvadsp_mbox_recv(struct nvadsp_mbox *mbox, uint32_t *data, bool block,
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unsigned int timeout);
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status_t nvadsp_mbox_close(struct nvadsp_mbox *mbox);
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#ifdef CONFIG_MBOX_ACK_HANDLER
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static inline void register_ack_handler(struct nvadsp_mbox *mbox,
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nvadsp_mbox_handler_t handler)
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{
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mbox->ack_handler = handler;
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}
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#endif
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/*
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* Circular Message Queue
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*/
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typedef struct _msgq_message_t {
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int32_t size; /* size of payload in words */
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int32_t payload[1]; /* variable length payload */
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} msgq_message_t;
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#define MSGQ_MESSAGE_HEADER_SIZE \
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(sizeof(msgq_message_t) - sizeof(((msgq_message_t *)0)->payload))
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#define MSGQ_MESSAGE_HEADER_WSIZE \
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(MSGQ_MESSAGE_HEADER_SIZE / sizeof(int32_t))
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typedef struct _msgq_t {
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int32_t size; /* queue size in words */
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int32_t write_index; /* queue write index */
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int32_t read_index; /* queue read index */
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int32_t queue[1]; /* variable length queue */
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} msgq_t;
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#define MSGQ_HEADER_SIZE (sizeof(msgq_t) - sizeof(((msgq_t *)0)->queue))
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#define MSGQ_HEADER_WSIZE (MSGQ_HEADER_SIZE / sizeof(int32_t))
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#define MSGQ_MAX_QUEUE_WSIZE (8192 - MSGQ_HEADER_WSIZE)
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#define MSGQ_MSG_WSIZE(x) \
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(((sizeof(x) + sizeof(int32_t) - 1) & (~(sizeof(int32_t)-1))) >> 2)
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#define MSGQ_MSG_PAYLOAD_WSIZE(x) \
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(MSGQ_MSG_WSIZE(x) - MSGQ_MESSAGE_HEADER_WSIZE)
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void msgq_init(msgq_t *msgq, int32_t size);
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int32_t msgq_queue_message(msgq_t *msgq, const msgq_message_t *message);
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int32_t msgq_dequeue_message(msgq_t *msgq, msgq_message_t *message);
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#define msgq_discard_message(msgq) msgq_dequeue_message(msgq, NULL)
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/*
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* DRAM Sharing
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*/
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typedef dma_addr_t nvadsp_iova_addr_t;
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typedef enum dma_data_direction nvadsp_data_direction_t;
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nvadsp_iova_addr_t
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nvadsp_dram_map_single(struct device *nvadsp_dev,
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void *cpu_addr, size_t size,
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nvadsp_data_direction_t direction);
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void
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nvadsp_dram_unmap_single(struct device *nvadsp_dev,
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nvadsp_iova_addr_t iova_addr, size_t size,
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nvadsp_data_direction_t direction);
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nvadsp_iova_addr_t
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nvadsp_dram_map_page(struct device *nvadsp_dev,
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struct page *page, unsigned long offset, size_t size,
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nvadsp_data_direction_t direction);
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void
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nvadsp_dram_unmap_page(struct device *nvadsp_dev,
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nvadsp_iova_addr_t iova_addr, size_t size,
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nvadsp_data_direction_t direction);
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void
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nvadsp_dram_sync_single_for_cpu(struct device *nvadsp_dev,
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nvadsp_iova_addr_t iova_addr, size_t size,
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nvadsp_data_direction_t direction);
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void
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nvadsp_dram_sync_single_for_device(struct device *nvadsp_dev,
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nvadsp_iova_addr_t iova_addr, size_t size,
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nvadsp_data_direction_t direction);
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/*
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* ADSP OS
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*/
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typedef const void *nvadsp_os_handle_t;
|
||||
|
||||
void nvadsp_adsp_init(void);
|
||||
int __must_check nvadsp_os_load(void);
|
||||
int __must_check nvadsp_os_start(void);
|
||||
void nvadsp_os_stop(void);
|
||||
int __must_check nvadsp_os_suspend(void);
|
||||
void dump_adsp_sys(void);
|
||||
void nvadsp_get_os_version(char *, int);
|
||||
int adsp_usage_set(unsigned int val);
|
||||
unsigned int adsp_usage_get(void);
|
||||
/*
|
||||
* ADSP TSC
|
||||
*/
|
||||
uint64_t nvadsp_get_timestamp_counter(void);
|
||||
|
||||
/*
|
||||
* ADSP OS App
|
||||
*/
|
||||
#define ARGV_SIZE_IN_WORDS 128
|
||||
|
||||
enum {
|
||||
NVADSP_APP_STATE_UNKNOWN,
|
||||
NVADSP_APP_STATE_INITIALIZED,
|
||||
NVADSP_APP_STATE_STARTED,
|
||||
NVADSP_APP_STATE_STOPPED
|
||||
};
|
||||
|
||||
enum adsp_app_status_msg {
|
||||
OS_LOAD_ADSP_APPS,
|
||||
RUN_ADSP_APP,
|
||||
ADSP_APP_INIT,
|
||||
ADSP_APP_START,
|
||||
ADSP_APP_START_STATUS,
|
||||
ADSP_APP_COMPLETE_STATUS
|
||||
};
|
||||
|
||||
struct nvadsp_app_info;
|
||||
typedef const void *nvadsp_app_handle_t;
|
||||
typedef void (*app_complete_status_notifier)(struct nvadsp_app_info *,
|
||||
enum adsp_app_status_msg, int32_t);
|
||||
|
||||
typedef struct adsp_app_mem {
|
||||
/* DRAM segment*/
|
||||
void *dram;
|
||||
/* DRAM in shared memory segment. uncached */
|
||||
void *shared;
|
||||
/* DRAM in shared memory segment. write combined */
|
||||
void *shared_wc;
|
||||
/* ARAM if available, DRAM OK */
|
||||
void *aram;
|
||||
/* set to 1 if ARAM allocation succeeded else 0 meaning allocated from
|
||||
* dram.
|
||||
*/
|
||||
uint32_t aram_flag;
|
||||
/* ARAM Segment. exclusively */
|
||||
void *aram_x;
|
||||
/* set to 1 if ARAM allocation succeeded */
|
||||
uint32_t aram_x_flag;
|
||||
} adsp_app_mem_t;
|
||||
|
||||
typedef struct adsp_app_iova_mem {
|
||||
/* DRAM segment*/
|
||||
uint32_t dram;
|
||||
/* DRAM in shared memory segment. uncached */
|
||||
uint32_t shared;
|
||||
/* DRAM in shared memory segment. write combined */
|
||||
uint32_t shared_wc;
|
||||
/* ARAM if available, DRAM OK */
|
||||
uint32_t aram;
|
||||
/*
|
||||
* set to 1 if ARAM allocation succeeded else 0 meaning allocated from
|
||||
* dram.
|
||||
*/
|
||||
uint32_t aram_flag;
|
||||
/* ARAM Segment. exclusively */
|
||||
uint32_t aram_x;
|
||||
/* set to 1 if ARAM allocation succeeded */
|
||||
uint32_t aram_x_flag;
|
||||
} adsp_app_iova_mem_t;
|
||||
|
||||
|
||||
typedef struct nvadsp_app_args {
|
||||
/* number of arguments passed in */
|
||||
int32_t argc;
|
||||
/* binary representation of arguments */
|
||||
int32_t argv[ARGV_SIZE_IN_WORDS];
|
||||
} nvadsp_app_args_t;
|
||||
|
||||
typedef struct nvadsp_app_info {
|
||||
const char *name;
|
||||
const int instance_id;
|
||||
const uint32_t token;
|
||||
const int state;
|
||||
adsp_app_mem_t mem;
|
||||
adsp_app_iova_mem_t iova_mem;
|
||||
struct list_head node;
|
||||
uint32_t stack_size;
|
||||
const void *handle;
|
||||
int return_status;
|
||||
struct completion wait_for_app_complete;
|
||||
struct completion wait_for_app_start;
|
||||
app_complete_status_notifier complete_status_notifier;
|
||||
struct work_struct complete_work;
|
||||
enum adsp_app_status_msg status_msg;
|
||||
void *priv;
|
||||
} nvadsp_app_info_t;
|
||||
|
||||
nvadsp_app_handle_t __must_check nvadsp_app_load(const char *, const char *);
|
||||
nvadsp_app_info_t __must_check *nvadsp_app_init(nvadsp_app_handle_t,
|
||||
nvadsp_app_args_t *);
|
||||
void nvadsp_app_unload(nvadsp_app_handle_t);
|
||||
int __must_check nvadsp_app_start(nvadsp_app_info_t *);
|
||||
int nvadsp_app_stop(nvadsp_app_info_t *);
|
||||
int nvadsp_app_deinit(nvadsp_app_info_t *);
|
||||
void *nvadsp_alloc_coherent(size_t, dma_addr_t *, gfp_t);
|
||||
void nvadsp_free_coherent(size_t, void *, dma_addr_t);
|
||||
nvadsp_app_info_t __must_check *nvadsp_run_app(nvadsp_os_handle_t, const char *,
|
||||
nvadsp_app_args_t *, app_complete_status_notifier,
|
||||
uint32_t, uint32_t, bool);
|
||||
void nvadsp_exit_app(nvadsp_app_info_t *app, bool terminate);
|
||||
|
||||
static inline void
|
||||
set_app_complete_notifier(
|
||||
nvadsp_app_info_t *info, app_complete_status_notifier notifier)
|
||||
{
|
||||
info->complete_status_notifier = notifier;
|
||||
}
|
||||
|
||||
static inline void wait_for_nvadsp_app_complete(nvadsp_app_info_t *info)
|
||||
{
|
||||
/*
|
||||
* wait_for_complete must be called only after app has started
|
||||
*/
|
||||
if (info->state == NVADSP_APP_STATE_STARTED)
|
||||
wait_for_completion(&info->wait_for_app_complete);
|
||||
}
|
||||
|
||||
/**
|
||||
* wait_for_nvadsp_app_complete_timeout:
|
||||
* @info: pointer to nvadsp_app_info_t
|
||||
* @timeout: timeout value in jiffies
|
||||
*
|
||||
* This waits for either a completion of a specific app to be signaled or for a
|
||||
* specified timeout to expire. It is interruptible. The timeout is in jiffies.
|
||||
*
|
||||
* The return value is -ERESTARTSYS if interrupted, 0 if timed out,
|
||||
* positive (at least 1, or number of jiffies left till timeout) if completed.
|
||||
*/
|
||||
static inline long wait_for_nvadsp_app_complete_timeout(nvadsp_app_info_t *info,
|
||||
unsigned long timeout)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
/*
|
||||
* wait_for_complete must be called only after app has started
|
||||
*/
|
||||
if (info->state == NVADSP_APP_STATE_STARTED)
|
||||
ret = wait_for_completion_interruptible_timeout(
|
||||
&info->wait_for_app_complete, timeout);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* set adma reg dump callback function pointer
|
||||
* @cb_adma_regdump: function pointer for callback
|
||||
*
|
||||
* This api is exported and can be accessed by adsp audio driver,
|
||||
* which during adsp init, calls this api to set the callback
|
||||
* function pointer
|
||||
*/
|
||||
void nvadsp_set_adma_dump_reg(void (*cb_adma_regdump)(void));
|
||||
|
||||
#ifdef CONFIG_TEGRA_ADSP_DFS
|
||||
/*
|
||||
* Override adsp freq and reinit actmon counters
|
||||
*
|
||||
* @params:
|
||||
* freq: adsp freq in KHz
|
||||
* return - final freq got set.
|
||||
* - 0, incase of error.
|
||||
*
|
||||
*/
|
||||
unsigned long adsp_override_freq(unsigned long freq);
|
||||
void adsp_update_dfs_min_rate(unsigned long freq);
|
||||
|
||||
/* Enable / disable dynamic freq scaling */
|
||||
void adsp_update_dfs(bool enable);
|
||||
#else
|
||||
static inline unsigned long adsp_override_freq(unsigned long freq)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void adsp_update_dfs_min_rate(unsigned long freq)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void adsp_update_dfs(bool enable)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
void *nvadsp_aram_request(const char *name, size_t size);
|
||||
bool nvadsp_aram_release(void *handle);
|
||||
|
||||
unsigned long nvadsp_aram_get_address(void *handle);
|
||||
void nvadsp_aram_print(void);
|
||||
|
||||
#endif /* __LINUX_TEGRA_NVADSP_H */
|
||||
Reference in New Issue
Block a user