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arm64: tegra: Add more DT overlays
Add a new DT overlay for Tegra194 Jetson boards that populates the necessary device-tree nodes for devices that use out-of-tree drivers. Add the DT overlays for OPTEE and the Tegra234 SBSA UART that have been copied from the linux-stable branch. By adding them to this repository we can remove from linux-stable branch because this branch should only include changes from upstream. Bug 3733730 Change-Id: I13172d6c6e9930c85f0126477668858dccbbf560 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2770883 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -2,10 +2,13 @@
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# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# DT overlays
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dtbo-y += tegra-optee.dtbo
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dtbo-y += tegra194-carveouts.dtbo
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dtbo-y += tegra194-jetson.dtbo
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dtbo-y += tegra194-p3509-0000+p3668-0001-overlay.dtbo
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dtbo-y += tegra234-p3737-0000+p3701-0000-overlay.dtbo
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dtbo-y += tegra234-jetson.dtbo
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dtbo-y += tegra234-sbsa-uart.dtbo
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# Nvidia internal DT platforms
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43
arch/arm64/boot/dts/nvidia/tegra-optee.dts
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43
arch/arm64/boot/dts/nvidia/tegra-optee.dts
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Jetson Device-tree overlay for OP-TEE.
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*/
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/dts-v1/;
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/plugin/;
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/ {
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overlay-name = "OP-TEE overlay";
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compatible = "nvidia,tegra194", "nvidia,tegra234";
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fragment@0 {
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target-path = "/";
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board_config {
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sw-modules = "kernel";
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};
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__overlay__ {
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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status = "disabled";
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};
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};
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};
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};
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};
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157
arch/arm64/boot/dts/nvidia/tegra194-jetson.dts
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157
arch/arm64/boot/dts/nvidia/tegra194-jetson.dts
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@@ -0,0 +1,157 @@
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/tegra194-mc.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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/ {
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overlay-name = "Tegra194 Jetson Overlay";
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compatible = "nvidia,tegra194";
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fragment@0 {
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target-path = "/bus@0/host1x@13e00000";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges = <0x14800000 0x14800000 0x02800000>,
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<0x24f00000 0x24f00000 0x00100000>;
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nvdla0@15880000 {
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compatible = "nvidia,tegra194-nvdla";
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reg = <0x15880000 0x00040000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DLA0_CORE>,
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<&bpmp TEGRA194_CLK_DLA0_FALCON>;
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clock-names = "nvdla", "nvdla_flcn";
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resets = <&bpmp TEGRA194_RESET_DLA0>;
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reset-names = "nvdla";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAA>;
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA0RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0FALRDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu TEGRA194_SID_NVDLA0>;
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dma-coherent;
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};
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nvdla1@158c0000 {
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compatible = "nvidia,tegra194-nvdla";
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reg = <0x158c0000 0x00040000>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DLA1_CORE>,
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<&bpmp TEGRA194_CLK_DLA1_FALCON>;
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clock-names = "nvdla", "nvdla_flcn";
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resets = <&bpmp TEGRA194_RESET_DLA1>;
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reset-names = "nvdla";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAB>;
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA1RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1FALRDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu TEGRA194_SID_NVDLA1>;
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dma-coherent;
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};
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pva0@16000000 {
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compatible = "nvidia,tegra194-pva";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAA>;
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reg = <0x16000000 0x00800000>,
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<0x24f00000 0x00080000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA194_RESET_PVA0_ALL>;
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reset-names = "nvpva";
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clocks = <&bpmp TEGRA194_CLK_NAFLL_PVA_VPS>,
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<&bpmp TEGRA194_CLK_NAFLL_PVA_CORE>,
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<&bpmp TEGRA194_CLK_PVA0_AXI>,
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<&bpmp TEGRA194_CLK_PVA0_VPS0>,
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<&bpmp TEGRA194_CLK_PVA0_VPS1>;
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clock-names = "nafll_pva_vps", "nafll_pva_core", "axi", "vps0", "vps1";
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA0RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0RDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0RDC &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRC &emc>;
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interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";
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iommus = <&smmu TEGRA194_SID_PVA0>;
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dma-coherent;
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};
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pva1@16800000 {
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compatible = "nvidia,tegra194-pva";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAB>;
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reg = <0x16800000 0x00800000>,
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<0x24f80000 0x00080000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA194_RESET_PVA1_ALL>;
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reset-names = "nvpva";
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clocks = <&bpmp TEGRA194_CLK_PVA1_AXI>,
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<&bpmp TEGRA194_CLK_PVA1_VPS0>,
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<&bpmp TEGRA194_CLK_PVA1_VPS1>;
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clock-names = "axi", "vps0", "vps1";
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA1RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1RDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1RDC &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRC &emc>;
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interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";
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iommus = <&smmu TEGRA194_SID_PVA1>;
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dma-coherent;
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};
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};
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};
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fragment@1 {
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target-path = "/";
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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cvnas@14000000 {
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compatible = "nvidia,tegra194-cvnas";
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reg = <0x0 0x14000000 0x0 0x20000>, /* CV0_REG0_BASE */
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<0x0 0x14020000 0x0 0x10000>, /* CV0_SRAM_BASE */
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<0x0 0x0b240000 0x0 0x10000>; /* HSM_BASE */
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_CVNAS>;
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assigned-clocks = <&bpmp TEGRA194_CLK_CVNAS>;
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assigned-clock-rates = <1356800000>;
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resets = <&bpmp TEGRA194_RESET_CVNAS>,
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<&bpmp TEGRA194_RESET_CVNAS_FCM>;
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reset-names = "rst", "rst_fcm";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_CV>;
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cvsramslice = <4 0x1000>;
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cvsram-reg = <0x0 0x50000000 0x0 0x400000>;
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};
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};
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};
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};
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42
arch/arm64/boot/dts/nvidia/tegra234-sbsa-uart.dts
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42
arch/arm64/boot/dts/nvidia/tegra234-sbsa-uart.dts
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@@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Tegra234 Device-tree overlay for SBSA UART
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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overlay-name = "Tegra234 SBSA UART overlay";
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compatible = "nvidia,tegra234";
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fragment@0 {
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target-path = "/bus@0/";
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__overlay__ {
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serial@31d0000 {
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compatible = "arm,sbsa-uart";
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reg = <0x31d0000 0x10000>;
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interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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status = "okay";
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};
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};
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};
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};
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