ASoC: tegra-alt: Fix MVC mute issue

MVC Mute Mixer ctrl setting is not reflecting correct
status as the mute ctrl register is not cached and therefore
getting reset to default in resume call that is being called
after reading the mixer ctrl.

To avoid this, MVC mute register is made non-volatile and
get_sync/put_sync is avoided for reading this cached register

Mute status reset in cache everytime after setting volume
for proper reflection of mute status in mixer controls. Note
that cached value will be synced to hardware on resume.

Bug 200532059

Change-Id: I9ee072d84c8103facdad22b2708113c4bcdda039
Signed-off-by: Asha Talambedu <atalambedu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165774
(cherry picked from commit 85badb30954b503121f139a66eba4dc02eb90068)
Reviewed-on: https://git-master.nvidia.com/r/2185120
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Asha Talambedu
2019-08-06 11:26:22 +05:30
committed by Sameer Pujar
parent aa1f1ad292
commit d5be4c92a4

View File

@@ -146,9 +146,7 @@ static int tegra210_mvc_get_vol(struct snd_kcontrol *kcontrol,
} else {
u32 val;
pm_runtime_get_sync(codec->dev);
regmap_read(mvc->regmap, reg, &val);
pm_runtime_put(codec->dev);
ucontrol->value.integer.value[0] =
((val & TEGRA210_MVC_MUTE_MASK) != 0);
}
@@ -207,6 +205,10 @@ static int tegra210_mvc_put_vol(struct snd_kcontrol *kcontrol,
end:
pm_runtime_put(codec->dev);
if (reg == TEGRA210_MVC_TARGET_VOL)
ret |= regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_MUTE_MASK, 0);
return ret;
}
@@ -573,7 +575,6 @@ static bool tegra210_mvc_volatile_reg(struct device *dev, unsigned int reg)
case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL:
case TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_DATA:
case TEGRA210_MVC_PEAK_VALUE:
case TEGRA210_MVC_CTRL:
return true;
default:
return false;