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t23x: ari: build mce ari driver as a module
Bug 3680143 Change-Id: I1092b85239222b6af9a9ecfc536801f298706e60 Signed-off-by: Sanjay Chandrashekara <sanjayc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2774586 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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Sanjay Chandrashekara
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91
include/linux/platform/tegra/t23x_ari.h
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91
include/linux/platform/tegra/t23x_ari.h
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@@ -0,0 +1,91 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef T23X_ARI_H
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#define T23X_ARI_H
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/* ARI Version numbers */
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#define TEGRA_ARI_VERSION_MAJOR 8UL
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#define TEGRA_ARI_VERSION_MINOR 1UL
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/*
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* ARI Request IDs
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*
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* TODO: RENUMBER range before finalization
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* NOTE: for documentation purposes, only documenting gaps
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* in ranges, to indicate that we know about the missing ids
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*
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* Require NO LAB Locks
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* range from 0 - 31
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*/
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#define TEGRA_ARI_VERSION 0UL
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#define TEGRA_ARI_ECHO 1UL
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#define TEGRA_ARI_NUM_CORES 2UL
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#define TEGRA_ARI_CSTATE_STAT_QUERY 3UL
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/* Undefined 4 - 28 */
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/* Debug Only ARIs at the end of the NO LAB Lock Range */
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#define TEGRA_ARI_CORE_DEBUG_RECOVERY 29UL
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#define TEGRA_ARI_DSU_DEBUG_RECOVERY 30UL
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#define TEGRA_ARI_CLUSTER_WARM_RESET 31UL
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/*
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* Require CORE LAB Lock -- obtained by MTM from ARI
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* range from 32 - 63
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*/
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/* UNDEFINED 32 */
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/* UNDEFINED 33 */
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#define TEGRA_ARI_ONLINE_CORE 34UL
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#define TEGRA_ARI_ENTER_CSTATE 35UL
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/* UNDEFINED 36 */
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#define TEGRA_ARI_TRIGGER_ONLINE_IST 37UL
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/*
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* Require CLUSTER and CORE LAB Lock -- obtained by MTM from ARI
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* range from 64 - 95
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*/
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/* UNDEFINED 64 */
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#define TEGRA_ARI_NVFREQ_REQ 65UL
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#define TEGRA_ARI_NVFREQ_FEEDBACK 66UL
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#define TEGRA_ARI_CLUSTER_ATCLKEN 67UL
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/*
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* Require CCPLEX, CLUSTER and CORE LAB Lock -- obtained by MTM from ARI
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* range from 96 - 127
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*/
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#define TEGRA_ARI_CCPLEX_CACHE_CONTROL 96UL
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#define TEGRA_ARI_CCPLEX_CACHE_CLEAN 97UL
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/* UNDEFINED 98 */
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#define TEGRA_ARI_CCPLEX_LATIC_ON 99UL
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#define TEGRA_ARI_UPDATE_CROSSOVER 100UL
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/* UNDEFINED 101 */
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#define TEGRA_ARI_CCPLEX_SHUTDOWN 102UL
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/* UNDEFINED 103 */
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#define TEGRA_ARI_CSTATE_INFO 104UL
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#define TEGRA_ARI_IS_SC7_ALLOWED 105UL
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/* UNDEFINED 106 */
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/* UNDEFINED 107 */
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#define TEGRA_ARI_SECURITY_CONFIG 108UL
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#define TEGRA_ARI_UPDATE_CCPLEX_CARVEOUTS 109UL
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#define TEGRA_ARI_DDA_CONTROL 110UL
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#define TEGRA_ARI_PERFMON 111UL
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#define TEGRA_ARI_DEBUG_CONFIG 112UL
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#define TEGRA_ARI_CCPLEX_ERROR_RECOVERY_RESET 114UL
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/* Values for ARI CSTATE STAT QUERY */
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#define TEGRA_ARI_STAT_QUERY_SC7_ENTRIES 1UL
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#define TEGRA_ARI_STAT_QUERY_CC7_ENTRIES 6UL
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#define TEGRA_ARI_STAT_QUERY_C7_ENTRIES 14UL
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#define TEGRA_ARI_STAT_QUERY_SC7_ENTRY_TIME_SUM 60UL
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#define TEGRA_ARI_STAT_QUERY_CC7_ENTRY_TIME_SUM 61UL
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#define TEGRA_ARI_STAT_QUERY_C7_ENTRY_TIME_SUM 64UL
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#define TEGRA_ARI_STAT_QUERY_SC7_EXIT_TIME_SUM 70UL
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#define TEGRA_ARI_STAT_QUERY_CC7_EXIT_TIME_SUM 71UL
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#define TEGRA_ARI_STAT_QUERY_C7_EXIT_TIME_SUM 74UL
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/* Values for ARI UPDATE CROSSOVER */
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#define TEGRA_ARI_CROSSOVER_C7_LOWER_BOUND 0UL
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#define TEGRA_ARI_CROSSOVER_CC7_LOWER_BOUND 1UL
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/* Values for ARI UPDATE CCPLEX CARVEOUTS */
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#define TEGRA_ARI_UPDATE_CCPLEX_CARVEOUTS_ALL 0UL
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#endif /* T23X_ARI_H */
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148
include/linux/platform/tegra/tegra-mce.h
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148
include/linux/platform/tegra/tegra-mce.h
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef _LINUX_TEGRA_MCE_H
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#define _LINUX_TEGRA_MCE_H
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/* NOTE:
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* For correct version validation, below two defines need to be
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* updated whenever there is a new ARI implementation.
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*/
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#define CUR_ARI_VER_MAJOR 1
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#define CUR_ARI_VER_MINOR 2
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enum {
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TEGRA_MCE_XOVER_C1_C6, /* Only valid for Denver */
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TEGRA_MCE_XOVER_CC1_CC6,
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TEGRA_MCE_XOVER_CC1_CC7,
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TEGRA_MCE_XOVER_MAX = TEGRA_MCE_XOVER_CC1_CC7
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};
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enum {
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TEGRA_MCE_CSTATS_CLEAR,
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TEGRA_MCE_CSTATS_ENTRIES_SC7,
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TEGRA_MCE_CSTATS_ENTRIES_SC4,
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TEGRA_MCE_CSTATS_ENTRIES_SC3,
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TEGRA_MCE_CSTATS_ENTRIES_SC2,
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TEGRA_MCE_CSTATS_ENTRIES_CCP3,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CC6,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CC7,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CC6,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CC7,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE0_C6,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE1_C6,
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/* RESV: 12-13 */
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE0_C7 = 14,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE1_C7,
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/* RESV: 16-17 */
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE0_C7 = 18,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE1_C7,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE2_C7,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE3_C7,
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TEGRA_MCE_CSTATS_LAST_ENTRY_D15_CORE0,
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TEGRA_MCE_CSTATS_LAST_ENTRY_D15_CORE1,
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/* RESV: 24-25 */
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE0,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE1,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE2,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE3,
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TEGRA_MCE_CSTATS_MAX = TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE3,
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};
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enum {
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TEGRA_MCE_ENUM_D15_CORE0,
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TEGRA_MCE_D15_CORE1,
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/* RESV: 2-3 */
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TEGRA_MCE_ENUM_A57_0 = 4,
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TEGRA_MCE_ENUM_A57_1,
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TEGRA_MCE_ENUM_A57_2,
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TEGRA_MCE_ENUM_A57_3,
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TEGRA_MCE_ENUM_MAX = TEGRA_MCE_ENUM_A57_3,
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};
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enum {
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TEGRA_MCE_FEATURE_CCP3,
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};
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/* MCA support */
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typedef union {
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struct {
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u8 cmd;
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u8 subidx;
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u8 idx;
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u8 inst;
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};
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struct {
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u32 low;
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u32 high;
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};
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u64 data;
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} mca_cmd_t;
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/* NOTE: These functions will return -ENOTSUPP if no implementation */
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int tegra_mce_enter_cstate(u32 state, u32 wake_time);
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int tegra_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid);
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int tegra_mce_update_crossover_time(u32 type, u32 time);
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int tegra_mce_read_cstate_stats(u32 state, u64 *stats);
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int tegra_mce_write_cstate_stats(u32 state, u32 stats);
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int tegra_mce_is_sc7_allowed(u32 state, u32 wake, u32 *allowed);
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int tegra_mce_online_core(int cpu);
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int tegra_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable);
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int tegra_mce_echo_data(u64 data, u64 *matched);
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int tegra_mce_read_versions(u32 *major, u32 *minor);
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int tegra_mce_enum_features(u64 *features);
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int tegra_mce_read_uncore_mca(mca_cmd_t cmd, u64 *data, u32 *error);
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int tegra_mce_write_uncore_mca(mca_cmd_t cmd, u64 data, u32 *error);
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int tegra_mce_read_uncore_perfmon(u32 req, u32 *data);
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int tegra_mce_write_uncore_perfmon(u32 req, u32 data);
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int tegra_mce_enable_latic(void);
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int tegra_mce_write_dda_ctrl(u32 index, u64 value);
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int tegra_mce_read_dda_ctrl(u32 index, u64 *value);
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/* L3 cache ways read/write functions */
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int tegra_mce_read_l3_cache_ways(u64 *value);
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int tegra_mce_write_l3_cache_ways(u64 data, u64 *value);
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int tegra_mce_read_rt_safe_mask(u64 *);
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int tegra_mce_write_rt_safe_mask(u64);
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int tegra_mce_read_rt_window_us(u64 *);
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int tegra_mce_write_rt_window_us(u64);
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int tegra_mce_read_rt_fwd_progress_us(u64 *);
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int tegra_mce_write_rt_fwd_progress_us(u64);
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struct tegra_mce_ops {
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int (*enter_cstate)(u32, u32);
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int (*update_cstate_info)(u32, u32, u32, u8, u32, bool);
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int (*update_crossover_time)(u32, u32);
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int (*read_cstate_stats)(u32, u64 *);
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int (*write_cstate_stats)(u32, u32);
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int (*is_sc7_allowed)(u32, u32, u32 *);
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int (*online_core)(int);
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int (*cc3_ctrl)(u32, u32, u8);
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int (*echo_data)(u64, u64*);
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int (*read_versions)(u32 *, u32 *);
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int (*enum_features)(u64 *);
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int (*read_uncore_mca)(mca_cmd_t, u64 *, u32 *);
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int (*write_uncore_mca)(mca_cmd_t, u64, u32 *);
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int (*read_uncore_perfmon)(u32, u32 *);
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int (*write_uncore_perfmon)(u32, u32);
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int (*enable_latic)(void);
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int (*write_dda_ctrl)(u32 index, u64 value);
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int (*read_dda_ctrl)(u32 index, u64 *value);
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int (*read_l3_cache_ways)(u64 *value);
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int (*write_l3_cache_ways)(u64 data, u64 *value);
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int (*read_rt_safe_mask)(u64 *);
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int (*write_rt_safe_mask)(u64);
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int (*read_rt_window_us)(u64 *);
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int (*write_rt_window_us)(u64);
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int (*read_rt_fwd_progress_us)(u64 *);
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int (*write_rt_fwd_progress_us)(u64);
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};
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void tegra_mce_set_ops(struct tegra_mce_ops *);
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#endif /* _LINUX_TEGRA_MCE_H */
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