drivers:nvpps: clear TSC CAPTURE interrupt enable bit

Clear INTR_EN bit from TSC_CAPTURE_CONFIGURATION_PTX
register as part of PTP TSC sync initialization sequence
as nvpps does not use capture interrupts for PTP-TSC
functioning.

Bug 4640129

Signed-off-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Change-Id: I9f374d8cde49cabcbc57e9edaf92031c07b6ada1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3177373
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vijay Mishra <vijaym@nvidia.com>
This commit is contained in:
Sheetal Tigadoli
2024-07-18 10:43:37 +00:00
committed by mobile promotions
parent a21f30c983
commit d71b21ebb9

View File

@@ -918,7 +918,7 @@ static void nvpps_ptp_tsc_sync_config(struct platform_device *pdev)
writel((0x50011 | (pdev_data->k_int_val << TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET_K_INT_SHIFT)), writel((0x50011 | (pdev_data->k_int_val << TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET_K_INT_SHIFT)),
pdev_data->tsc_reg_map_base + TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET); pdev_data->tsc_reg_map_base + TSC_LOCKING_FAST_ADJUST_CONFIGURATION_OFFSET);
writel(0x67, pdev_data->tsc_reg_map_base + TSC_LOCKING_ADJUST_DELTA_CONTROL_OFFSET); writel(0x67, pdev_data->tsc_reg_map_base + TSC_LOCKING_ADJUST_DELTA_CONTROL_OFFSET);
writel(0x313, pdev_data->tsc_reg_map_base + TSC_CAPTURE_CONFIGURATION_PTX_OFFSET); writel(0x311, pdev_data->tsc_reg_map_base + TSC_CAPTURE_CONFIGURATION_PTX_OFFSET);
writel(0x1, pdev_data->tsc_reg_map_base + TSC_STSCRSR_OFFSET); writel(0x1, pdev_data->tsc_reg_map_base + TSC_STSCRSR_OFFSET);
tsc_config_ptx_0 = readl(pdev_data->tsc_reg_map_base + TSC_CAPTURE_CONFIGURATION_PTX_OFFSET); tsc_config_ptx_0 = readl(pdev_data->tsc_reg_map_base + TSC_CAPTURE_CONFIGURATION_PTX_OFFSET);