From d75315355cad18c08d2cc0dd8df806d52bce80d3 Mon Sep 17 00:00:00 2001 From: Viswanath L Date: Tue, 2 Apr 2024 15:51:08 +0000 Subject: [PATCH] nvadsp: t264: Reorg and update chip data - Move chip data from patch files to dev-*.c files for ease of maintenance - Add patch file to patch compatible and chip data into dev.c file, also add dev-*.c files to build makefile - Add stub for dump_core_state function pointer - ADSP updates - Use AMISC base directly from reg DT prop as it will be offset as per the DSP instance (drop adsp_prid) - Set amc_not_avlbl to true for ADSP[1], so only ADSP[0] will access AMC - Change compatible of ADSP[0] to "nvidia,tegra264-adsp" in order to keep continuity with previous chip generations (unique identifier string is "adsp") Also remove T264 adsp support from kprev. Bug 3682950 Bug 4165898 Change-Id: I22abf3fda01f4e0e259759ba1816a9580a474d40 Signed-off-by: Viswanath L Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3107870 GVS: Gerrit_Virtual_Submit Reviewed-by: Dara Ramesh Reviewed-by: Asha T --- drivers/platform/tegra/nvadsp/dev-t264-aon.c | 43 +++++++++-- drivers/platform/tegra/nvadsp/dev-t264.c | 77 +++++++++++++++++--- 2 files changed, 105 insertions(+), 15 deletions(-) diff --git a/drivers/platform/tegra/nvadsp/dev-t264-aon.c b/drivers/platform/tegra/nvadsp/dev-t264-aon.c index 6bae9574..5ba8fc05 100644 --- a/drivers/platform/tegra/nvadsp/dev-t264-aon.c +++ b/drivers/platform/tegra/nvadsp/dev-t264-aon.c @@ -2,7 +2,6 @@ // SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. #include "dev.h" -#include "dev-t264-aon.h" /* Defining offsets */ #define AO_MISC_CPU_RESET_VECTOR_0 0x0 @@ -13,7 +12,7 @@ #define AO_MISC_CPU_SET_RUNSTALL_0 0x1 #define AO_MISC_CPU_CLEAR_RUNSTALL_0 0x0 -int nvaon_os_t264_init(struct platform_device *pdev) +static int nvaon_os_t264_init(struct platform_device *pdev) { /* TBD */ return 0; @@ -65,7 +64,7 @@ static int __nvaon_t264_runtime_idle(struct device *dev) return 0; } -int nvaon_pm_t264_init(struct platform_device *pdev) +static int nvaon_pm_t264_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; @@ -80,6 +79,11 @@ int nvaon_pm_t264_init(struct platform_device *pdev) } #endif /* CONFIG_PM */ +static void __dump_core_state_t264_aon(struct nvadsp_drv_data *d) +{ + /* TBD */ +} + static int __set_boot_vec_t264(struct nvadsp_drv_data *d) { /* TBD */ @@ -129,7 +133,7 @@ static int __map_hwmbox_interrupts(struct nvadsp_drv_data *d) return 0; } -static bool __check_wfi_status(struct nvadsp_drv_data *d) +static bool __check_wfi_status_t264_aon(struct nvadsp_drv_data *d) { void __iomem *cpu_config_base; bool wfi_status = false; @@ -148,7 +152,7 @@ static bool __check_wfi_status(struct nvadsp_drv_data *d) return wfi_status; } -int nvaon_reset_t264_init(struct platform_device *pdev) +static int nvaon_dev_t264_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); int ret = 0; @@ -161,6 +165,33 @@ int nvaon_reset_t264_init(struct platform_device *pdev) d->set_boot_freqs = __set_boot_freqs_t264; d->map_hwmbox_interrupts = __map_hwmbox_interrupts; - d->check_wfi_status = __check_wfi_status; + d->check_wfi_status = __check_wfi_status_t264_aon; + d->dump_core_state = __dump_core_state_t264_aon; + return ret; } + +struct nvadsp_chipdata tegra264_aon_chipdata = { + .hwmb = { + .reg_idx = AON_HSP, + .hwmbox0_reg = 0x00000, + .hwmbox1_reg = 0X08000, + .hwmbox2_reg = 0X10000, + .hwmbox3_reg = 0X18000, + .hwmbox4_reg = 0X20000, + .hwmbox5_reg = 0X28000, + .hwmbox6_reg = 0X30000, + .hwmbox7_reg = 0X38000, + .empty_int_ie = 0x8, + }, + .adsp_shared_mem_hwmbox = 0x08048, /* HWMBOX1 TYPE1_DATA0 */ + .adsp_boot_config_hwmbox = 0x0804C, /* HWMBOX1 TYPE1_DATA1 */ + .dev_init = nvaon_dev_t264_init, + .os_init = nvaon_os_t264_init, +#ifdef CONFIG_PM + .pm_init = nvaon_pm_t264_init, +#endif + .adsp_elf = "aon_t264.elf", + .num_irqs = NVAON_VIRQ_MAX, + .amc_not_avlbl = true, +}; diff --git a/drivers/platform/tegra/nvadsp/dev-t264.c b/drivers/platform/tegra/nvadsp/dev-t264.c index 98692e57..6a3da70c 100644 --- a/drivers/platform/tegra/nvadsp/dev-t264.c +++ b/drivers/platform/tegra/nvadsp/dev-t264.c @@ -5,15 +5,13 @@ #include #include "dev.h" -#include "dev-t264.h" -#define AMISC_ADSP_CPU_CONFIG_STRIDE (0x1000) #define AMISC_ADSP_CPU_CONFIG (0x0) #define AMISC_ADSP_STATVECTORSEL (1 << 4) #define AMISC_ADSP_RUNSTALL (1 << 0) #define AMISC_ADSP_CPU_RESETVEC 0x4 -int nvadsp_os_t264_init(struct platform_device *pdev) +static int nvadsp_os_t264_init(struct platform_device *pdev) { /* TBD */ return 0; @@ -63,7 +61,7 @@ static int __nvadsp_t264_runtime_idle(struct device *dev) return 0; } -int nvadsp_pm_t264_init(struct platform_device *pdev) +static int nvadsp_pm_t264_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; @@ -78,6 +76,11 @@ int nvadsp_pm_t264_init(struct platform_device *pdev) } #endif /* CONFIG_PM */ +static void __dump_core_state_t264(struct nvadsp_drv_data *d) +{ + /* TBD */ +} + static int __set_boot_vec_t264(struct nvadsp_drv_data *d) { /* TBD */ @@ -99,8 +102,7 @@ static int __assert_t264_adsp(struct nvadsp_drv_data *d) int ret = 0; /* Assert RUNSTALL */ - cpu_config_base = d->base_regs[AMISC] + - (d->chip_data->adsp_prid * AMISC_ADSP_CPU_CONFIG_STRIDE); + cpu_config_base = d->base_regs[AMISC]; cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG); cpu_config |= AMISC_ADSP_RUNSTALL; writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG); @@ -129,8 +131,7 @@ static int __deassert_t264_adsp(struct nvadsp_drv_data *d) } /* Deassert RUNSTALL */ - cpu_config_base = d->base_regs[AMISC] + - (d->chip_data->adsp_prid * AMISC_ADSP_CPU_CONFIG_STRIDE); + cpu_config_base = d->base_regs[AMISC]; cpu_config = readl(cpu_config_base + AMISC_ADSP_CPU_CONFIG); cpu_config &= (~AMISC_ADSP_RUNSTALL); writel(cpu_config, cpu_config_base + AMISC_ADSP_CPU_CONFIG); @@ -139,7 +140,13 @@ end: return ret; } -int nvadsp_reset_t264_init(struct platform_device *pdev) +static bool __check_wfi_status_t264(struct nvadsp_drv_data *d) +{ + /* TBD */ + return true; +} + +static int nvadsp_dev_t264_init(struct platform_device *pdev) { struct nvadsp_drv_data *d = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; @@ -151,6 +158,9 @@ int nvadsp_reset_t264_init(struct platform_device *pdev) d->set_boot_vec = __set_boot_vec_t264; d->set_boot_freqs = __set_boot_freqs_t264; + d->check_wfi_status = __check_wfi_status_t264; + d->dump_core_state = __dump_core_state_t264; + d->adspall_rst = devm_reset_control_get(dev, "adsp"); if (IS_ERR(d->adspall_rst)) { dev_err(dev, "cannot get adsp reset\n"); @@ -159,3 +169,52 @@ int nvadsp_reset_t264_init(struct platform_device *pdev) return ret; } + +struct nvadsp_chipdata tegra264_adsp0_chipdata = { + .hwmb = { + .reg_idx = AHSP, + .hwmbox0_reg = 0x00000, + .hwmbox1_reg = 0X08000, + .hwmbox2_reg = 0X10000, + .hwmbox3_reg = 0X18000, + .hwmbox4_reg = 0X20000, + .hwmbox5_reg = 0X28000, + .hwmbox6_reg = 0X30000, + .hwmbox7_reg = 0X38000, + .empty_int_ie = 0x8, + }, + .adsp_shared_mem_hwmbox = 0x08048, /* HWMBOX1 TYPE1_DATA0 */ + .adsp_boot_config_hwmbox = 0x0804C, /* HWMBOX1 TYPE1_DATA1 */ + .dev_init = nvadsp_dev_t264_init, + .os_init = nvadsp_os_t264_init, +#ifdef CONFIG_PM + .pm_init = nvadsp_pm_t264_init, +#endif + .adsp_elf = "adsp0_t264.elf", + .num_irqs = NVADSP_VIRQ_MAX, +}; + +struct nvadsp_chipdata tegra264_adsp1_chipdata = { + .hwmb = { + .reg_idx = AHSP, + .hwmbox0_reg = 0x00000, + .hwmbox1_reg = 0X08000, + .hwmbox2_reg = 0X10000, + .hwmbox3_reg = 0X18000, + .hwmbox4_reg = 0X20000, + .hwmbox5_reg = 0X28000, + .hwmbox6_reg = 0X30000, + .hwmbox7_reg = 0X38000, + .empty_int_ie = 0x8, + }, + .adsp_shared_mem_hwmbox = 0x08048, /* HWMBOX1 TYPE1_DATA0 */ + .adsp_boot_config_hwmbox = 0x0804C, /* HWMBOX1 TYPE1_DATA1 */ + .dev_init = nvadsp_dev_t264_init, + .os_init = nvadsp_os_t264_init, +#ifdef CONFIG_PM + .pm_init = nvadsp_pm_t264_init, +#endif + .adsp_elf = "adsp1_t264.elf", + .num_irqs = NVADSP_VIRQ_MAX, + .amc_not_avlbl = true, +};