From d85e055a1e5b44eac991fc12d789969492d8fccb Mon Sep 17 00:00:00 2001 From: abhamidipati Date: Tue, 27 Jun 2023 20:43:41 +0000 Subject: [PATCH] drivers: pva: Add support for T264 - Programming sequence and Driver private data modification for T264 - Add chip specific defines for number of context devices and context device name length - Update the VMEM start and end region addresses for T264 JIRA PVAAS-13227 Change-Id: Ib4512e5690d006f8a5139e37c680e74d7d566492 Signed-off-by: abhamidipati Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2927484 Reviewed-by: Sreehari Mohan Reviewed-by: Krish Agarwal Reviewed-by: Omar Nemri GVS: Gerrit_Virtual_Submit --- .../video/tegra/host/pva/hw_vmem_pva_t264.h | 30 ++++++++ .../tegra/host/pva/pva_cntxt_dev_name_t264.h | 19 +++++ .../host/pva/pva_iommu_context_dev_t264.h | 29 ++++++++ drivers/video/tegra/host/pva/pva_t264.h | 71 +++++++++++++++++++ .../host/pva/pva_vmem_regions_tab_t264.h | 24 +++++++ 5 files changed, 173 insertions(+) create mode 100644 drivers/video/tegra/host/pva/hw_vmem_pva_t264.h create mode 100644 drivers/video/tegra/host/pva/pva_cntxt_dev_name_t264.h create mode 100644 drivers/video/tegra/host/pva/pva_iommu_context_dev_t264.h create mode 100644 drivers/video/tegra/host/pva/pva_t264.h create mode 100644 drivers/video/tegra/host/pva/pva_vmem_regions_tab_t264.h diff --git a/drivers/video/tegra/host/pva/hw_vmem_pva_t264.h b/drivers/video/tegra/host/pva/hw_vmem_pva_t264.h new file mode 100644 index 00000000..5ce8e51b --- /dev/null +++ b/drivers/video/tegra/host/pva/hw_vmem_pva_t264.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __hw_vmem_pva_t264_h__ +#define __hw_vmem_pva_t264_h__ + +#define VMEM_REGION_COUNT_T26x 4U + +#define T26x_VMEM0_START 0x40U +#define T26x_VMEM0_END 0x20000U +#define T26x_VMEM1_START 0x40000U +#define T26x_VMEM1_END 0x60000U +#define T26x_VMEM2_START 0x80000U +#define T26x_VMEM2_END 0xA0000U +#define T26x_VMEM3_START 0xC0000U +#define T26x_VMEM3_END 0xE0000U + +#endif diff --git a/drivers/video/tegra/host/pva/pva_cntxt_dev_name_t264.h b/drivers/video/tegra/host/pva/pva_cntxt_dev_name_t264.h new file mode 100644 index 00000000..ea2bae4c --- /dev/null +++ b/drivers/video/tegra/host/pva/pva_cntxt_dev_name_t264.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __PVA_CNTXT_DEV_NAME_T264_H__ +#define __PVA_CNTXT_DEV_NAME_T264_H__ +#define PVA_CNTXT_DEV_NAME_T264 "\"pva0_niso1_ctx8\"," +#endif diff --git a/drivers/video/tegra/host/pva/pva_iommu_context_dev_t264.h b/drivers/video/tegra/host/pva/pva_iommu_context_dev_t264.h new file mode 100644 index 00000000..66fd7cae --- /dev/null +++ b/drivers/video/tegra/host/pva/pva_iommu_context_dev_t264.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __IOMMU_CONTEXT_DEV_T264_H__ +#define __IOMMU_CONTEXT_DEV_T264_H__ + +/** + * @brief Context device name length for T26x. + */ +#define NVPVA_CNTXT_DEV_NAME_LEN (31U) + +/** + * @brief Number of context devices for T26x. + */ +#define NVPVA_CNTXT_DEVICE_CNT_T264 (9U) + +#endif diff --git a/drivers/video/tegra/host/pva/pva_t264.h b/drivers/video/tegra/host/pva/pva_t264.h new file mode 100644 index 00000000..a2e516e7 --- /dev/null +++ b/drivers/video/tegra/host/pva/pva_t264.h @@ -0,0 +1,71 @@ +/* + * Tegra Graphics Chip support for T264 + * + * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __PVA_T264_H__ +#define __PVA_T264_H__ + +static char *aux_dev_name_t264 = "818c000000.pva0:pva0_niso1_ctx7"; +static u32 aux_dev_name_len_t264 = 31; + +struct nvhost_device_data t264_pva0_info = { + .version = PVA_HW_GEN3, + .num_channels = 1, + .clocks = { + {"axi", UINT_MAX,}, + {"vps0", UINT_MAX,}, + {"vps1", UINT_MAX,}, + }, + .ctrl_ops = &tegra_pva_ctrl_ops, + .devfs_name_family = "pva", + .class = NV_PVA0_CLASS_ID, + .autosuspend_delay = 500, + .finalize_poweron = pva_finalize_poweron, + .prepare_poweroff = pva_prepare_poweroff, + .firmware_name = "nvhost_pva030.fw", + .resource_policy = RESOURCE_PER_CHANNEL_INSTANCE, + .vm_regs = { + {0x240000, false, 0}, + {0x240004, false, 0}, + {0x240008, false, 0}, + {0x24000c, false, 0}, + {0x240010, false, 0}, + {0x240014, false, 0}, + {0x240018, false, 0}, + {0x24001c, false, 0}, + {0x240020, false, 0}, + {0x240020, false, 8}, + {0x240020, false, 16}, + {0x240024, false, 0}, + {0x240024, false, 8} + }, + .poweron_reset = true, + .serialize = true, + .get_reloc_phys_addr = nvhost_t23x_get_reloc_phys_addr, + .can_powergate = true, +}; + +#ifdef CONFIG_PVA_CO_DISABLED +static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7, + 8, 8, 8, 8, 8, 0, 0, 0}; +#else +static u32 vm_regs_sid_idx_t264[] = {1, 2, 3, 4, 5, 6, 7, 7, + 8, 0, 9, 8, 8, 0, 0, 0}; +#endif +static u32 vm_regs_reg_idx_t264[] = {0, 1, 2, 3, 4, 5, 6, 7, + 8, 8, 8, 9, 9, 0, 0, 0}; + +#endif diff --git a/drivers/video/tegra/host/pva/pva_vmem_regions_tab_t264.h b/drivers/video/tegra/host/pva/pva_vmem_regions_tab_t264.h new file mode 100644 index 00000000..779531fb --- /dev/null +++ b/drivers/video/tegra/host/pva/pva_vmem_regions_tab_t264.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * VMEM Regions Initialization for T264 + */ +#ifndef __PVA_VMEM_REGIONS_TAB_T264_H__ +#define __PVA_VMEM_REGIONS_TAB_T264_H__ + {{.start = T26x_VMEM0_START, .end = T26x_VMEM0_END}, + {.start = T26x_VMEM1_START, .end = T26x_VMEM1_END}, + {.start = T26x_VMEM2_START, .end = T26x_VMEM2_END}, + {.start = T26x_VMEM3_START, .end = T26x_VMEM3_END}}, +#endif