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ASoC: tegra-alt: Add get/put handlers for T210 xbar
Bug 1442940 Change-Id: I633c144a4f22b1c9d41f656a47331358b46d43d7 Signed-off-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Reviewed-on: http://git-master/r/412204 Reviewed-by: Songhee Baek <sbaek@nvidia.com> Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
This commit is contained in:
Arun Shamanna Lakshmi
committed by
Sameer Pujar
Sameer Pujar
parent
1ce137c34c
commit
d9c7333753
@@ -297,22 +297,131 @@ static const int tegra210_xbar_mux_values[] = {
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/* index 35..53 above are inputs of PART2 Mux */
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};
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#define MUX0_REG(id) (TEGRA210_XBAR_PART0_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (id)))
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int tegra210_xbar_get_value_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
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struct snd_soc_dapm_widget *widget = wlist->widgets[0];
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struct snd_soc_codec *codec = widget->codec;
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struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
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unsigned int reg_count, reg_val, val, bit_pos = 0, i;
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unsigned int reg[TEGRA210_XBAR_UPDATE_MAX_REG];
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#define MUX1_REG(id) (TEGRA210_XBAR_PART1_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (id)))
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reg_count = xbar->soc_data->reg_count;
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#define MUX2_REG(id) (TEGRA210_XBAR_PART2_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (id)))
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if (reg_count > TEGRA210_XBAR_UPDATE_MAX_REG)
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return -EINVAL;
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for (i = 0; i < reg_count; i++) {
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reg[i] = (e->reg +
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xbar->soc_data->reg_offset * i);
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reg_val = snd_soc_read(codec, reg[i]);
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val = reg_val & xbar->soc_data->mask[i];
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if (val != 0) {
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bit_pos = ffs(val) + (8 * codec->val_bytes * i);
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break;
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}
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}
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for (i = 0; i < e->max; i++) {
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if (bit_pos == e->values[i]) {
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ucontrol->value.enumerated.item[0] = i;
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break;
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}
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}
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return 0;
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}
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int tegra210_xbar_put_value_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
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struct snd_soc_dapm_widget *widget = wlist->widgets[0];
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struct snd_soc_codec *codec = widget->codec;
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struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
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unsigned int *item = ucontrol->value.enumerated.item;
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unsigned int change = 0, reg_idx = 0, value, *mask, bit_pos = 0;
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unsigned int i, wi, reg_count, reg_val = 0, update_idx = 0;
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unsigned int reg[TEGRA210_XBAR_UPDATE_MAX_REG];
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struct snd_soc_dapm_update update[TEGRA210_XBAR_UPDATE_MAX_REG];
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/* initialize the reg_count and mask from soc_data */
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reg_count = xbar->soc_data->reg_count;
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mask = (unsigned int *)xbar->soc_data->mask;
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if (item[0] >= e->max || reg_count > TEGRA210_XBAR_UPDATE_MAX_REG)
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return -EINVAL;
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value = e->values[item[0]];
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if (value) {
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/* get the register index and value to set */
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reg_idx = (value - 1) / (8 * codec->val_bytes);
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bit_pos = (value - 1) % (8 * codec->val_bytes);
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reg_val = BIT(bit_pos);
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}
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for (i = 0; i < reg_count; i++) {
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reg[i] = e->reg + xbar->soc_data->reg_offset * i;
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if (i == reg_idx) {
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change |= snd_soc_test_bits(codec, reg[i],
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mask[i], reg_val);
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/* set the selected register */
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update[reg_count - 1].reg = reg[reg_idx];
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update[reg_count - 1].mask = mask[reg_idx];
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update[reg_count - 1].val = reg_val;
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} else {
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/* accumulate the change to update the DAPM path
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when none is selected */
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change |= snd_soc_test_bits(codec, reg[i],
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mask[i], 0);
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/* clear the register when not selected */
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update[update_idx].reg = reg[i];
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update[update_idx].mask = mask[i];
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update[update_idx++].val = 0;
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}
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}
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/* power the widgets */
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if (change) {
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for (wi = 0; wi < wlist->num_widgets; wi++) {
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widget = wlist->widgets[wi];
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widget->value = reg_val;
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for (i = 0; i < reg_count; i++) {
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update[i].kcontrol = kcontrol;
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update[i].widget = widget;
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widget->dapm->update = &update[i];
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snd_soc_dapm_mux_update_power(widget,
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kcontrol, item[0], e);
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widget->dapm->update = NULL;
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}
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}
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}
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return change;
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}
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#define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
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#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
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{ .reg = xreg, .shift_l = shift, .shift_r = shift, \
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.max = xmax, .texts = xtexts, .values = xvalues, \
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.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0}
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#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, \
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xtexts, xvalues) \
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struct soc_enum name = SOC_VALUE_ENUM_WIDE(xreg, shift, \
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ARRAY_SIZE(xtexts), xtexts, xvalues)
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#define MUX_ENUM_CTRL_DECL(ename, id) \
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int ename##_regs[3] = { MUX0_REG(id), MUX1_REG(id), MUX2_REG(id) }; \
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unsigned int ename##_masks[3] = { 0xf1f03ff, 0x3f30031f, 0xff1cf313 }; \
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SOC_VALUE_ENUM_ONEHOT_DECL(ename##_enum, ename##_regs, ename##_masks, 3, \
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SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
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tegra210_xbar_mux_texts, tegra210_xbar_mux_values); \
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static const struct snd_kcontrol_new ename##_control = \
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SOC_DAPM_ENUM_ONEHOT("Route", ename##_enum)
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SOC_DAPM_ENUM_EXT("Route", ename##_enum,\
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tegra210_xbar_get_value_enum,\
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tegra210_xbar_put_value_enum)
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MUX_ENUM_CTRL_DECL(admaif1_tx, 0x00);
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MUX_ENUM_CTRL_DECL(admaif2_tx, 0x01);
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@@ -600,6 +709,11 @@ static struct snd_soc_codec_driver tegra210_xbar_codec = {
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static const struct tegra210_xbar_soc_data soc_data_tegra210 = {
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.regmap_config = &tegra210_xbar_regmap_config,
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.mask[0] = 0xf1f03ff,
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.mask[1] = 0x3f30031f,
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.mask[2] = 0xff1cf313,
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.reg_count = 3,
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.reg_offset = TEGRA210_XBAR_PART1_RX,
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};
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static const struct of_device_id tegra210_xbar_of_match[] = {
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