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Documentation: Fix error from dt_binding_check
Fix the errors generated when running the dt_binding_check on the DT binding document yaml format. Change-Id: Ie000447c97e92532755a484be02c5b347216d774 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2702785 GVS: Gerrit_Virtual_Submit
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@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/nvidia-vrs-seq.yaml#
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$id: http://devicetree.org/schemas/mfd/nvidia-vrs-pseq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA VRS sequencer driver
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@@ -28,15 +28,10 @@ properties:
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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const: 3
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description:
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The first cell is the IRQ number, the second cell is the trigger type.
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rtc:
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$ref: ../rtc/nvidia-vrs-rtc.yaml
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required:
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- compatible
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- reg
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@@ -48,8 +43,15 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define TEGRA234_IRQ_PMIC_EXT_INTR 209
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bpmp {
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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@@ -58,10 +60,6 @@ examples:
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interrupts = <GIC_SPI TEGRA234_IRQ_PMIC_EXT_INTR IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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vrs_rtc: rtc {
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status = "okay";
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};
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};
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};
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};
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@@ -32,9 +32,13 @@ additionalProperties: false
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examples:
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- |
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i2c@3180000 {
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reg = <0x3180000 0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pex9749: pex9749@5f {
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compatible = "pex9749";
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reg = <0x5f>;
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#thermal-sensor-cells = <1>;
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};
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};
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...
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@@ -17,19 +17,17 @@ allOf:
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra-wdt-t234
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- const: nvidia,tegra-wdt-t19x
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- const: nvidia,tegra-wdt-t18x
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- const: nvidia,tegra-wdt-t18x-linsim
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enum:
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- nvidia,tegra-wdt-t234
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- nvidia,tegra-wdt-t19x
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- nvidia,tegra-wdt-t18x
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- nvidia,tegra-wdt-t18x-linsim
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reg:
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maxItems: 3
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description: |
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This driver required base register of three controller as
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first entry is for the watchdog timer 0 address,
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second entry is for the address of the Timer0 and
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third entry is for the address of TKE.
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items:
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- description: Base register address and size of the watchdog timer 0.
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- description: Base register address and size of the Timer 0.
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- description: Base register address and size of the TKE.
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interrupts:
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maxItems: 1
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@@ -97,6 +95,10 @@ unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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watchdog@2190000 {
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compatible = "nvidia,tegra-wdt-t234";
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reg = <0x0 0x02190000 0x0 0x10000>, /* WDT0 */
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@@ -110,4 +112,5 @@ examples:
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timeout-sec = <120>;
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nvidia,disable-debug-reset;
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};
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};
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...
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