nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-24 02:01:36 +03:00
Code Issues Packages Projects Releases Wiki Activity

nvadsp: Add multi-instance support

Browse Source 
ADSP host driver is enhanced to be multi-instance
capable and reentrant:
 - Trailing unique identifier string in compatible DT property, like
    "adsp", "adsp1" or "aon", is used to identify the driver instances
 - Each probed driver instance is inserted into a global list, from
    which the handle can be fetched using 'nvadsp_get_handle' API
    (passing the above unique identifier as argument)
 - Above unique identifier is also used as name for the DBFS
    directory (containing files like adsp_console, adsp_logger, etc.)
 - 'nvadsp_get_handle' is the only exported API; all other APIs are
    accessible via function pointers within 'struct nvadsp_handle'
 - APIs above maintain one-is-to-one correspondence with all
    legacy APIs, with the addition of a new argument
    'struct nvadsp_handle *' at the beginning
 - Legacy APIs continue to be supported, but they are hardwired to
    work only if the kernel probes just one driver instance
 - All driver files are cleaned up to not use any global state
    variables (necessary for reentrancy)

Bug 3682950

Change-Id: Id5db49e861b2f81716ae8352b36b406654da2bbd
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3092701
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
This commit is contained in:
Viswanath L
2024-03-08 21:07:39 +00:00
committed by mobile promotions
parent 9458d6b97f
commit e2a1904d46
17 changed files with 1332 additions and 862 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/platform/tegra/nvadsp/dev.h
View File

@@ -16,7 +16,6 @@
#endif
#include <linux/interconnect.h>
#include "hwmailbox.h"
#include "amc.h"
/*
@@ -119,6 +118,9 @@ struct nvadsp_hwmb {
u32 empty_int_ie;
};
/* Max SW mailboxes */
#define NVADSP_MAILBOX_MAX 1024
/* Max no. of entries in "nvidia,cluster_mem" */
#define MAX_CLUSTER_MEM 3
@@ -163,14 +165,33 @@ struct nvadsp_chipdata {
size_t num_regs;
};
/* Maximum number of LOAD MAPPINGS supported */
#define NM_LOAD_MAPPINGS 20
struct nvadsp_mappings {
phys_addr_t da;
void *va;
int len;
};
struct nvadsp_drv_data {
/**
* API handle exposed to caller
* MUST BE THE FIRST FIELD IN THIS STRUCTURE
*/
struct nvadsp_handle nvadsp_handle;
void __iomem **base_regs;
void __iomem **base_regs_saved;
struct platform_device *pdev;
struct hwmbox_queue hwmbox_send_queue;
struct nvadsp_mbox **mboxes;
unsigned long *mbox_ids;
/* Memories allocated by subsidiary modules */
void *hwmbox_send_queue; /* struct hwmbox_queue */
void *os_priv; /* struct nvadsp_os_data */
void *app_priv; /* struct nvadsp_app_priv_struct */
struct nvadsp_mbox *mboxes[NVADSP_MAILBOX_MAX];
unsigned long mbox_ids[BITS_TO_LONGS(NVADSP_MAILBOX_MAX)];
spinlock_t mbox_lock;
#ifdef CONFIG_DEBUG_FS
@@ -259,6 +280,13 @@ struct nvadsp_drv_data {
/* "nvidia,dram_map" */
struct nvadsp_reg_map dram_map[MAX_DRAM_MAP];
struct nvadsp_mappings adsp_map[NM_LOAD_MAPPINGS];
int map_idx;
/* ARAM manager */
void *aram_handle;
struct dentry *aram_dump_debugfs_file;
};
#define ADSP_CONFIG 0x04